update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/mips/kernel/jump_label.c
..
..
@@ -40,18 +40,38 @@
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 {
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 	union mips_instruction *insn_p;
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 	union mips_instruction insn;
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+	long offset;
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 	insn_p = (union mips_instruction *)msk_isa16_mode(e->code);
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-
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-	/* Jump only works within an aligned region its delay slot is in. */
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-	BUG_ON((e->target & ~J_RANGE_MASK) != ((e->code + 4) & ~J_RANGE_MASK));
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 	/* Target must have the right alignment and ISA must be preserved. */
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 	BUG_ON((e->target & J_ALIGN_MASK) != J_ISA_BIT);
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 	if (type == JUMP_LABEL_JMP) {
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-		insn.j_format.opcode = J_ISA_BIT ? mm_j32_op : j_op;
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-		insn.j_format.target = e->target >> J_RANGE_SHIFT;
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+		if (!IS_ENABLED(CONFIG_CPU_MICROMIPS) && MIPS_ISA_REV >= 6) {
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+			offset = e->target - ((unsigned long)insn_p + 4);
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+			offset >>= 2;
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+
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+			/*
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+			 * The branch offset must fit in the instruction's 26
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+			 * bit field.
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+			 */
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+			WARN_ON((offset >= (long)BIT(25)) ||
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+				(offset < -(long)BIT(25)));
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+
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+			insn.j_format.opcode = bc6_op;
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+			insn.j_format.target = offset;
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+		} else {
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+			/*
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+			 * Jump only works within an aligned region its delay
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+			 * slot is in.
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+			 */
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+			WARN_ON((e->target & ~J_RANGE_MASK) !=
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+				((e->code + 4) & ~J_RANGE_MASK));
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+
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+			insn.j_format.opcode = J_ISA_BIT ? mm_j32_op : j_op;
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+			insn.j_format.target = e->target >> J_RANGE_SHIFT;
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+		}
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 	} else {
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 		insn.word = 0; /* nop */
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 	}