update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/mips/kernel/idle.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * MIPS idle loop and WAIT instruction support.
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  *
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@@ -5,11 +6,6 @@
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  * Copyright (C) 1994 - 2006 Ralf Baechle
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  * Copyright (C) 2003, 2004  Maciej W. Rozycki
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  * Copyright (C) 2001, 2004, 2011, 2012	 MIPS Technologies, Inc.
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License
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- * as published by the Free Software Foundation; either version
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- * 2 of the License, or (at your option) any later version.
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  */
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 #include <linux/cpu.h>
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 #include <linux/export.h>
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@@ -37,19 +33,19 @@
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 {
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 	unsigned long cfg = read_c0_conf();
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 	write_c0_conf(cfg | R30XX_CONF_HALT);
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-	local_irq_enable();
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+	raw_local_irq_enable();
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 }
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 static void __cpuidle r39xx_wait(void)
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 {
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 	if (!need_resched())
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 		write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
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-	local_irq_enable();
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+	raw_local_irq_enable();
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 }
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 void __cpuidle r4k_wait(void)
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 {
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-	local_irq_enable();
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+	raw_local_irq_enable();
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 	__r4k_wait();
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 }
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@@ -68,7 +64,7 @@
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 		"	.set	arch=r4000	\n"
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 		"	wait			\n"
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 		"	.set	pop		\n");
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-	local_irq_enable();
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+	raw_local_irq_enable();
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 }
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 /*
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@@ -88,7 +84,7 @@
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 		"	wait						\n"
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 		"	mtc0	$1, $12		# stalls until W stage	\n"
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 		"	.set	pop					\n");
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-	local_irq_enable();
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+	raw_local_irq_enable();
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 }
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 /*
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@@ -101,7 +97,8 @@
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 	unsigned long c0status = read_c0_status() | 1;	/* irqs on */
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 	__asm__(
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-	"	.set	arch=r4000			\n"
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+	"	.set	push			\n"
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+	"	.set	arch=r4000		\n"
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 	"	cache	0x14, 0(%0)		\n"
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 	"	cache	0x14, 32(%0)		\n"
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 	"	sync				\n"
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@@ -111,7 +108,7 @@
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 	"	nop				\n"
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 	"	nop				\n"
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 	"	nop				\n"
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-	"	.set	mips0			\n"
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+	"	.set	pop			\n"
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 	: : "r" (au1k_wait), "r" (c0status));
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 }
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@@ -154,7 +151,6 @@
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 		cpu_wait = r39xx_wait;
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 		break;
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 	case CPU_R4200:
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-/*	case CPU_R4300: */
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 	case CPU_R4600:
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 	case CPU_R4640:
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 	case CPU_R4650:
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@@ -176,14 +172,16 @@
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 	case CPU_CAVIUM_OCTEON_PLUS:
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 	case CPU_CAVIUM_OCTEON2:
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 	case CPU_CAVIUM_OCTEON3:
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-	case CPU_JZRISC:
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-	case CPU_LOONGSON1:
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+	case CPU_XBURST:
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+	case CPU_LOONGSON32:
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 	case CPU_XLR:
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 	case CPU_XLP:
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 		cpu_wait = r4k_wait;
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 		break;
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-	case CPU_LOONGSON3:
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-		if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2)
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+	case CPU_LOONGSON64:
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+		if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >=
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+				(PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0) ||
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+				(c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
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 			cpu_wait = r4k_wait;
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 		break;
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@@ -204,7 +202,7 @@
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 		 */
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 		if (IS_ENABLED(CONFIG_MIPS_EJTAG_FDC_TTY))
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 			break;
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-		/* fall through */
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+		fallthrough;
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 	case CPU_M14KC:
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 	case CPU_M14KEC:
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 	case CPU_24K:
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@@ -259,7 +257,7 @@
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 	if (cpu_wait)
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 		cpu_wait();
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 	else
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-		local_irq_enable();
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+		raw_local_irq_enable();
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 }
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 #ifdef CONFIG_CPU_IDLE