update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/mips/kernel/branch.c
..
..
@@ -20,6 +20,8 @@
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20
 #include <asm/ptrace.h>
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 #include <linux/uaccess.h>
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22
 
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+#include "probes-common.h"
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+
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 /*
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  * Calculate and return exception PC in case of branch delay slot
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  * for microMIPS and MIPS16e. It does not clear the ISA mode bit.
..
..
@@ -32,7 +34,7 @@
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 	/* Calculate exception PC in branch delay slot. */
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 	if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) {
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 		/* This should never happen because delay slot was checked. */
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-		force_sig(SIGSEGV, current);
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+		force_sig(SIGSEGV);
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 		return epc;
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 	}
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 	if (cpu_has_mips16) {
..
..
@@ -58,9 +60,7 @@
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 		       unsigned long *contpc)
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 {
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 	union mips_instruction insn = (union mips_instruction)dec_insn.insn;
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-	int bc_false = 0;
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-	unsigned int fcr31;
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-	unsigned int bit;
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+	int __maybe_unused bc_false = 0;
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64
 
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 	if (!cpu_has_mmips)
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 		return 0;
..
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@@ -92,7 +92,7 @@
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 			regs->regs[31] = regs->cp0_epc +
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 				dec_insn.pc_inc +
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 				dec_insn.next_pc_inc;
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-			/* Fall through */
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+			fallthrough;
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 		case mm_bltz_op:
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 			if ((long)regs->regs[insn.mm_i_format.rs] < 0)
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 				*contpc = regs->cp0_epc +
..
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@@ -108,7 +108,7 @@
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 			regs->regs[31] = regs->cp0_epc +
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 					dec_insn.pc_inc +
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 					dec_insn.next_pc_inc;
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-			/* Fall through */
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+			fallthrough;
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 		case mm_bgez_op:
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 			if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
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 				*contpc = regs->cp0_epc +
..
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@@ -139,10 +139,14 @@
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 					dec_insn.pc_inc +
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 					dec_insn.next_pc_inc;
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 			return 1;
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+#ifdef CONFIG_MIPS_FP_SUPPORT
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 		case mm_bc2f_op:
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-		case mm_bc1f_op:
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+		case mm_bc1f_op: {
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+			unsigned int fcr31;
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+			unsigned int bit;
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+
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 			bc_false = 1;
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-			/* Fall through */
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+			fallthrough;
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 		case mm_bc2t_op:
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 		case mm_bc1t_op:
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 			preempt_disable();
..
..
@@ -167,6 +171,8 @@
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 					dec_insn.pc_inc + dec_insn.next_pc_inc;
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 			return 1;
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 		}
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+#endif /* CONFIG_MIPS_FP_SUPPORT */
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+		}
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 		break;
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 	case mm_pool16c_op:
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 		switch (insn.mm_i_format.rt) {
..
..
@@ -174,7 +180,7 @@
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 		case mm_jalrs16_op:
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 			regs->regs[31] = regs->cp0_epc +
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 				dec_insn.pc_inc + dec_insn.next_pc_inc;
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-			/* Fall through */
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+			fallthrough;
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 		case mm_jr16_op:
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 			*contpc = regs->regs[insn.mm_i_format.rs];
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 			return 1;
..
..
@@ -235,7 +241,7 @@
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 	case mm_jal32_op:
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 		regs->regs[31] = regs->cp0_epc +
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 			dec_insn.pc_inc + dec_insn.next_pc_inc;
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-		/* Fall through */
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+		fallthrough;
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 	case mm_j32_op:
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 		*contpc = regs->cp0_epc + dec_insn.pc_inc;
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 		*contpc >>= 27;
..
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@@ -301,7 +307,7 @@
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 	return 0;
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 sigsegv:
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-	force_sig(SIGSEGV, current);
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+	force_sig(SIGSEGV);
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 	return -EFAULT;
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 }
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@@ -324,7 +330,7 @@
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 	/* Read the instruction. */
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 	addr = (u16 __user *)msk_isa16_mode(epc);
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 	if (__get_user(inst.full, addr)) {
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-		force_sig(SIGSEGV, current);
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+		force_sig(SIGSEGV);
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 		return -EFAULT;
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 	}
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@@ -339,7 +345,7 @@
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 	case MIPS16e_jal_op:
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 		addr += 1;
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 		if (__get_user(inst2, addr)) {
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-			force_sig(SIGSEGV, current);
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+			force_sig(SIGSEGV);
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 			return -EFAULT;
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 		}
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 		fullinst = ((unsigned)inst.full << 16) | inst2;
..
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@@ -416,8 +422,8 @@
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 int __compute_return_epc_for_insn(struct pt_regs *regs,
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 				   union mips_instruction insn)
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 {
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-	unsigned int bit, fcr31, dspcontrol, reg;
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 	long epc = regs->cp0_epc;
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+	unsigned int dspcontrol;
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 	int ret = 0;
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428
 
423
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 	switch (insn.i_format.opcode) {
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@@ -428,7 +434,7 @@
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 		switch (insn.r_format.func) {
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 		case jalr_op:
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 			regs->regs[insn.r_format.rd] = epc + 8;
431
-			/* Fall through */
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+			fallthrough;
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 		case jr_op:
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 			if (NO_R6EMU && insn.r_format.func == jr_op)
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 				goto sigill_r2r6;
..
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@@ -447,6 +453,7 @@
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 		case bltzl_op:
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 			if (NO_R6EMU)
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 				goto sigill_r2r6;
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+			fallthrough;
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 		case bltz_op:
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 			if ((long)regs->regs[insn.i_format.rs] < 0) {
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 				epc = epc + 4 + (insn.i_format.simmediate << 2);
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@@ -460,6 +467,7 @@
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 		case bgezl_op:
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 			if (NO_R6EMU)
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 				goto sigill_r2r6;
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+			fallthrough;
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 		case bgez_op:
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 			if ((long)regs->regs[insn.i_format.rs] >= 0) {
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 				epc = epc + 4 + (insn.i_format.simmediate << 2);
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@@ -555,6 +563,7 @@
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 	case jalx_op:
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 	case jal_op:
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 		regs->regs[31] = regs->cp0_epc + 8;
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+		fallthrough;
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 	case j_op:
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 		epc += 4;
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 		epc >>= 28;
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@@ -571,6 +580,7 @@
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 	case beql_op:
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 		if (NO_R6EMU)
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 			goto sigill_r2r6;
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+		fallthrough;
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 	case beq_op:
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 		if (regs->regs[insn.i_format.rs] ==
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 		    regs->regs[insn.i_format.rt]) {
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@@ -585,6 +595,7 @@
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 	case bnel_op:
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 		if (NO_R6EMU)
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 			goto sigill_r2r6;
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+		fallthrough;
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 	case bne_op:
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 		if (regs->regs[insn.i_format.rs] !=
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 		    regs->regs[insn.i_format.rt]) {
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@@ -599,6 +610,7 @@
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 	case blezl_op: /* not really i_format */
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 		if (!insn.i_format.rt && NO_R6EMU)
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 			goto sigill_r2r6;
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+		fallthrough;
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 	case blez_op:
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 		/*
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 		 * Compact branches for R6 for the
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@@ -634,6 +646,7 @@
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 	case bgtzl_op:
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 		if (!insn.i_format.rt && NO_R6EMU)
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 			goto sigill_r2r6;
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+		fallthrough;
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 	case bgtz_op:
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 		/*
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 		 * Compact branches for R6 for the
..
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@@ -667,23 +680,18 @@
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 		regs->cp0_epc = epc;
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 		break;
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682
 
683
+#ifdef CONFIG_MIPS_FP_SUPPORT
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 	/*
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 	 * And now the FPA/cp1 branch instructions.
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 	 */
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-	case cop1_op:
687
+	case cop1_op: {
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+		unsigned int bit, fcr31, reg;
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+
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 		if (cpu_has_mips_r6 &&
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 		    ((insn.i_format.rs == bc1eqz_op) ||
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 		     (insn.i_format.rs == bc1nez_op))) {
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-			if (!used_math()) { /* First time FPU user */
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-				ret = init_fpu();
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-				if (ret && NO_R6EMU) {
680
-					ret = -ret;
681
-					break;
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-				}
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-				ret = 0;
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-				set_used_math();
685
-			}
686
-			lose_fpu(1);    /* Save FPU state for the emulator. */
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+			if (!init_fp_ctx(current))
694
+				lose_fpu(1);
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695
 			reg = insn.i_format.rt;
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 			bit = get_fpr32(&current->thread.fpu.fpr[reg], 0) & 0x1;
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 			if (insn.i_format.rs == bc1eqz_op)
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@@ -736,6 +744,9 @@
736
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 			}
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 			break;
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 		}
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+	}
748
+#endif /* CONFIG_MIPS_FP_SUPPORT */
749
+
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 #ifdef CONFIG_CPU_CAVIUM_OCTEON
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 	case lwc2_op: /* This is bbit0 on Octeon */
741
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 		if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
..
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@@ -820,17 +831,17 @@
820
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 sigill_dsp:
821
832
 	pr_debug("%s: DSP branch but not DSP ASE - sending SIGILL.\n",
822
833
 		 current->comm);
823
-	force_sig(SIGILL, current);
834
+	force_sig(SIGILL);
824
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 	return -EFAULT;
825
836
 sigill_r2r6:
826
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 	pr_debug("%s: R2 branch but r2-to-r6 emulator is not present - sending SIGILL.\n",
827
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 		 current->comm);
828
-	force_sig(SIGILL, current);
839
+	force_sig(SIGILL);
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 	return -EFAULT;
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 sigill_r6:
831
842
 	pr_debug("%s: R6 branch but no MIPSr6 ISA support - sending SIGILL.\n",
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843
 		 current->comm);
833
-	force_sig(SIGILL, current);
844
+	force_sig(SIGILL);
834
845
 	return -EFAULT;
835
846
 }
836
847
 EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
..
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@@ -850,7 +861,7 @@
850
861
 	 */
851
862
 	addr = (unsigned int __user *) epc;
852
863
 	if (__get_user(insn.word, addr)) {
853
-		force_sig(SIGSEGV, current);
864
+		force_sig(SIGSEGV);
854
865
 		return -EFAULT;
855
866
 	}
856
867
 
..
..
@@ -858,7 +869,7 @@
858
869
 
859
870
 unaligned:
860
871
 	printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
861
-	force_sig(SIGBUS, current);
872
+	force_sig(SIGBUS);
862
873
 	return -EFAULT;
863
874
 }
864
875