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2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/arch/mips/include/asm/pci/bridge.h
....@@ -45,18 +45,21 @@
4545 
4646 #ifndef __ASSEMBLY__
4747 
48
-/*
49
- * All accesses to bridge hardware registers must be done
50
- * using 32-bit loads and stores.
51
- */
52
-typedef u32	bridgereg_t;
48
+#define ATE_V		0x01
49
+#define ATE_CO		0x02
50
+#define ATE_PREC	0x04
51
+#define ATE_PREF	0x08
52
+#define ATE_BAR		0x10
5353 
54
-typedef u64	bridge_ate_t;
54
+#define ATE_PFNSHIFT		12
55
+#define ATE_TIDSHIFT		8
56
+#define ATE_RMFSHIFT		48
5557 
56
-/* pointers to bridge ATEs
57
- * are always "pointer to volatile"
58
- */
59
-typedef volatile bridge_ate_t  *bridge_ate_p;
58
+#define mkate(xaddr, xid, attr) (((xaddr) & 0x0000fffffffff000ULL) | \
59
+				 ((xid)<<ATE_TIDSHIFT) | \
60
+				 (attr))
61
+
62
+#define BRIDGE_INTERNAL_ATES	128
6063 
6164 /*
6265  * It is generally preferred that hardware registers on the bridge
....@@ -65,7 +68,7 @@
6568  * Generated from Bridge spec dated 04oct95
6669  */
6770 
68
-typedef volatile struct bridge_s {
71
+struct bridge_regs {
6972 	/* Local Registers			       0x000000-0x00FFFF */
7073 
7174 	/* standard widget configuration	       0x000000-0x000057 */
....@@ -86,105 +89,105 @@
8689 #define b_wid_tflush			b_widget.w_tflush
8790 
8891 	/* bridge-specific widget configuration 0x000058-0x00007F */
89
-	bridgereg_t	    _pad_000058;
90
-	bridgereg_t	    b_wid_aux_err;		/* 0x00005C */
91
-	bridgereg_t	    _pad_000060;
92
-	bridgereg_t	    b_wid_resp_upper;		/* 0x000064 */
93
-	bridgereg_t	    _pad_000068;
94
-	bridgereg_t	    b_wid_resp_lower;		/* 0x00006C */
95
-	bridgereg_t	    _pad_000070;
96
-	bridgereg_t	    b_wid_tst_pin_ctrl;		/* 0x000074 */
97
-	bridgereg_t	_pad_000078[2];
92
+	u32	_pad_000058;
93
+	u32	b_wid_aux_err;		/* 0x00005C */
94
+	u32	_pad_000060;
95
+	u32	b_wid_resp_upper;		/* 0x000064 */
96
+	u32	_pad_000068;
97
+	u32	b_wid_resp_lower;		/* 0x00006C */
98
+	u32	_pad_000070;
99
+	u32	 b_wid_tst_pin_ctrl;		/* 0x000074 */
100
+	u32	_pad_000078[2];
98101 
99102 	/* PMU & Map 0x000080-0x00008F */
100
-	bridgereg_t	_pad_000080;
101
-	bridgereg_t	b_dir_map;			/* 0x000084 */
102
-	bridgereg_t	_pad_000088[2];
103
+	u32	_pad_000080;
104
+	u32	b_dir_map;			/* 0x000084 */
105
+	u32	_pad_000088[2];
103106 
104107 	/* SSRAM 0x000090-0x00009F */
105
-	bridgereg_t	_pad_000090;
106
-	bridgereg_t	b_ram_perr;			/* 0x000094 */
107
-	bridgereg_t	_pad_000098[2];
108
+	u32	_pad_000090;
109
+	u32	b_ram_perr;			/* 0x000094 */
110
+	u32	_pad_000098[2];
108111 
109112 	/* Arbitration 0x0000A0-0x0000AF */
110
-	bridgereg_t	_pad_0000A0;
111
-	bridgereg_t	b_arb;				/* 0x0000A4 */
112
-	bridgereg_t	_pad_0000A8[2];
113
+	u32	_pad_0000A0;
114
+	u32	b_arb;				/* 0x0000A4 */
115
+	u32	_pad_0000A8[2];
113116 
114117 	/* Number In A Can 0x0000B0-0x0000BF */
115
-	bridgereg_t	_pad_0000B0;
116
-	bridgereg_t	b_nic;				/* 0x0000B4 */
117
-	bridgereg_t	_pad_0000B8[2];
118
+	u32	_pad_0000B0;
119
+	u32	b_nic;				/* 0x0000B4 */
120
+	u32	_pad_0000B8[2];
118121 
119122 	/* PCI/GIO 0x0000C0-0x0000FF */
120
-	bridgereg_t	_pad_0000C0;
121
-	bridgereg_t	b_bus_timeout;			/* 0x0000C4 */
123
+	u32	_pad_0000C0;
124
+	u32	b_bus_timeout;			/* 0x0000C4 */
122125 #define b_pci_bus_timeout b_bus_timeout
123126 
124
-	bridgereg_t	_pad_0000C8;
125
-	bridgereg_t	b_pci_cfg;			/* 0x0000CC */
126
-	bridgereg_t	_pad_0000D0;
127
-	bridgereg_t	b_pci_err_upper;		/* 0x0000D4 */
128
-	bridgereg_t	_pad_0000D8;
129
-	bridgereg_t	b_pci_err_lower;		/* 0x0000DC */
130
-	bridgereg_t	_pad_0000E0[8];
127
+	u32	_pad_0000C8;
128
+	u32	b_pci_cfg;			/* 0x0000CC */
129
+	u32	_pad_0000D0;
130
+	u32	b_pci_err_upper;		/* 0x0000D4 */
131
+	u32	_pad_0000D8;
132
+	u32	b_pci_err_lower;		/* 0x0000DC */
133
+	u32	_pad_0000E0[8];
131134 #define b_gio_err_lower b_pci_err_lower
132135 #define b_gio_err_upper b_pci_err_upper
133136 
134137 	/* Interrupt 0x000100-0x0001FF */
135
-	bridgereg_t	_pad_000100;
136
-	bridgereg_t	b_int_status;			/* 0x000104 */
137
-	bridgereg_t	_pad_000108;
138
-	bridgereg_t	b_int_enable;			/* 0x00010C */
139
-	bridgereg_t	_pad_000110;
140
-	bridgereg_t	b_int_rst_stat;			/* 0x000114 */
141
-	bridgereg_t	_pad_000118;
142
-	bridgereg_t	b_int_mode;			/* 0x00011C */
143
-	bridgereg_t	_pad_000120;
144
-	bridgereg_t	b_int_device;			/* 0x000124 */
145
-	bridgereg_t	_pad_000128;
146
-	bridgereg_t	b_int_host_err;			/* 0x00012C */
138
+	u32	_pad_000100;
139
+	u32	b_int_status;			/* 0x000104 */
140
+	u32	_pad_000108;
141
+	u32	b_int_enable;			/* 0x00010C */
142
+	u32	_pad_000110;
143
+	u32	b_int_rst_stat;			/* 0x000114 */
144
+	u32	_pad_000118;
145
+	u32	b_int_mode;			/* 0x00011C */
146
+	u32	_pad_000120;
147
+	u32	b_int_device;			/* 0x000124 */
148
+	u32	_pad_000128;
149
+	u32	b_int_host_err;			/* 0x00012C */
147150 
148151 	struct {
149
-		bridgereg_t	__pad;			/* 0x0001{30,,,68} */
150
-		bridgereg_t	addr;			/* 0x0001{34,,,6C} */
152
+		u32	__pad;			/* 0x0001{30,,,68} */
153
+		u32	addr;			/* 0x0001{34,,,6C} */
151154 	} b_int_addr[8];				/* 0x000130 */
152155 
153
-	bridgereg_t	_pad_000170[36];
156
+	u32	_pad_000170[36];
154157 
155158 	/* Device 0x000200-0x0003FF */
156159 	struct {
157
-		bridgereg_t	__pad;			/* 0x0002{00,,,38} */
158
-		bridgereg_t	reg;			/* 0x0002{04,,,3C} */
160
+		u32	__pad;			/* 0x0002{00,,,38} */
161
+		u32	reg;			/* 0x0002{04,,,3C} */
159162 	} b_device[8];					/* 0x000200 */
160163 
161164 	struct {
162
-		bridgereg_t	__pad;			/* 0x0002{40,,,78} */
163
-		bridgereg_t	reg;			/* 0x0002{44,,,7C} */
165
+		u32	__pad;			/* 0x0002{40,,,78} */
166
+		u32	reg;			/* 0x0002{44,,,7C} */
164167 	} b_wr_req_buf[8];				/* 0x000240 */
165168 
166169 	struct {
167
-		bridgereg_t	__pad;			/* 0x0002{80,,,88} */
168
-		bridgereg_t	reg;			/* 0x0002{84,,,8C} */
170
+		u32	__pad;			/* 0x0002{80,,,88} */
171
+		u32	reg;			/* 0x0002{84,,,8C} */
169172 	} b_rrb_map[2];					/* 0x000280 */
170173 #define b_even_resp	b_rrb_map[0].reg		/* 0x000284 */
171174 #define b_odd_resp	b_rrb_map[1].reg		/* 0x00028C */
172175 
173
-	bridgereg_t	_pad_000290;
174
-	bridgereg_t	b_resp_status;			/* 0x000294 */
175
-	bridgereg_t	_pad_000298;
176
-	bridgereg_t	b_resp_clear;			/* 0x00029C */
176
+	u32	_pad_000290;
177
+	u32	b_resp_status;			/* 0x000294 */
178
+	u32	_pad_000298;
179
+	u32	b_resp_clear;			/* 0x00029C */
177180 
178
-	bridgereg_t	_pad_0002A0[24];
181
+	u32	_pad_0002A0[24];
179182 
180183 	char		_pad_000300[0x10000 - 0x000300];
181184 
182185 	/* Internal Address Translation Entry RAM 0x010000-0x0103FF */
183186 	union {
184
-		bridge_ate_t	wr;			/* write-only */
187
+		u64	wr;			/* write-only */
185188 		struct {
186
-			bridgereg_t	_p_pad;
187
-			bridgereg_t	rd;		/* read-only */
189
+			u32	_p_pad;
190
+			u32	rd;		/* read-only */
188191 		}			hi;
189192 	}			    b_int_ate_ram[128];
190193 
....@@ -192,8 +195,8 @@
192195 
193196 	/* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */
194197 	struct {
195
-		bridgereg_t	_p_pad;
196
-		bridgereg_t	rd;		/* read-only */
198
+		u32	_p_pad;
199
+		u32	rd;		/* read-only */
197200 	} b_int_ate_ram_lo[128];
198201 
199202 	char	_pad_011400[0x20000 - 0x011400];
....@@ -212,7 +215,7 @@
212215 		} f[8];
213216 	} b_type0_cfg_dev[8];					/* 0x020000 */
214217 
215
-    /* PCI Type 1 Configuration Space 0x028000-0x028FFF */
218
+	/* PCI Type 1 Configuration Space 0x028000-0x028FFF */
216219 	union {				/* make all access sizes available. */
217220 		u8	c[0x1000 / 1];
218221 		u16	s[0x1000 / 2];
....@@ -233,7 +236,7 @@
233236 	u8	_pad_030007[0x04fff8];			/* 0x030008-0x07FFFF */
234237 
235238 	/* External Address Translation Entry RAM 0x080000-0x0FFFFF */
236
-	bridge_ate_t	b_ext_ate_ram[0x10000];
239
+	u64	b_ext_ate_ram[0x10000];
237240 
238241 	/* Reserved 0x100000-0x1FFFFF */
239242 	char	_pad_100000[0x200000-0x100000];
....@@ -259,13 +262,13 @@
259262 		u32	l[0x400000 / 4];	/* read-only */
260263 		u64	d[0x400000 / 8];	/* read-only */
261264 	} b_external_flash;			/* 0xC00000 */
262
-} bridge_t;
265
+};
263266 
264267 /*
265268  * Field formats for Error Command Word and Auxiliary Error Command Word
266269  * of bridge.
267270  */
268
-typedef struct bridge_err_cmdword_s {
271
+struct bridge_err_cmdword {
269272 	union {
270273 		u32		cmd_word;
271274 		struct {
....@@ -282,7 +285,7 @@
282285 				rsvd:8;
283286 		} berr_st;
284287 	} berr_un;
285
-} bridge_err_cmdword_t;
288
+};
286289 
287290 #define berr_field	berr_un.berr_st
288291 #endif /* !__ASSEMBLY__ */
....@@ -290,7 +293,7 @@
290293 /*
291294  * The values of these macros can and should be crosschecked
292295  * regularly against the offsets of the like-named fields
293
- * within the "bridge_t" structure above.
296
+ * within the bridge_regs structure above.
294297  */
295298 
296299 /* Byte offset macros for Bridge internal registers */
....@@ -797,59 +800,26 @@
797800 #define PCI64_ATTR_RMF_MASK	0x00ff000000000000
798801 #define PCI64_ATTR_RMF_SHFT	48
799802 
800
-#ifndef __ASSEMBLY__
801
-/* Address translation entry for mapped pci32 accesses */
802
-typedef union ate_u {
803
-	u64	ent;
804
-	struct ate_s {
805
-		u64	rmf:16;
806
-		u64	addr:36;
807
-		u64	targ:4;
808
-		u64	reserved:3;
809
-		u64	barrier:1;
810
-		u64	prefetch:1;
811
-		u64	precise:1;
812
-		u64	coherent:1;
813
-		u64	valid:1;
814
-	} field;
815
-} ate_t;
816
-#endif /* !__ASSEMBLY__ */
817
-
818
-#define ATE_V		0x01
819
-#define ATE_CO		0x02
820
-#define ATE_PREC	0x04
821
-#define ATE_PREF	0x08
822
-#define ATE_BAR		0x10
823
-
824
-#define ATE_PFNSHIFT		12
825
-#define ATE_TIDSHIFT		8
826
-#define ATE_RMFSHIFT		48
827
-
828
-#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \
829
-				((xid)<<ATE_TIDSHIFT) | \
830
-				(attr)
831
-
832
-#define BRIDGE_INTERNAL_ATES	128
833
-
834803 struct bridge_controller {
835
-	struct pci_controller	pc;
836
-	struct resource		mem;
837
-	struct resource		io;
838804 	struct resource		busn;
839
-	bridge_t		*base;
805
+	struct bridge_regs	*base;
806
+	unsigned long		baddr;
807
+	unsigned long		intr_addr;
808
+	struct irq_domain	*domain;
809
+	unsigned int		pci_int[8][2];
810
+	unsigned int		int_mapping[8][2];
811
+	u32			ioc3_sid[8];
840812 	nasid_t			nasid;
841
-	unsigned int		widget_id;
842
-	unsigned int		irq_cpu;
843
-	u64			baddr;
844
-	unsigned int		pci_int[8];
845813 };
846814 
847815 #define BRIDGE_CONTROLLER(bus) \
848816 	((struct bridge_controller *)((bus)->sysdata))
849817 
850
-extern void register_bridge_irq(unsigned int irq);
851
-extern int request_bridge_irq(struct bridge_controller *bc);
852
-
853
-extern struct pci_ops bridge_pci_ops;
818
+#define bridge_read(bc, reg)		__raw_readl(&bc->base->reg)
819
+#define bridge_write(bc, reg, val)	__raw_writel(val, &bc->base->reg)
820
+#define bridge_set(bc, reg, val)	\
821
+	__raw_writel(__raw_readl(&bc->base->reg) | (val), &bc->base->reg)
822
+#define bridge_clr(bc, reg, val)	\
823
+	__raw_writel(__raw_readl(&bc->base->reg) & ~(val), &bc->base->reg)
854824 
855825 #endif /* _ASM_PCI_BRIDGE_H */