| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | 3 | * Atheros AR71XX/AR724X/AR913X specific setup |
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| 3 | 4 | * |
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| .. | .. |
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| 6 | 7 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
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| 7 | 8 | * |
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| 8 | 9 | * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP |
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| 9 | | - * |
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| 10 | | - * This program is free software; you can redistribute it and/or modify it |
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| 11 | | - * under the terms of the GNU General Public License version 2 as published |
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| 12 | | - * by the Free Software Foundation. |
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| 13 | 10 | */ |
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| 14 | 11 | |
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| 15 | 12 | #include <linux/kernel.h> |
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| 16 | 13 | #include <linux/init.h> |
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| 17 | | -#include <linux/bootmem.h> |
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| 14 | +#include <linux/io.h> |
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| 15 | +#include <linux/memblock.h> |
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| 18 | 16 | #include <linux/err.h> |
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| 19 | 17 | #include <linux/clk.h> |
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| 20 | | -#include <linux/clk-provider.h> |
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| 18 | +#include <linux/of_clk.h> |
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| 21 | 19 | #include <linux/of_fdt.h> |
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| 20 | +#include <linux/irqchip.h> |
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| 22 | 21 | |
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| 23 | 22 | #include <asm/bootinfo.h> |
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| 24 | 23 | #include <asm/idle.h> |
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| 25 | 24 | #include <asm/time.h> /* for mips_hpt_frequency */ |
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| 26 | 25 | #include <asm/reboot.h> /* for _machine_{restart,halt} */ |
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| 27 | | -#include <asm/mips_machine.h> |
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| 28 | 26 | #include <asm/prom.h> |
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| 29 | 27 | #include <asm/fw/fw.h> |
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| 30 | 28 | |
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| 31 | 29 | #include <asm/mach-ath79/ath79.h> |
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| 32 | 30 | #include <asm/mach-ath79/ar71xx_regs.h> |
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| 33 | 31 | #include "common.h" |
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| 34 | | -#include "dev-common.h" |
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| 35 | | -#include "machtypes.h" |
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| 36 | 32 | |
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| 37 | 33 | #define ATH79_SYS_TYPE_LEN 64 |
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| 38 | 34 | |
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| .. | .. |
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| 156 | 152 | case REV_ID_MAJOR_QCA9533_V2: |
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| 157 | 153 | ver = 2; |
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| 158 | 154 | ath79_soc_rev = 2; |
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| 159 | | - /* drop through */ |
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| 160 | | - |
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| 155 | + fallthrough; |
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| 161 | 156 | case REV_ID_MAJOR_QCA9533: |
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| 162 | 157 | ath79_soc = ATH79_SOC_QCA9533; |
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| 163 | 158 | chip = "9533"; |
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| .. | .. |
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| 211 | 206 | return ath79_sys_type; |
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| 212 | 207 | } |
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| 213 | 208 | |
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| 214 | | -int get_c0_perfcount_int(void) |
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| 215 | | -{ |
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| 216 | | - return ATH79_MISC_IRQ(5); |
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| 217 | | -} |
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| 218 | | -EXPORT_SYMBOL_GPL(get_c0_perfcount_int); |
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| 219 | | - |
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| 220 | 209 | unsigned int get_c0_compare_int(void) |
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| 221 | 210 | { |
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| 222 | 211 | return CP0_LEGACY_COMPARE_IRQ; |
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| .. | .. |
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| 235 | 224 | else if (fw_passed_dtb) |
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| 236 | 225 | __dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb)); |
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| 237 | 226 | |
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| 238 | | - if (mips_machtype != ATH79_MACH_GENERIC_OF) { |
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| 239 | | - ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE, |
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| 240 | | - AR71XX_RESET_SIZE); |
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| 241 | | - ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE, |
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| 242 | | - AR71XX_PLL_SIZE); |
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| 243 | | - ath79_detect_sys_type(); |
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| 244 | | - ath79_ddr_ctrl_init(); |
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| 227 | + ath79_reset_base = ioremap(AR71XX_RESET_BASE, |
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| 228 | + AR71XX_RESET_SIZE); |
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| 229 | + ath79_pll_base = ioremap(AR71XX_PLL_BASE, |
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| 230 | + AR71XX_PLL_SIZE); |
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| 231 | + ath79_detect_sys_type(); |
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| 232 | + ath79_ddr_ctrl_init(); |
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| 245 | 233 | |
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| 246 | | - detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX); |
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| 234 | + detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX); |
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| 247 | 235 | |
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| 248 | | - /* OF machines should use the reset driver */ |
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| 249 | | - _machine_restart = ath79_restart; |
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| 250 | | - } |
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| 251 | | - |
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| 236 | + _machine_restart = ath79_restart; |
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| 252 | 237 | _machine_halt = ath79_halt; |
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| 253 | 238 | pm_power_off = ath79_halt; |
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| 254 | 239 | } |
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| 255 | 240 | |
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| 256 | | -static void __init ath79_of_plat_time_init(void) |
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| 241 | +void __init plat_time_init(void) |
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| 257 | 242 | { |
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| 258 | 243 | struct device_node *np; |
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| 259 | 244 | struct clk *clk; |
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| .. | .. |
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| 283 | 268 | clk_put(clk); |
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| 284 | 269 | } |
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| 285 | 270 | |
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| 286 | | -void __init plat_time_init(void) |
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| 271 | +void __init arch_init_irq(void) |
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| 287 | 272 | { |
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| 288 | | - unsigned long cpu_clk_rate; |
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| 289 | | - unsigned long ahb_clk_rate; |
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| 290 | | - unsigned long ddr_clk_rate; |
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| 291 | | - unsigned long ref_clk_rate; |
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| 292 | | - |
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| 293 | | - if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) { |
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| 294 | | - ath79_of_plat_time_init(); |
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| 295 | | - return; |
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| 296 | | - } |
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| 297 | | - |
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| 298 | | - ath79_clocks_init(); |
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| 299 | | - |
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| 300 | | - cpu_clk_rate = ath79_get_sys_clk_rate("cpu"); |
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| 301 | | - ahb_clk_rate = ath79_get_sys_clk_rate("ahb"); |
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| 302 | | - ddr_clk_rate = ath79_get_sys_clk_rate("ddr"); |
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| 303 | | - ref_clk_rate = ath79_get_sys_clk_rate("ref"); |
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| 304 | | - |
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| 305 | | - pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n", |
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| 306 | | - cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000, |
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| 307 | | - ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000, |
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| 308 | | - ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000, |
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| 309 | | - ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000); |
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| 310 | | - |
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| 311 | | - mips_hpt_frequency = cpu_clk_rate / 2; |
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| 273 | + irqchip_init(); |
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| 312 | 274 | } |
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| 313 | | - |
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| 314 | | -static int __init ath79_setup(void) |
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| 315 | | -{ |
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| 316 | | - if (mips_machtype == ATH79_MACH_GENERIC_OF) |
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| 317 | | - return 0; |
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| 318 | | - |
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| 319 | | - ath79_gpio_init(); |
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| 320 | | - ath79_register_uart(); |
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| 321 | | - ath79_register_wdt(); |
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| 322 | | - |
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| 323 | | - mips_machine_setup(); |
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| 324 | | - |
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| 325 | | - return 0; |
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| 326 | | -} |
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| 327 | | - |
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| 328 | | -arch_initcall(ath79_setup); |
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| 329 | 275 | |
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| 330 | 276 | void __init device_tree_init(void) |
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| 331 | 277 | { |
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| 332 | 278 | unflatten_and_copy_device_tree(); |
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| 333 | 279 | } |
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| 334 | | - |
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| 335 | | -MIPS_MACHINE(ATH79_MACH_GENERIC, |
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| 336 | | - "Generic", |
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| 337 | | - "Generic AR71XX/AR724X/AR913X based board", |
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| 338 | | - NULL); |
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| 339 | | - |
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| 340 | | -MIPS_MACHINE(ATH79_MACH_GENERIC_OF, |
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| 341 | | - "DTB", |
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| 342 | | - "Generic AR71XX/AR724X/AR913X based board (DT)", |
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| 343 | | - NULL); |
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