update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/arm64/mm/proc.S
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@@ -47,17 +47,19 @@
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 #ifdef CONFIG_KASAN_HW_TAGS
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 #define TCR_MTE_FLAGS SYS_TCR_EL1_TCMA1 | TCR_TBI1 | TCR_TBID1
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-#else
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+#elif defined(CONFIG_ARM64_MTE)
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 /*
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  * The mte_zero_clear_page_tags() implementation uses DC GZVA, which relies on
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  * TBI being enabled at EL1.
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  */
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 #define TCR_MTE_FLAGS TCR_TBI1 | TCR_TBID1
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+#else
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+#define TCR_MTE_FLAGS 0
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 #endif
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 /*
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  * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and
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- * changed during __cpu_setup to Normal Tagged if the system supports MTE.
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+ * changed during mte_cpu_setup to Normal Tagged if the system supports MTE.
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  */
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 #define MAIR_EL1_SET							\
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 	(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |	\
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@@ -427,47 +429,6 @@
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 	 * Memory region attributes
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 	 */
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 	mov_q	x5, MAIR_EL1_SET
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-#ifdef CONFIG_ARM64_MTE
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-	mte_tcr	.req	x20
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-
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-	mov	mte_tcr, #0
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-
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-	/*
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-	 * Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported
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-	 * (ID_AA64PFR1_EL1[11:8] > 1).
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-	 */
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-	mrs	x10, ID_AA64PFR1_EL1
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-	ubfx	x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4
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-	cmp	x10, #ID_AA64PFR1_MTE
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-	b.lt	1f
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-
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-	/* Normal Tagged memory type at the corresponding MAIR index */
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-	mov	x10, #MAIR_ATTR_NORMAL_TAGGED
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-	bfi	x5, x10, #(8 *  MT_NORMAL_TAGGED), #8
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-
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-	mov	x10, #KERNEL_GCR_EL1
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-	msr_s	SYS_GCR_EL1, x10
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-
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-	/*
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-	 * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then
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-	 * RGSR_EL1.SEED must be non-zero for IRG to produce
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-	 * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we
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-	 * must initialize it.
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-	 */
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-	mrs	x10, CNTVCT_EL0
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-	ands	x10, x10, #SYS_RGSR_EL1_SEED_MASK
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-	csinc	x10, x10, xzr, ne
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-	lsl	x10, x10, #SYS_RGSR_EL1_SEED_SHIFT
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-	msr_s	SYS_RGSR_EL1, x10
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-
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-	/* clear any pending tag check faults in TFSR*_EL1 */
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-	msr_s	SYS_TFSR_EL1, xzr
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-	msr_s	SYS_TFSRE0_EL1, xzr
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-
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-	/* set the TCR_EL1 bits */
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-	mov_q	mte_tcr, TCR_MTE_FLAGS
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-1:
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-#endif
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 	msr	mair_el1, x5
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 	/*
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 	 * Set/prepare TCR and TTBR. TCR_EL1.T1SZ gets further
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@@ -475,11 +436,8 @@
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 	 */
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 	mov_q	x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
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 			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
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-			TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS
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-#ifdef CONFIG_ARM64_MTE
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-	orr	x10, x10, mte_tcr
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-	.unreq	mte_tcr
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-#endif
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+			TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS | TCR_MTE_FLAGS
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+
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 	tcr_clear_errata_bits x10, x9, x5
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 #ifdef CONFIG_ARM64_VA_BITS_52