update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/arm64/kernel/mte.c
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@@ -242,6 +242,49 @@
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 	mte_check_tfsr_el1();
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 }
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+void mte_cpu_setup(void)
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+{
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+	u64 rgsr;
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+
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+	/*
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+	 * CnP must be enabled only after the MAIR_EL1 register has been set
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+	 * up. Inconsistent MAIR_EL1 between CPUs sharing the same TLB may
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+	 * lead to the wrong memory type being used for a brief window during
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+	 * CPU power-up.
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+	 *
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+	 * CnP is not a boot feature so MTE gets enabled before CnP, but let's
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+	 * make sure that is the case.
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+	 */
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+	BUG_ON(read_sysreg(ttbr0_el1) & TTBR_CNP_BIT);
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+	BUG_ON(read_sysreg(ttbr1_el1) & TTBR_CNP_BIT);
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+
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+	/* Normal Tagged memory type at the corresponding MAIR index */
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+	sysreg_clear_set(mair_el1,
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+			 MAIR_ATTRIDX(MAIR_ATTR_MASK, MT_NORMAL_TAGGED),
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+			 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_TAGGED,
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+				      MT_NORMAL_TAGGED));
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+
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+	write_sysreg_s(KERNEL_GCR_EL1, SYS_GCR_EL1);
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+
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+	/*
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+	 * If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then
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+	 * RGSR_EL1.SEED must be non-zero for IRG to produce
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+	 * pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we
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+	 * must initialize it.
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+	 */
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+	rgsr = (read_sysreg(CNTVCT_EL0) & SYS_RGSR_EL1_SEED_MASK) <<
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+	       SYS_RGSR_EL1_SEED_SHIFT;
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+	if (rgsr == 0)
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+		rgsr = 1 << SYS_RGSR_EL1_SEED_SHIFT;
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+	write_sysreg_s(rgsr, SYS_RGSR_EL1);
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+
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+	/* clear any pending tag check faults in TFSR*_EL1 */
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+	write_sysreg_s(0, SYS_TFSR_EL1);
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+	write_sysreg_s(0, SYS_TFSRE0_EL1);
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+
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+	local_flush_tlb_all();
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+}
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+
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 void mte_suspend_enter(void)
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 {
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 	if (!system_supports_mte())
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@@ -258,6 +301,14 @@
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 	mte_check_tfsr_el1();
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 }
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+void mte_suspend_exit(void)
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+{
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+	if (!system_supports_mte())
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+		return;
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+
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+	mte_cpu_setup();
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+}
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+
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 long set_mte_ctrl(struct task_struct *task, unsigned long arg)
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 {
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 	u64 mte_ctrl = (~((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT) &