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79 | 79 | #define ARM_CPU_PART_CORTEX_A78AE 0xD42 |
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80 | 80 | #define ARM_CPU_PART_CORTEX_X1 0xD44 |
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81 | 81 | #define ARM_CPU_PART_CORTEX_A510 0xD46 |
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| 82 | +#define ARM_CPU_PART_CORTEX_A520 0xD80 |
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82 | 83 | #define ARM_CPU_PART_CORTEX_A710 0xD47 |
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83 | 84 | #define ARM_CPU_PART_CORTEX_X2 0xD48 |
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84 | 85 | #define ARM_CPU_PART_NEOVERSE_N2 0xD49 |
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130 | 131 | #define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE) |
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131 | 132 | #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) |
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132 | 133 | #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) |
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| 134 | +#define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520) |
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133 | 135 | #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) |
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134 | 136 | #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) |
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135 | 137 | #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) |
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