update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/arm64/include/asm/atomic_ll_sc.h
..
..
@@ -12,19 +12,6 @@
12
12
 
13
13
 #include <linux/stringify.h>
14
14
 
15
-#ifdef CONFIG_ARM64_LSE_ATOMICS
16
-#define __LL_SC_FALLBACK(asm_ops)					\
17
-"	b	3f\n"							\
18
-"	.subsection	1\n"						\
19
-"3:\n"									\
20
-asm_ops "\n"								\
21
-"	b	4f\n"							\
22
-"	.previous\n"							\
23
-"4:\n"
24
-#else
25
-#define __LL_SC_FALLBACK(asm_ops) asm_ops
26
-#endif
27
-
28
15
 #ifndef CONFIG_CC_HAS_K_CONSTRAINT
29
16
 #define K
30
17
 #endif
..
..
@@ -43,12 +30,11 @@
43
30
 	int result;							\
44
31
 									\
45
32
 	asm volatile("// atomic_" #op "\n"				\
46
-	__LL_SC_FALLBACK(						\
47
-"	prfm	pstl1strm, %2\n"					\
48
-"1:	ldxr	%w0, %2\n"						\
49
-"	" #asm_op "	%w0, %w0, %w3\n"				\
50
-"	stxr	%w1, %w0, %2\n"						\
51
-"	cbnz	%w1, 1b\n")						\
33
+	"	prfm	pstl1strm, %2\n"				\
34
+	"1:	ldxr	%w0, %2\n"					\
35
+	"	" #asm_op "	%w0, %w0, %w3\n"			\
36
+	"	stxr	%w1, %w0, %2\n"					\
37
+	"	cbnz	%w1, 1b\n"					\
52
38
 	: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)		\
53
39
 	: __stringify(constraint) "r" (i));				\
54
40
 }
..
..
@@ -61,13 +47,12 @@
61
47
 	int result;							\
62
48
 									\
63
49
 	asm volatile("// atomic_" #op "_return" #name "\n"		\
64
-	__LL_SC_FALLBACK(						\
65
-"	prfm	pstl1strm, %2\n"					\
66
-"1:	ld" #acq "xr	%w0, %2\n"					\
67
-"	" #asm_op "	%w0, %w0, %w3\n"				\
68
-"	st" #rel "xr	%w1, %w0, %2\n"					\
69
-"	cbnz	%w1, 1b\n"						\
70
-"	" #mb )								\
50
+	"	prfm	pstl1strm, %2\n"				\
51
+	"1:	ld" #acq "xr	%w0, %2\n"				\
52
+	"	" #asm_op "	%w0, %w0, %w3\n"			\
53
+	"	st" #rel "xr	%w1, %w0, %2\n"				\
54
+	"	cbnz	%w1, 1b\n"					\
55
+	"	" #mb							\
71
56
 	: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)		\
72
57
 	: __stringify(constraint) "r" (i)				\
73
58
 	: cl);								\
..
..
@@ -83,13 +68,12 @@
83
68
 	int val, result;						\
84
69
 									\
85
70
 	asm volatile("// atomic_fetch_" #op #name "\n"			\
86
-	__LL_SC_FALLBACK(						\
87
-"	prfm	pstl1strm, %3\n"					\
88
-"1:	ld" #acq "xr	%w0, %3\n"					\
89
-"	" #asm_op "	%w1, %w0, %w4\n"				\
90
-"	st" #rel "xr	%w2, %w1, %3\n"					\
91
-"	cbnz	%w2, 1b\n"						\
92
-"	" #mb )								\
71
+	"	prfm	pstl1strm, %3\n"				\
72
+	"1:	ld" #acq "xr	%w0, %3\n"				\
73
+	"	" #asm_op "	%w1, %w0, %w4\n"			\
74
+	"	st" #rel "xr	%w2, %w1, %3\n"				\
75
+	"	cbnz	%w2, 1b\n"					\
76
+	"	" #mb							\
93
77
 	: "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter)	\
94
78
 	: __stringify(constraint) "r" (i)				\
95
79
 	: cl);								\
..
..
@@ -142,12 +126,11 @@
142
126
 	unsigned long tmp;						\
143
127
 									\
144
128
 	asm volatile("// atomic64_" #op "\n"				\
145
-	__LL_SC_FALLBACK(						\
146
-"	prfm	pstl1strm, %2\n"					\
147
-"1:	ldxr	%0, %2\n"						\
148
-"	" #asm_op "	%0, %0, %3\n"					\
149
-"	stxr	%w1, %0, %2\n"						\
150
-"	cbnz	%w1, 1b")						\
129
+	"	prfm	pstl1strm, %2\n"				\
130
+	"1:	ldxr	%0, %2\n"					\
131
+	"	" #asm_op "	%0, %0, %3\n"				\
132
+	"	stxr	%w1, %0, %2\n"					\
133
+	"	cbnz	%w1, 1b"					\
151
134
 	: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)		\
152
135
 	: __stringify(constraint) "r" (i));				\
153
136
 }
..
..
@@ -160,13 +143,12 @@
160
143
 	unsigned long tmp;						\
161
144
 									\
162
145
 	asm volatile("// atomic64_" #op "_return" #name "\n"		\
163
-	__LL_SC_FALLBACK(						\
164
-"	prfm	pstl1strm, %2\n"					\
165
-"1:	ld" #acq "xr	%0, %2\n"					\
166
-"	" #asm_op "	%0, %0, %3\n"					\
167
-"	st" #rel "xr	%w1, %0, %2\n"					\
168
-"	cbnz	%w1, 1b\n"						\
169
-"	" #mb )								\
146
+	"	prfm	pstl1strm, %2\n"				\
147
+	"1:	ld" #acq "xr	%0, %2\n"				\
148
+	"	" #asm_op "	%0, %0, %3\n"				\
149
+	"	st" #rel "xr	%w1, %0, %2\n"				\
150
+	"	cbnz	%w1, 1b\n"					\
151
+	"	" #mb							\
170
152
 	: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)		\
171
153
 	: __stringify(constraint) "r" (i)				\
172
154
 	: cl);								\
..
..
@@ -176,19 +158,18 @@
176
158
 
177
159
 #define ATOMIC64_FETCH_OP(name, mb, acq, rel, cl, op, asm_op, constraint)\
178
160
 static inline long							\
179
-__ll_sc_atomic64_fetch_##op##name(s64 i, atomic64_t *v)		\
161
+__ll_sc_atomic64_fetch_##op##name(s64 i, atomic64_t *v)			\
180
162
 {									\
181
163
 	s64 result, val;						\
182
164
 	unsigned long tmp;						\
183
165
 									\
184
166
 	asm volatile("// atomic64_fetch_" #op #name "\n"		\
185
-	__LL_SC_FALLBACK(						\
186
-"	prfm	pstl1strm, %3\n"					\
187
-"1:	ld" #acq "xr	%0, %3\n"					\
188
-"	" #asm_op "	%1, %0, %4\n"					\
189
-"	st" #rel "xr	%w2, %1, %3\n"					\
190
-"	cbnz	%w2, 1b\n"						\
191
-"	" #mb )								\
167
+	"	prfm	pstl1strm, %3\n"				\
168
+	"1:	ld" #acq "xr	%0, %3\n"				\
169
+	"	" #asm_op "	%1, %0, %4\n"				\
170
+	"	st" #rel "xr	%w2, %1, %3\n"				\
171
+	"	cbnz	%w2, 1b\n"					\
172
+	"	" #mb							\
192
173
 	: "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (v->counter)	\
193
174
 	: __stringify(constraint) "r" (i)				\
194
175
 	: cl);								\
..
..
@@ -240,15 +221,14 @@
240
221
 	unsigned long tmp;
241
222
 
242
223
 	asm volatile("// atomic64_dec_if_positive\n"
243
-	__LL_SC_FALLBACK(
244
-"	prfm	pstl1strm, %2\n"
245
-"1:	ldxr	%0, %2\n"
246
-"	subs	%0, %0, #1\n"
247
-"	b.lt	2f\n"
248
-"	stlxr	%w1, %0, %2\n"
249
-"	cbnz	%w1, 1b\n"
250
-"	dmb	ish\n"
251
-"2:")
224
+	"	prfm	pstl1strm, %2\n"
225
+	"1:	ldxr	%0, %2\n"
226
+	"	subs	%0, %0, #1\n"
227
+	"	b.lt	2f\n"
228
+	"	stlxr	%w1, %0, %2\n"
229
+	"	cbnz	%w1, 1b\n"
230
+	"	dmb	ish\n"
231
+	"2:"
252
232
 	: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
253
233
 	:
254
234
 	: "cc", "memory");
..
..
@@ -274,7 +254,6 @@
274
254
 		old = (u##sz)old;					\
275
255
 									\
276
256
 	asm volatile(							\
277
-	__LL_SC_FALLBACK(						\
278
257
 	"	prfm	pstl1strm, %[v]\n"				\
279
258
 	"1:	ld" #acq "xr" #sfx "\t%" #w "[oldval], %[v]\n"		\
280
259
 	"	eor	%" #w "[tmp], %" #w "[oldval], %" #w "[old]\n"	\
..
..
@@ -282,7 +261,7 @@
282
261
 	"	st" #rel "xr" #sfx "\t%w[tmp], %" #w "[new], %[v]\n"	\
283
262
 	"	cbnz	%w[tmp], 1b\n"					\
284
263
 	"	" #mb "\n"						\
285
-	"2:")								\
264
+	"2:"								\
286
265
 	: [tmp] "=&r" (tmp), [oldval] "=&r" (oldval),			\
287
266
 	  [v] "+Q" (*(u##sz *)ptr)					\
288
267
 	: [old] __stringify(constraint) "r" (old), [new] "r" (new)	\
..
..
@@ -326,7 +305,6 @@
326
305
 	unsigned long tmp, ret;						\
327
306
 									\
328
307
 	asm volatile("// __cmpxchg_double" #name "\n"			\
329
-	__LL_SC_FALLBACK(						\
330
308
 	"	prfm	pstl1strm, %2\n"				\
331
309
 	"1:	ldxp	%0, %1, %2\n"					\
332
310
 	"	eor	%0, %0, %3\n"					\
..
..
@@ -336,8 +314,8 @@
336
314
 	"	st" #rel "xp	%w0, %5, %6, %2\n"			\
337
315
 	"	cbnz	%w0, 1b\n"					\
338
316
 	"	" #mb "\n"						\
339
-	"2:")								\
340
-	: "=&r" (tmp), "=&r" (ret), "+Q" (*(unsigned long *)ptr)	\
317
+	"2:"								\
318
+	: "=&r" (tmp), "=&r" (ret), "+Q" (*(__uint128_t *)ptr)		\
341
319
 	: "r" (old1), "r" (old2), "r" (new1), "r" (new2)		\
342
320
 	: cl);								\
343
321
 									\