forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf
kernel/arch/arm64/boot/dts/rockchip/rk3568-amp.dtsi
....@@ -1,6 +1,6 @@
11 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
22 /*
3
- * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
3
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
44 */
55
66 / {
....@@ -9,11 +9,6 @@
99 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>,
1010 <&cru PCLK_TIMER>, <&cru CLK_TIMER4>, <&cru CLK_TIMER5>,
1111 <&cru ACLK_MCU>;
12
- clock-names = "baudclk", "apb_pclk", "pclk", "timer";
13
- assigned-clocks = <&cru SCLK_UART4>,
14
- <&cru CLK_TIMER4>,
15
- <&cru CLK_TIMER5>;
16
- assigned-clock-rates = <24000000>;
1712
1813 pinctrl-names = "default";
1914 pinctrl-0 = <&uart4m1_xfer>;
....@@ -22,22 +17,11 @@
2217 amp_cpus: amp-cpus {
2318 amp-cpu3 {
2419 id = <0x0 0x300>;
25
- entry = <0x0 0x1800000>;
20
+ entry = <0x0 0x2800000>;
21
+ boot-on = <0>;
2622 mode = <0>;
2723 };
2824 };
29
- };
30
-
31
- rpmsg: rpmsg@7c00000 {
32
- compatible = "rockchip,rk3568-rpmsg";
33
- mbox-names = "rpmsg-rx", "rpmsg-tx";
34
- mboxes = <&mailbox 0 &mailbox 3>;
35
- rockchip,vdev-nums = <1>;
36
- rockchip,link-id = <0x03>;
37
- reg = <0x0 0x7c00000 0x0 0x20000>;
38
- memory-region = <&rpmsg_dma_reserved>;
39
-
40
- status = "okay";
4125 };
4226
4327 reserved-memory {
....@@ -68,8 +52,22 @@
6852 no-map;
6953 };
7054 };
55
+
56
+ rpmsg: rpmsg@7c00000 {
57
+ compatible = "rockchip,rpmsg";
58
+ mbox-names = "rpmsg-rx", "rpmsg-tx";
59
+ mboxes = <&mailbox 0 &mailbox 3>;
60
+ rockchip,vdev-nums = <1>;
61
+ rockchip,link-id = <0x03>;
62
+ reg = <0x0 0x7c00000 0x0 0x20000>;
63
+ memory-region = <&rpmsg_dma_reserved>;
64
+
65
+ status = "okay";
66
+ };
7167 };
7268
7369 &mailbox {
70
+ rockchip,txpoll-period-ms = <1>;
7471 status = "okay";
7572 };
73
+