~hc/RK356X_SDK_RELEASE.git

..	..	@@ -24,7 +24,14 @@
24	24	#size-cells = <2>;
25	25
26	26	aliases {
	27	+ dsi0 = &dsi;
	28	+ dsi1 = &dsi1;
27	29	ethernet0 = &gmac;
	30	+ gpio0 = &gpio0;
	31	+ gpio1 = &gpio1;
	32	+ gpio2 = &gpio2;
	33	+ gpio3 = &gpio3;
	34	+ gpio4 = &gpio4;
28	35	i2c0 = &i2c0;
29	36	i2c1 = &i2c1;
30	37	i2c2 = &i2c2;
..	..	@@ -42,8 +49,6 @@
42	49	serial2 = &uart2;
43	50	serial3 = &uart3;
44	51	serial4 = &uart4;
45		- dsi0 = &dsi;
46		- dsi1 = &dsi1;
47	52	};
48	53
49	54	cpus {
..	..	@@ -78,7 +83,7 @@
78	83
79	84	cpu_l0: cpu@0 {
80	85	device_type = "cpu";
81		- compatible = "arm,cortex-a53", "arm,armv8";
	86	+ compatible = "arm,cortex-a53";
82	87	reg = <0x0 0x0>;
83	88	enable-method = "psci";
84	89	capacity-dmips-mhz = <485>;
..	..	@@ -90,7 +95,7 @@
90	95
91	96	cpu_l1: cpu@1 {
92	97	device_type = "cpu";
93		- compatible = "arm,cortex-a53", "arm,armv8";
	98	+ compatible = "arm,cortex-a53";
94	99	reg = <0x0 0x1>;
95	100	enable-method = "psci";
96	101	capacity-dmips-mhz = <485>;
..	..	@@ -102,7 +107,7 @@
102	107
103	108	cpu_l2: cpu@2 {
104	109	device_type = "cpu";
105		- compatible = "arm,cortex-a53", "arm,armv8";
	110	+ compatible = "arm,cortex-a53";
106	111	reg = <0x0 0x2>;
107	112	enable-method = "psci";
108	113	capacity-dmips-mhz = <485>;
..	..	@@ -114,7 +119,7 @@
114	119
115	120	cpu_l3: cpu@3 {
116	121	device_type = "cpu";
117		- compatible = "arm,cortex-a53", "arm,armv8";
	122	+ compatible = "arm,cortex-a53";
118	123	reg = <0x0 0x3>;
119	124	enable-method = "psci";
120	125	capacity-dmips-mhz = <485>;
..	..	@@ -126,7 +131,7 @@
126	131
127	132	cpu_b0: cpu@100 {
128	133	device_type = "cpu";
129		- compatible = "arm,cortex-a72", "arm,armv8";
	134	+ compatible = "arm,cortex-a72";
130	135	reg = <0x0 0x100>;
131	136	enable-method = "psci";
132	137	capacity-dmips-mhz = <1024>;
..	..	@@ -138,7 +143,7 @@
138	143
139	144	cpu_b1: cpu@101 {
140	145	device_type = "cpu";
141		- compatible = "arm,cortex-a72", "arm,armv8";
	146	+ compatible = "arm,cortex-a72";
142	147	reg = <0x0 0x101>;
143	148	enable-method = "psci";
144	149	capacity-dmips-mhz = <1024>;
..	..	@@ -176,14 +181,6 @@
176	181	ports = <&vopl_out>, <&vopb_out>;
177	182	clocks = <&cru PLL_VPLL>, <&cru PLL_CPLL>;
178	183	clock-names = "hdmi-tmds-pll", "default-vop-pll";
179		- devfreq = <&dmc>;
180		- };
181		-
182		- firmware {
183		- optee: optee {
184		- compatible = "linaro,optee-tz";
185		- method = "smc";
186		- };
187	184	};
188	185
189	186	pmu_a53 {
..	..	@@ -231,7 +228,7 @@
231	228	#clock-cells = <0>;
232	229	};
233	230
234		- amba {
	231	+ amba: bus {
235	232	compatible = "simple-bus";
236	233	#address-cells = <2>;
237	234	#size-cells = <2>;
..	..	@@ -243,9 +240,9 @@
243	240	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
244	241	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
245	242	#dma-cells = <1>;
	243	+ arm,pl330-periph-burst;
246	244	clocks = <&cru ACLK_DMAC0_PERILP>;
247	245	clock-names = "apb_pclk";
248		- arm,pl330-periph-burst;
249	246	};
250	247
251	248	dmac_peri: dma-controller@ff6e0000 {
..	..	@@ -254,9 +251,9 @@
254	251	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
255	252	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
256	253	#dma-cells = <1>;
	254	+ arm,pl330-periph-burst;
257	255	clocks = <&cru ACLK_DMAC1_PERILP>;
258	256	clock-names = "apb_pclk";
259		- arm,pl330-periph-burst;
260	257	};
261	258	};
262	259
..	..	@@ -325,10 +322,11 @@
325	322	resets = <&cru SRST_A_GMAC>;
326	323	reset-names = "stmmaceth";
327	324	rockchip,grf = <&grf>;
	325	+ snps,txpbl = <0x4>;
328	326	status = "disabled";
329	327	};
330	328
331		- sdio0: dwmmc@fe310000 {
	329	+ sdio0: mmc@fe310000 {
332	330	compatible = "rockchip,rk3399-dw-mshc",
333	331	"rockchip,rk3288-dw-mshc";
334	332	reg = <0x0 0xfe310000 0x0 0x4000>;
..	..	@@ -344,7 +342,7 @@
344	342	status = "disabled";
345	343	};
346	344
347		- sdmmc: dwmmc@fe320000 {
	345	+ sdmmc: mmc@fe320000 {
348	346	compatible = "rockchip,rk3399-dw-mshc",
349	347	"rockchip,rk3288-dw-mshc";
350	348	reg = <0x0 0xfe320000 0x0 0x4000>;
..	..	@@ -381,28 +379,14 @@
381	379	status = "disabled";
382	380	};
383	381
384		- usic: usb@fe340000 {
385		- compatible = "generic-ehci";
386		- reg = <0x0 0xfe340000 0x0 0x30000>;
387		- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH 0>;
388		- clocks = <&cru HCLK_HSIC>, <&cru SCLK_HSICPHY>,
389		- <&cru PCLK_HSICPHY>;
390		- clock-names = "hclk_hsic", "clk_hsicphy", "pclk_hsicphy";
391		- rockchip-has-usic;
392		- status = "disabled";
393		- };
394		-
395	382	usb_host0_ehci: usb@fe380000 {
396	383	compatible = "generic-ehci";
397	384	reg = <0x0 0xfe380000 0x0 0x20000>;
398	385	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
399	386	clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
400	387	<&u2phy0>;
401		- clock-names = "usbhost", "arbiter",
402		- "utmi";
403	388	phys = <&u2phy0_host>;
404	389	phy-names = "usb";
405		- power-domains = <&power RK3399_PD_PERIHP>;
406	390	status = "disabled";
407	391	};
408	392
..	..	@@ -412,11 +396,8 @@
412	396	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
413	397	clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
414	398	<&u2phy0>;
415		- clock-names = "usbhost", "arbiter",
416		- "utmi";
417	399	phys = <&u2phy0_host>;
418	400	phy-names = "usb";
419		- power-domains = <&power RK3399_PD_PERIHP>;
420	401	status = "disabled";
421	402	};
422	403
..	..	@@ -426,11 +407,8 @@
426	407	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
427	408	clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
428	409	<&u2phy1>;
429		- clock-names = "usbhost", "arbiter",
430		- "utmi";
431	410	phys = <&u2phy1_host>;
432	411	phy-names = "usb";
433		- power-domains = <&power RK3399_PD_PERIHP>;
434	412	status = "disabled";
435	413	};
436	414
..	..	@@ -440,11 +418,8 @@
440	418	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
441	419	clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
442	420	<&u2phy1>;
443		- clock-names = "usbhost", "arbiter",
444		- "utmi";
445	421	phys = <&u2phy1_host>;
446	422	phy-names = "usb";
447		- power-domains = <&power RK3399_PD_PERIHP>;
448	423	status = "disabled";
449	424	};
450	425
..	..	@@ -454,31 +429,36 @@
454	429	#size-cells = <2>;
455	430	ranges;
456	431	clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
457		- <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
	432	+ <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
	433	+ <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
458	434	clock-names = "ref_clk", "suspend_clk",
459		- "bus_clk", "grf_clk";
	435	+ "bus_clk", "aclk_usb3_rksoc_axi_perf",
	436	+ "aclk_usb3", "grf_clk";
460	437	status = "disabled";
461	438
462		- usbdrd_dwc3_0: dwc3@fe800000 {
	439	+ usbdrd_dwc3_0: usb@fe800000 {
463	440	compatible = "snps,dwc3";
464	441	reg = <0x0 0xfe800000 0x0 0x100000>;
465	442	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
	443	+ clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
	444	+ <&cru SCLK_USB3OTG0_SUSPEND>;
	445	+ clock-names = "ref", "bus_early", "suspend";
	446	+ resets = <&cru SRST_A_USB3_OTG0>;
	447	+ reset-names = "usb3-otg";
466	448	dr_mode = "otg";
467	449	phys = <&u2phy0_otg>, <&tcphy0_usb3>;
468	450	phy-names = "usb2-phy", "usb3-phy";
469	451	phy_type = "utmi_wide";
470		- power-domains = <&power RK3399_PD_USB3>;
471		- resets = <&cru SRST_A_USB3_OTG0>;
472		- reset-names = "usb3-otg";
473	452	snps,dis_enblslpm_quirk;
474		- snps,dis-u1u2-quirk;
	453	+ snps,dis-u1-entry-quirk;
	454	+ snps,dis-u2-entry-quirk;
475	455	snps,dis-u2-freeclk-exists-quirk;
476	456	snps,dis_u2_susphy_quirk;
477	457	snps,dis-del-phy-power-chg-quirk;
478	458	snps,dis-tx-ipgap-linecheck-quirk;
479		- snps,xhci-slow-suspend-quirk;
480		- snps,xhci-trb-ent-quirk;
481		- snps,xhci-warm-reset-on-suspend-quirk;
	459	+ snps,parkmode-disable-hs-quirk;
	460	+ snps,parkmode-disable-ss-quirk;
	461	+ power-domains = <&power RK3399_PD_USB3>;
482	462	status = "disabled";
483	463	};
484	464	};
..	..	@@ -489,30 +469,34 @@
489	469	#size-cells = <2>;
490	470	ranges;
491	471	clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
492		- <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
	472	+ <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
	473	+ <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
493	474	clock-names = "ref_clk", "suspend_clk",
494		- "bus_clk", "grf_clk";
	475	+ "bus_clk", "aclk_usb3_rksoc_axi_perf",
	476	+ "aclk_usb3", "grf_clk";
495	477	status = "disabled";
496	478
497		- usbdrd_dwc3_1: dwc3@fe900000 {
	479	+ usbdrd_dwc3_1: usb@fe900000 {
498	480	compatible = "snps,dwc3";
499	481	reg = <0x0 0xfe900000 0x0 0x100000>;
500	482	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
501		- dr_mode = "host";
	483	+ clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
	484	+ <&cru SCLK_USB3OTG1_SUSPEND>;
	485	+ clock-names = "ref", "bus_early", "suspend";
	486	+ resets = <&cru SRST_A_USB3_OTG1>;
	487	+ reset-names = "usb3-otg";
	488	+ dr_mode = "otg";
502	489	phys = <&u2phy1_otg>, <&tcphy1_usb3>;
503	490	phy-names = "usb2-phy", "usb3-phy";
504	491	phy_type = "utmi_wide";
505		- power-domains = <&power RK3399_PD_USB3>;
506		- resets = <&cru SRST_A_USB3_OTG1>;
507		- reset-names = "usb3-otg";
508	492	snps,dis_enblslpm_quirk;
509	493	snps,dis-u2-freeclk-exists-quirk;
510	494	snps,dis_u2_susphy_quirk;
511	495	snps,dis-del-phy-power-chg-quirk;
512	496	snps,dis-tx-ipgap-linecheck-quirk;
513		- snps,xhci-slow-suspend-quirk;
514		- snps,xhci-trb-ent-quirk;
515		- snps,xhci-warm-reset-on-suspend-quirk;
	497	+ snps,parkmode-disable-hs-quirk;
	498	+ snps,parkmode-disable-ss-quirk;
	499	+ power-domains = <&power RK3399_PD_USB3>;
516	500	status = "disabled";
517	501	};
518	502	};
..	..	@@ -570,6 +554,7 @@
570	554	its: interrupt-controller@fee20000 {
571	555	compatible = "arm,gic-v3-its";
572	556	msi-controller;
	557	+ #msi-cells = <1>;
573	558	reg = <0x0 0xfee20000 0x0 0x20000>;
574	559	};
575	560
..	..	@@ -744,6 +729,8 @@
744	729	clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
745	730	clock-names = "spiclk", "apb_pclk";
746	731	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
	732	+ dmas = <&dmac_peri 10>, <&dmac_peri 11>;
	733	+ dma-names = "tx", "rx";
747	734	pinctrl-names = "default";
748	735	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
749	736	#address-cells = <1>;
..	..	@@ -757,6 +744,8 @@
757	744	clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
758	745	clock-names = "spiclk", "apb_pclk";
759	746	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
	747	+ dmas = <&dmac_peri 12>, <&dmac_peri 13>;
	748	+ dma-names = "tx", "rx";
760	749	pinctrl-names = "default";
761	750	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
762	751	#address-cells = <1>;
..	..	@@ -770,6 +759,8 @@
770	759	clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
771	760	clock-names = "spiclk", "apb_pclk";
772	761	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
	762	+ dmas = <&dmac_peri 14>, <&dmac_peri 15>;
	763	+ dma-names = "tx", "rx";
773	764	pinctrl-names = "default";
774	765	pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
775	766	#address-cells = <1>;
..	..	@@ -783,6 +774,8 @@
783	774	clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
784	775	clock-names = "spiclk", "apb_pclk";
785	776	interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
	777	+ dmas = <&dmac_peri 18>, <&dmac_peri 19>;
	778	+ dma-names = "tx", "rx";
786	779	pinctrl-names = "default";
787	780	pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
788	781	#address-cells = <1>;
..	..	@@ -796,6 +789,8 @@
796	789	clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
797	790	clock-names = "spiclk", "apb_pclk";
798	791	interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
	792	+ dmas = <&dmac_bus 8>, <&dmac_bus 9>;
	793	+ dma-names = "tx", "rx";
799	794	pinctrl-names = "default";
800	795	pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
801	796	power-domains = <&power RK3399_PD_SDIOAUDIO>;
..	..	@@ -805,7 +800,7 @@
805	800	};
806	801
807	802	thermal_zones: thermal-zones {
808		- soc_thermal: soc-thermal {
	803	+ soc_thermal: cpu_thermal: cpu-thermal {
809	804	polling-delay-passive = <20>;
810	805	polling-delay = <1000>;
811	806	sustainable-power = <1000>; /* milliwatts */
..	..	@@ -813,17 +808,17 @@
813	808	thermal-sensors = <&tsadc 0>;
814	809
815	810	trips {
816		- threshold: trip-point-0 {
	811	+ threshold: cpu_alert0: cpu_alert0 {
817	812	temperature = <70000>;
818	813	hysteresis = <2000>;
819	814	type = "passive";
820	815	};
821		- target: trip-point-1 {
	816	+ target: cpu_alert1: cpu_alert1 {
822	817	temperature = <85000>;
823	818	hysteresis = <2000>;
824	819	type = "passive";
825	820	};
826		- soc_crit: soc-crit {
	821	+ soc_crit: cpu_crit: cpu_crit {
827	822	temperature = <115000>; /* millicelsius */
828	823	hysteresis = <2000>; /* millicelsius */
829	824	type = "critical";
..	..	@@ -871,9 +866,9 @@
871	866	resets = <&cru SRST_TSADC>;
872	867	reset-names = "tsadc-apb";
873	868	rockchip,grf = <&grf>;
874		- rockchip,hw-tshut-temp = <120000>;
	869	+ rockchip,hw-tshut-temp = <95000>;
875	870	pinctrl-names = "gpio", "otpout";
876		- pinctrl-0 = <&otp_gpio>;
	871	+ pinctrl-0 = <&otp_pin>;
877	872	pinctrl-1 = <&otp_out>;
878	873	#thermal-sensor-cells = <1>;
879	874	status = "disabled";
..	..	@@ -1022,26 +1017,26 @@
1022	1017	#size-cells = <0>;
1023	1018
1024	1019	/* These power domains are grouped by VD_CENTER */
1025		- pd_iep@RK3399_PD_IEP {
	1020	+ power-domain@RK3399_PD_IEP {
1026	1021	reg = <RK3399_PD_IEP>;
1027	1022	clocks = <&cru ACLK_IEP>,
1028	1023	<&cru HCLK_IEP>;
1029	1024	pm_qos = <&qos_iep>;
1030	1025	};
1031		- pd_rga@RK3399_PD_RGA {
	1026	+ power-domain@RK3399_PD_RGA {
1032	1027	reg = <RK3399_PD_RGA>;
1033	1028	clocks = <&cru ACLK_RGA>,
1034	1029	<&cru HCLK_RGA>;
1035	1030	pm_qos = <&qos_rga_r>,
1036	1031	<&qos_rga_w>;
1037	1032	};
1038		- pd_vcodec@RK3399_PD_VCODEC {
	1033	+ power-domain@RK3399_PD_VCODEC {
1039	1034	reg = <RK3399_PD_VCODEC>;
1040	1035	clocks = <&cru ACLK_VCODEC>,
1041	1036	<&cru HCLK_VCODEC>;
1042	1037	pm_qos = <&qos_video_m0>;
1043	1038	};
1044		- pd_vdu@RK3399_PD_VDU {
	1039	+ power-domain@RK3399_PD_VDU {
1045	1040	reg = <RK3399_PD_VDU>;
1046	1041	clocks = <&cru ACLK_VDU>,
1047	1042	<&cru HCLK_VDU>;
..	..	@@ -1050,29 +1045,29 @@
1050	1045	};
1051	1046
1052	1047	/* These power domains are grouped by VD_GPU */
1053		- pd_gpu@RK3399_PD_GPU {
	1048	+ power-domain@RK3399_PD_GPU {
1054	1049	reg = <RK3399_PD_GPU>;
1055	1050	clocks = <&cru ACLK_GPU>;
1056	1051	pm_qos = <&qos_gpu>;
1057	1052	};
1058	1053
1059	1054	/* These power domains are grouped by VD_LOGIC */
1060		- pd_edp@RK3399_PD_EDP {
	1055	+ power-domain@RK3399_PD_EDP {
1061	1056	reg = <RK3399_PD_EDP>;
1062	1057	clocks = <&cru PCLK_EDP_CTRL>;
1063	1058	};
1064		- pd_emmc@RK3399_PD_EMMC {
	1059	+ power-domain@RK3399_PD_EMMC {
1065	1060	reg = <RK3399_PD_EMMC>;
1066	1061	clocks = <&cru ACLK_EMMC>;
1067	1062	pm_qos = <&qos_emmc>;
1068	1063	};
1069		- pd_gmac@RK3399_PD_GMAC {
	1064	+ power-domain@RK3399_PD_GMAC {
1070	1065	reg = <RK3399_PD_GMAC>;
1071	1066	clocks = <&cru ACLK_GMAC>,
1072	1067	<&cru PCLK_GMAC>;
1073	1068	pm_qos = <&qos_gmac>;
1074	1069	};
1075		- pd_perihp@RK3399_PD_PERIHP {
	1070	+ power-domain@RK3399_PD_PERIHP {
1076	1071	reg = <RK3399_PD_PERIHP>;
1077	1072	#address-cells = <1>;
1078	1073	#size-cells = <0>;
..	..	@@ -1082,73 +1077,73 @@
1082	1077	<&qos_usb_host0>,
1083	1078	<&qos_usb_host1>;
1084	1079
1085		- pd_sd@RK3399_PD_SD {
	1080	+ power-domain@RK3399_PD_SD {
1086	1081	reg = <RK3399_PD_SD>;
1087	1082	clocks = <&cru HCLK_SDMMC>,
1088	1083	<&cru SCLK_SDMMC>;
1089	1084	pm_qos = <&qos_sd>;
1090	1085	};
1091	1086	};
1092		- pd_sdioaudio@RK3399_PD_SDIOAUDIO {
	1087	+ power-domain@RK3399_PD_SDIOAUDIO {
1093	1088	reg = <RK3399_PD_SDIOAUDIO>;
1094	1089	clocks = <&cru HCLK_SDIO>;
1095	1090	pm_qos = <&qos_sdioaudio>;
1096	1091	};
1097		- pd_usb3@RK3399_PD_USB3 {
	1092	+ power-domain@RK3399_PD_TCPD0 {
	1093	+ reg = <RK3399_PD_TCPD0>;
	1094	+ clocks = <&cru SCLK_UPHY0_TCPDCORE>,
	1095	+ <&cru SCLK_UPHY0_TCPDPHY_REF>;
	1096	+ };
	1097	+ power-domain@RK3399_PD_TCPD1 {
	1098	+ reg = <RK3399_PD_TCPD1>;
	1099	+ clocks = <&cru SCLK_UPHY1_TCPDCORE>,
	1100	+ <&cru SCLK_UPHY1_TCPDPHY_REF>;
	1101	+ };
	1102	+ power-domain@RK3399_PD_USB3 {
1098	1103	reg = <RK3399_PD_USB3>;
1099	1104	clocks = <&cru ACLK_USB3>;
1100	1105	pm_qos = <&qos_usb_otg0>,
1101	1106	<&qos_usb_otg1>;
1102	1107	};
1103		- pd_vio@RK3399_PD_VIO {
	1108	+ power-domain@RK3399_PD_VIO {
1104	1109	reg = <RK3399_PD_VIO>;
1105	1110	#address-cells = <1>;
1106	1111	#size-cells = <0>;
1107	1112
1108		- pd_hdcp@RK3399_PD_HDCP {
	1113	+ power-domain@RK3399_PD_HDCP {
1109	1114	reg = <RK3399_PD_HDCP>;
1110	1115	clocks = <&cru ACLK_HDCP>,
1111	1116	<&cru HCLK_HDCP>,
1112	1117	<&cru PCLK_HDCP>;
1113	1118	pm_qos = <&qos_hdcp>;
1114	1119	};
1115		- pd_isp0@RK3399_PD_ISP0 {
	1120	+ power-domain@RK3399_PD_ISP0 {
1116	1121	reg = <RK3399_PD_ISP0>;
1117	1122	clocks = <&cru ACLK_ISP0>,
1118	1123	<&cru HCLK_ISP0>;
1119	1124	pm_qos = <&qos_isp0_m0>,
1120	1125	<&qos_isp0_m1>;
1121	1126	};
1122		- pd_isp1@RK3399_PD_ISP1 {
	1127	+ power-domain@RK3399_PD_ISP1 {
1123	1128	reg = <RK3399_PD_ISP1>;
1124	1129	clocks = <&cru ACLK_ISP1>,
1125	1130	<&cru HCLK_ISP1>;
1126	1131	pm_qos = <&qos_isp1_m0>,
1127	1132	<&qos_isp1_m1>;
1128	1133	};
1129		- pd_tcpc0@RK3399_PD_TCPC0 {
1130		- reg = <RK3399_PD_TCPD0>;
1131		- clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1132		- <&cru SCLK_UPHY0_TCPDPHY_REF>;
1133		- };
1134		- pd_tcpc1@RK3399_PD_TCPC1 {
1135		- reg = <RK3399_PD_TCPD1>;
1136		- clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1137		- <&cru SCLK_UPHY1_TCPDPHY_REF>;
1138		- };
1139		- pd_vo@RK3399_PD_VO {
	1134	+ power-domain@RK3399_PD_VO {
1140	1135	reg = <RK3399_PD_VO>;
1141	1136	#address-cells = <1>;
1142	1137	#size-cells = <0>;
1143	1138
1144		- pd_vopb@RK3399_PD_VOPB {
	1139	+ power-domain@RK3399_PD_VOPB {
1145	1140	reg = <RK3399_PD_VOPB>;
1146	1141	clocks = <&cru ACLK_VOP0>,
1147	1142	<&cru HCLK_VOP0>;
1148	1143	pm_qos = <&qos_vop_big_r>,
1149	1144	<&qos_vop_big_w>;
1150	1145	};
1151		- pd_vopl@RK3399_PD_VOPL {
	1146	+ power-domain@RK3399_PD_VOPL {
1152	1147	reg = <RK3399_PD_VOPL>;
1153	1148	clocks = <&cru ACLK_VOP1>,
1154	1149	<&cru HCLK_VOP1>;
..	..	@@ -1162,8 +1157,6 @@
1162	1157	pmugrf: syscon@ff320000 {
1163	1158	compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1164	1159	reg = <0x0 0xff320000 0x0 0x1000>;
1165		- #address-cells = <1>;
1166		- #size-cells = <1>;
1167	1160
1168	1161	pmu_io_domains: io-domains {
1169	1162	compatible = "rockchip,rk3399-pmu-io-voltage-domain";
..	..	@@ -1339,20 +1332,16 @@
1339	1332	status = "disabled";
1340	1333	};
1341	1334
1342		- vdpu: vdpu@ff650400 {
1343		- compatible = "rockchip,vpu-decoder-v2";
1344		- reg = <0x0 0xff650400 0x0 0x400>;
1345		- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1346		- interrupt-names = "irq_dec";
	1335	+ vpu: video-codec@ff650000 {
	1336	+ compatible = "rockchip,rk3399-vpu";
	1337	+ reg = <0x0 0xff650000 0x0 0x800>;
	1338	+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
	1339	+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
	1340	+ interrupt-names = "vepu", "vdpu";
1347	1341	clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1348		- clock-names = "aclk_vcodec", "hclk_vcodec";
1349		- resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
1350		- reset-names = "shared_video_h", "shared_video_a";
	1342	+ clock-names = "aclk", "hclk";
1351	1343	iommus = <&vpu_mmu>;
1352	1344	power-domains = <&power RK3399_PD_VCODEC>;
1353		- rockchip,srv = <&mpp_srv>;
1354		- rockchip,taskqueue-node = <0>;
1355		- rockchip,resetgroup-node = <0>;
1356	1345	status = "disabled";
1357	1346	};
1358	1347
..	..	@@ -1373,6 +1362,23 @@
1373	1362	status = "disabled";
1374	1363	};
1375	1364
	1365	+ vdpu: vdpu@ff650400 {
	1366	+ compatible = "rockchip,vpu-decoder-v2";
	1367	+ reg = <0x0 0xff650400 0x0 0x400>;
	1368	+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
	1369	+ interrupt-names = "irq_dec";
	1370	+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
	1371	+ clock-names = "aclk_vcodec", "hclk_vcodec";
	1372	+ resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
	1373	+ reset-names = "shared_video_h", "shared_video_a";
	1374	+ iommus = <&vpu_mmu>;
	1375	+ power-domains = <&power RK3399_PD_VCODEC>;
	1376	+ rockchip,srv = <&mpp_srv>;
	1377	+ rockchip,taskqueue-node = <0>;
	1378	+ rockchip,resetgroup-node = <0>;
	1379	+ status = "disabled";
	1380	+ };
	1381	+
1376	1382	vpu_mmu: iommu@ff650800 {
1377	1383	compatible = "rockchip,iommu";
1378	1384	reg = <0x0 0xff650800 0x0 0x40>;
..	..	@@ -1380,8 +1386,20 @@
1380	1386	interrupt-names = "vpu_mmu";
1381	1387	clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1382	1388	clock-names = "aclk", "iface";
1383		- power-domains = <&power RK3399_PD_VCODEC>;
1384	1389	#iommu-cells = <0>;
	1390	+ power-domains = <&power RK3399_PD_VCODEC>;
	1391	+ status = "disabled";
	1392	+ };
	1393	+
	1394	+ vdec: video-codec@ff660000 {
	1395	+ compatible = "rockchip,rk3399-vdec";
	1396	+ reg = <0x0 0xff660000 0x0 0x400>;
	1397	+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
	1398	+ clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
	1399	+ <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
	1400	+ clock-names = "axi", "ahb", "cabac", "core";
	1401	+ iommus = <&vdec_mmu>;
	1402	+ power-domains = <&power RK3399_PD_VDU>;
1385	1403	status = "disabled";
1386	1404	};
1387	1405
..	..	@@ -1399,7 +1417,7 @@
1399	1417	<&cru SRST_VDU_CA>, <&cru SRST_VDU_CORE>;
1400	1418	reset-names = "video_h", "video_a", "niu_h", "niu_a",
1401	1419	"video_cabac", "video_core";
1402		- iommus = <&rkvdec_mmu>;
	1420	+ iommus = <&vdec_mmu>;
1403	1421	rockchip,srv = <&mpp_srv>;
1404	1422	rockchip,taskqueue-node = <1>;
1405	1423	rockchip,resetgroup-node = <1>;
..	..	@@ -1407,11 +1425,11 @@
1407	1425	status = "disabled";
1408	1426	};
1409	1427
1410		- rkvdec_mmu: iommu@ff660480 {
	1428	+ vdec_mmu: iommu@ff660480 {
1411	1429	compatible = "rockchip,iommu";
1412	1430	reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1413	1431	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1414		- interrupt-names = "rkvdec_mmu";
	1432	+ interrupt-names = "vdec_mmu";
1415	1433	clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1416	1434	clock-names = "aclk", "iface";
1417	1435	power-domains = <&power RK3399_PD_VDU>;
..	..	@@ -1499,23 +1517,22 @@
1499	1517	pmucru: pmu-clock-controller@ff750000 {
1500	1518	compatible = "rockchip,rk3399-pmucru";
1501	1519	reg = <0x0 0xff750000 0x0 0x1000>;
	1520	+ rockchip,grf = <&pmugrf>;
1502	1521	#clock-cells = <1>;
1503	1522	#reset-cells = <1>;
1504		- assigned-clocks = <&pmucru PLL_PPLL>, <&pmucru FCLK_CM0S_SRC_PMU>;
1505		- assigned-clock-rates = <676000000>, <97000000>;
	1523	+ assigned-clocks = <&pmucru PLL_PPLL>;
	1524	+ assigned-clock-rates = <676000000>;
1506	1525	};
1507	1526
1508	1527	cru: clock-controller@ff760000 {
1509	1528	compatible = "rockchip,rk3399-cru";
1510	1529	reg = <0x0 0xff760000 0x0 0x1000>;
	1530	+ rockchip,grf = <&grf>;
1511	1531	#clock-cells = <1>;
1512	1532	#reset-cells = <1>;
1513	1533	assigned-clocks =
1514		- <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1515		- <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1516		- <&cru ARMCLKL>, <&cru ARMCLKB>,
1517	1534	<&cru PLL_GPLL>, <&cru PLL_CPLL>,
1518		- <&cru ACLK_GPU>, <&cru PLL_NPLL>,
	1535	+ <&cru PLL_NPLL>,
1519	1536	<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1520	1537	<&cru PCLK_PERIHP>,
1521	1538	<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
..	..	@@ -1525,11 +1542,8 @@
1525	1542	<&cru ACLK_GIC_PRE>,
1526	1543	<&cru PCLK_DDR>;
1527	1544	assigned-clock-rates =
1528		- <400000000>, <200000000>,
1529		- <400000000>, <200000000>,
1530		- <816000000>, <816000000>,
1531	1545	<594000000>, <800000000>,
1532		- <200000000>, <1000000000>,
	1546	+ <1000000000>,
1533	1547	<150000000>, <75000000>,
1534	1548	<37500000>,
1535	1549	<100000000>, <100000000>,
..	..	@@ -1551,6 +1565,17 @@
1551	1565	status = "disabled";
1552	1566	};
1553	1567
	1568	+ mipi_dphy_rx0: mipi-dphy-rx0 {
	1569	+ compatible = "rockchip,rk3399-mipi-dphy";
	1570	+ clocks = <&cru SCLK_MIPIDPHY_REF>,
	1571	+ <&cru SCLK_DPHY_RX0_CFG>,
	1572	+ <&cru PCLK_VIO_GRF>;
	1573	+ clock-names = "dphy-ref", "dphy-cfg", "grf";
	1574	+ power-domains = <&power RK3399_PD_VIO>;
	1575	+ #phy-cells = <0>;
	1576	+ status = "disabled";
	1577	+ };
	1578	+
1554	1579	u2phy0: usb2-phy@e450 {
1555	1580	compatible = "rockchip,rk3399-usb2phy";
1556	1581	reg = <0xe450 0x10>;
..	..	@@ -1558,7 +1583,6 @@
1558	1583	clock-names = "phyclk";
1559	1584	#clock-cells = <0>;
1560	1585	clock-output-names = "clk_usbphy0_480m";
1561		- power-domains = <&power RK3399_PD_PERIHP>;
1562	1586	status = "disabled";
1563	1587
1564	1588	u2phy0_host: host-port {
..	..	@@ -1586,7 +1610,6 @@
1586	1610	clock-names = "phyclk";
1587	1611	#clock-cells = <0>;
1588	1612	clock-output-names = "clk_usbphy1_480m";
1589		- power-domains = <&power RK3399_PD_PERIHP>;
1590	1613	status = "disabled";
1591	1614
1592	1615	u2phy1_host: host-port {
..	..	@@ -1612,6 +1635,7 @@
1612	1635	reg = <0xf780 0x24>;
1613	1636	clocks = <&sdhci>;
1614	1637	clock-names = "emmcclk";
	1638	+ drive-impedance-ohm = <50>;
1615	1639	#phy-cells = <0>;
1616	1640	status = "disabled";
1617	1641	};
..	..	@@ -1623,16 +1647,6 @@
1623	1647	#phy-cells = <1>;
1624	1648	resets = <&cru SRST_PCIEPHY>;
1625	1649	reset-names = "phy";
1626		- status = "disabled";
1627		- };
1628		-
1629		- mipi_dphy_rx0: mipi-dphy-rx0 {
1630		- compatible = "rockchip,rk3399-mipi-dphy";
1631		- clocks = <&cru SCLK_MIPIDPHY_REF>,
1632		- <&cru SCLK_DPHY_RX0_CFG>,
1633		- <&cru PCLK_VIO_GRF>;
1634		- clock-names = "dphy-ref", "dphy-cfg", "grf";
1635		- power-domains = <&power RK3399_PD_VIO>;
1636	1650	status = "disabled";
1637	1651	};
1638	1652
..	..	@@ -1687,13 +1701,6 @@
1687	1701	<&cru SRST_P_UPHY0_TCPHY>;
1688	1702	reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1689	1703	rockchip,grf = <&grf>;
1690		- rockchip,typec-conn-dir = <0xe580 0 16>;
1691		- rockchip,usb3tousb2-en = <0xe580 3 19>;
1692		- rockchip,usb3-host-disable = <0x2434 0 16>;
1693		- rockchip,usb3-host-port = <0x2434 12 28>;
1694		- rockchip,external-psm = <0xe588 14 30>;
1695		- rockchip,pipe-status = <0xe5c0 0 0>;
1696		- rockchip,uphy-dp-sel = <0x6268 19 19>;
1697	1704	status = "disabled";
1698	1705
1699	1706	tcphy0_dp: dp-port {
..	..	@@ -1719,13 +1726,6 @@
1719	1726	<&cru SRST_P_UPHY1_TCPHY>;
1720	1727	reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1721	1728	rockchip,grf = <&grf>;
1722		- rockchip,typec-conn-dir = <0xe58c 0 16>;
1723		- rockchip,usb3tousb2-en = <0xe58c 3 19>;
1724		- rockchip,usb3-host-disable = <0x2444 0 16>;
1725		- rockchip,usb3-host-port = <0x2444 12 28>;
1726		- rockchip,external-psm = <0xe594 14 30>;
1727		- rockchip,pipe-status = <0xe5c0 16 16>;
1728		- rockchip,uphy-dp-sel = <0x6268 3 19>;
1729	1729	status = "disabled";
1730	1730
1731	1731	tcphy1_dp: dp-port {
..	..	@@ -1830,8 +1830,8 @@
1830	1830	vopl: vop@ff8f0000 {
1831	1831	compatible = "rockchip,rk3399-vop-lit";
1832	1832	reg = <0x0 0xff8f0000 0x0 0x600>,
1833		- <0x0 0xff8f1c00 0x0 0x200>,
1834		- <0x0 0xff8f2000 0x0 0x400>;
	1833	+ <0x0 0xff8f1c00 0x0 0x200>,
	1834	+ <0x0 0xff8f2000 0x0 0x400>;
1835	1835	reg-names = "regs", "cabc_lut", "gamma_lut";
1836	1836	interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1837	1837	clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>, <&cru DCLK_VOP1_DIV>;
..	..	@@ -1861,14 +1861,14 @@
1861	1861	remote-endpoint = <&hdmi_in_vopl>;
1862	1862	};
1863	1863
1864		- vopl_out_dp: endpoint@3 {
	1864	+ vopl_out_dsi1: endpoint@3 {
1865	1865	reg = <3>;
1866		- remote-endpoint = <&dp_in_vopl>;
	1866	+ remote-endpoint = <&dsi1_in_vopl>;
1867	1867	};
1868	1868
1869		- vopl_out_dsi1: endpoint@4 {
	1869	+ vopl_out_dp: endpoint@4 {
1870	1870	reg = <4>;
1871		- remote-endpoint = <&dsi1_in_vopl>;
	1871	+ remote-endpoint = <&dp_in_vopl>;
1872	1872	};
1873	1873	};
1874	1874	};
..	..	@@ -1893,14 +1893,15 @@
1893	1893	clock-names = "aclk", "iface";
1894	1894	power-domains = <&power RK3399_PD_VOPL>;
1895	1895	#iommu-cells = <0>;
	1896	+ rockchip,disable-device-link-resume;
1896	1897	status = "disabled";
1897	1898	};
1898	1899
1899	1900	vopb: vop@ff900000 {
1900	1901	compatible = "rockchip,rk3399-vop-big";
1901	1902	reg = <0x0 0xff900000 0x0 0x600>,
1902		- <0x0 0xff901c00 0x0 0x200>,
1903		- <0x0 0xff902000 0x0 0x1000>;
	1903	+ <0x0 0xff901c00 0x0 0x200>,
	1904	+ <0x0 0xff902000 0x0 0x1000>;
1904	1905	reg-names = "regs", "cabc_lut", "gamma_lut";
1905	1906	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1906	1907	clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>, <&cru DCLK_VOP0_DIV>;
..	..	@@ -1930,14 +1931,14 @@
1930	1931	remote-endpoint = <&hdmi_in_vopb>;
1931	1932	};
1932	1933
1933		- vopb_out_dp: endpoint@3 {
	1934	+ vopb_out_dsi1: endpoint@3 {
1934	1935	reg = <3>;
1935		- remote-endpoint = <&dp_in_vopb>;
	1936	+ remote-endpoint = <&dsi1_in_vopb>;
1936	1937	};
1937	1938
1938		- vopb_out_dsi1: endpoint@4 {
	1939	+ vopb_out_dp: endpoint@4 {
1939	1940	reg = <4>;
1940		- remote-endpoint = <&dsi1_in_vopb>;
	1941	+ remote-endpoint = <&dp_in_vopb>;
1941	1942	};
1942	1943	};
1943	1944	};
..	..	@@ -1962,6 +1963,7 @@
1962	1963	clock-names = "aclk", "iface";
1963	1964	power-domains = <&power RK3399_PD_VOPB>;
1964	1965	#iommu-cells = <0>;
	1966	+ rockchip,disable-device-link-resume;
1965	1967	status = "disabled";
1966	1968	};
1967	1969
..	..	@@ -2048,10 +2050,10 @@
2048	2050	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
2049	2051	clocks = <&cru PCLK_HDMI_CTRL>,
2050	2052	<&cru SCLK_HDMI_SFR>,
2051		- <&cru PLL_VPLL>,
	2053	+ <&cru SCLK_HDMI_CEC>,
2052	2054	<&cru PCLK_VIO_GRF>,
2053		- <&cru SCLK_HDMI_CEC>;
2054		- clock-names = "iahb", "isfr", "vpll", "grf", "cec";
	2055	+ <&cru PLL_VPLL>;
	2056	+ clock-names = "iahb", "isfr", "cec", "grf", "vpll";
2055	2057	power-domains = <&power RK3399_PD_HDCP>;
2056	2058	reg-io-width = <4>;
2057	2059	rockchip,grf = <&grf>;
..	..	@@ -2077,23 +2079,27 @@
2077	2079	};
2078	2080	};
2079	2081
2080		- dsi: dsi@ff960000 {
2081		- compatible = "rockchip,rk3399-mipi-dsi";
	2082	+ dsi: mipi_dsi: dsi@ff960000 {
	2083	+ compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
2082	2084	reg = <0x0 0xff960000 0x0 0x8000>;
2083	2085	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
2084	2086	clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
2085		- <&cru SCLK_DPHY_TX0_CFG>;
2086		- clock-names = "ref", "pclk", "phy_cfg";
	2087	+ <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
	2088	+ clock-names = "ref", "pclk", "phy_cfg", "grf";
2087	2089	power-domains = <&power RK3399_PD_VIO>;
2088	2090	resets = <&cru SRST_P_MIPI_DSI0>;
2089	2091	reset-names = "apb";
2090	2092	rockchip,grf = <&grf>;
2091		- status = "disabled";
2092	2093	#address-cells = <1>;
2093	2094	#size-cells = <0>;
	2095	+ status = "disabled";
2094	2096
2095	2097	ports {
2096		- port {
	2098	+ #address-cells = <1>;
	2099	+ #size-cells = <0>;
	2100	+
	2101	+ port@0 {
	2102	+ reg = <0>;
2097	2103	#address-cells = <1>;
2098	2104	#size-cells = <0>;
2099	2105
..	..	@@ -2101,7 +2107,6 @@
2101	2107	reg = <0>;
2102	2108	remote-endpoint = <&vopb_out_dsi>;
2103	2109	};
2104		-
2105	2110	dsi_in_vopl: endpoint@1 {
2106	2111	reg = <1>;
2107	2112	remote-endpoint = <&vopl_out_dsi>;
..	..	@@ -2110,23 +2115,27 @@
2110	2115	};
2111	2116	};
2112	2117
2113		- dsi1: dsi@ff968000 {
2114		- compatible = "rockchip,rk3399-mipi-dsi";
	2118	+ dsi1: mipi_dsi1: dsi@ff968000 {
	2119	+ compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
2115	2120	reg = <0x0 0xff968000 0x0 0x8000>;
2116	2121	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
2117	2122	clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
2118		- <&cru SCLK_DPHY_TX1RX1_CFG>;
2119		- clock-names = "ref", "pclk", "phy_cfg";
	2123	+ <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
	2124	+ clock-names = "ref", "pclk", "phy_cfg", "grf";
2120	2125	power-domains = <&power RK3399_PD_VIO>;
2121	2126	resets = <&cru SRST_P_MIPI_DSI1>;
2122	2127	reset-names = "apb";
2123	2128	rockchip,grf = <&grf>;
2124		- status = "disabled";
2125	2129	#address-cells = <1>;
2126	2130	#size-cells = <0>;
	2131	+ status = "disabled";
2127	2132
2128	2133	ports {
2129		- port {
	2134	+ #address-cells = <1>;
	2135	+ #size-cells = <0>;
	2136	+
	2137	+ port@0 {
	2138	+ reg = <0>;
2130	2139	#address-cells = <1>;
2131	2140	#size-cells = <0>;
2132	2141
..	..	@@ -2147,9 +2156,9 @@
2147	2156	compatible = "rockchip,rk3399-mipi-dphy";
2148	2157	reg = <0x0 0xff968000 0x0 0x8000>;
2149	2158	clocks = <&cru SCLK_MIPIDPHY_REF>,
2150		- <&cru SCLK_DPHY_TX1RX1_CFG>,
2151		- <&cru PCLK_VIO_GRF>,
2152		- <&cru PCLK_MIPI_DSI1>;
	2159	+ <&cru SCLK_DPHY_TX1RX1_CFG>,
	2160	+ <&cru PCLK_VIO_GRF>,
	2161	+ <&cru PCLK_MIPI_DSI1>;
2153	2162	clock-names = "dphy-ref", "dphy-cfg",
2154	2163	"grf", "pclk_mipi_dsi";
2155	2164	rockchip,grf = <&grf>;
..	..	@@ -2161,8 +2170,10 @@
2161	2170	compatible = "rockchip,rk3399-edp";
2162	2171	reg = <0x0 0xff970000 0x0 0x8000>;
2163	2172	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
2164		- clocks = <&cru PCLK_EDP_CTRL>;
2165		- clock-names = "dp";
	2173	+ clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
	2174	+ clock-names = "dp", "pclk", "grf";
	2175	+ pinctrl-names = "default";
	2176	+ pinctrl-0 = <&edp_hpd>;
2166	2177	power-domains = <&power RK3399_PD_EDP>;
2167	2178	resets = <&cru SRST_P_EDP_CTRL>;
2168	2179	reset-names = "dp";
..	..	@@ -2172,8 +2183,7 @@
2172	2183	ports {
2173	2184	#address-cells = <1>;
2174	2185	#size-cells = <0>;
2175		-
2176		- port@0 {
	2186	+ edp_in: port@0 {
2177	2187	reg = <0>;
2178	2188	#address-cells = <1>;
2179	2189	#size-cells = <0>;
..	..	@@ -2191,31 +2201,19 @@
2191	2201	};
2192	2202	};
2193	2203
2194		- hdmi_hdcp2: hdmi-hdcp2@ff988000 {
2195		- compatible = "rockchip,rk3399-hdmi-hdcp2";
2196		- reg = <0x0 0xff988000 0x0 0x2000>;
2197		- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH 0>;
2198		- clocks = <&cru ACLK_HDCP22>, <&cru PCLK_HDCP22>,
2199		- <&cru HCLK_HDCP22>;
2200		- clock-names ="aclk_hdcp2", "pclk_hdcp2", "hdcp2_clk_hdmi";
2201		- status = "disabled";
2202		- };
2203		-
2204	2204	gpu: gpu@ff9a0000 {
2205	2205	compatible = "arm,malit860",
2206	2206	"arm,malit86x",
2207	2207	"arm,malit8xx",
2208	2208	"arm,mali-midgard";
2209		-
2210	2209	reg = <0x0 0xff9a0000 0x0 0x10000>;
2211		- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
2212		- <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
2213		- <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
2214		- interrupt-names = "GPU", "JOB", "MMU";
2215		-
	2210	+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
	2211	+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
	2212	+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
	2213	+ interrupt-names = "job", "mmu", "gpu";
2216	2214	clocks = <&cru ACLK_GPU>;
2217	2215	clock-names = "clk_mali";
2218		- #cooling-cells = <2>; /* min followed by max */
	2216	+ #cooling-cells = <2>;
2219	2217	power-domains = <&power RK3399_PD_GPU>;
2220	2218	power-off-delay-ms = <200>;
2221	2219	upthreshold = <40>;
..	..	@@ -2393,6 +2391,11 @@
2393	2391	bias-disable;
2394	2392	};
2395	2393
	2394	+ pcfg_pull_none_10ma: pcfg-pull-none-10ma {
	2395	+ bias-disable;
	2396	+ drive-strength = <10>;
	2397	+ };
	2398	+
2396	2399	pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2397	2400	bias-disable;
2398	2401	drive-strength = <12>;
..	..	@@ -2418,19 +2421,14 @@
2418	2421	drive-strength = <2>;
2419	2422	};
2420	2423
2421		- pcfg_pull_none_10ma: pcfg-pull-none-10ma {
2422		- bias-disable;
2423		- drive-strength = <10>;
	2424	+ pcfg_pull_up_8ma: pcfg-pull-up-8ma {
	2425	+ bias-pull-up;
	2426	+ drive-strength = <8>;
2424	2427	};
2425	2428
2426	2429	pcfg_pull_up_10ma: pcfg-pull-up-10ma {
2427	2430	bias-pull-up;
2428	2431	drive-strength = <10>;
2429		- };
2430		-
2431		- pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2432		- bias-pull-up;
2433		- drive-strength = <8>;
2434	2432	};
2435	2433
2436	2434	pcfg_pull_up_18ma: pcfg-pull-up-18ma {
..	..	@@ -2652,7 +2650,8 @@
2652	2650	};
2653	2651
2654	2652	i2s_8ch_mclk: i2s-8ch-mclk {
2655		- rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>;
	2653	+ rockchip,pins =
	2654	+ <4 RK_PA0 1 &pcfg_pull_none>;
2656	2655	};
2657	2656	};
2658	2657
..	..	@@ -2910,7 +2909,7 @@
2910	2909	};
2911	2910
2912	2911	tsadc {
2913		- otp_gpio: otp-gpio {
	2912	+ otp_pin: otp-pin {
2914	2913	rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2915	2914	};
2916	2915