~hc/RK356X_SDK_RELEASE.git

..	..	@@ -5,10 +5,24 @@
5	5	* Copyright (c) 2018, The Linux Foundation. All rights reserved.
6	6	*/
7	7
	8	+#include <dt-bindings/clock/qcom,camcc-sdm845.h>
	9	+#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
8	10	#include <dt-bindings/clock/qcom,gcc-sdm845.h>
	11	+#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
	12	+#include <dt-bindings/clock/qcom,lpass-sdm845.h>
9	13	#include <dt-bindings/clock/qcom,rpmh.h>
	14	+#include <dt-bindings/clock/qcom,videocc-sdm845.h>
	15	+#include <dt-bindings/interconnect/qcom,osm-l3.h>
	16	+#include <dt-bindings/interconnect/qcom,sdm845.h>
10	17	#include <dt-bindings/interrupt-controller/arm-gic.h>
	18	+#include <dt-bindings/phy/phy-qcom-qusb2.h>
	19	+#include <dt-bindings/power/qcom-rpmpd.h>
	20	+#include <dt-bindings/reset/qcom,sdm845-aoss.h>
	21	+#include <dt-bindings/reset/qcom,sdm845-pdc.h>
	22	+#include <dt-bindings/soc/qcom,apr.h>
11	23	#include <dt-bindings/soc/qcom,rpmh-rsc.h>
	24	+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
	25	+#include <dt-bindings/thermal/thermal.h>
12	26
13	27	/ {
14	28	interrupt-parent = <&intc>;
..	..	@@ -64,24 +78,108 @@
64	78	#size-cells = <2>;
65	79	ranges;
66	80
67		- memory@85fc0000 {
	81	+ hyp_mem: memory@85700000 {
	82	+ reg = <0 0x85700000 0 0x600000>;
	83	+ no-map;
	84	+ };
	85	+
	86	+ xbl_mem: memory@85e00000 {
	87	+ reg = <0 0x85e00000 0 0x100000>;
	88	+ no-map;
	89	+ };
	90	+
	91	+ aop_mem: memory@85fc0000 {
68	92	reg = <0 0x85fc0000 0 0x20000>;
69	93	no-map;
70	94	};
71	95
72		- memory@85fe0000 {
	96	+ aop_cmd_db_mem: memory@85fe0000 {
73	97	compatible = "qcom,cmd-db";
74		- reg = <0x0 0x85fe0000 0x0 0x20000>;
	98	+ reg = <0x0 0x85fe0000 0 0x20000>;
75	99	no-map;
76	100	};
77	101
78	102	smem_mem: memory@86000000 {
79		- reg = <0x0 0x86000000 0x0 0x200000>;
	103	+ reg = <0x0 0x86000000 0 0x200000>;
80	104	no-map;
81	105	};
82	106
83		- memory@86200000 {
	107	+ tz_mem: memory@86200000 {
84	108	reg = <0 0x86200000 0 0x2d00000>;
	109	+ no-map;
	110	+ };
	111	+
	112	+ rmtfs_mem: memory@88f00000 {
	113	+ compatible = "qcom,rmtfs-mem";
	114	+ reg = <0 0x88f00000 0 0x200000>;
	115	+ no-map;
	116	+
	117	+ qcom,client-id = <1>;
	118	+ qcom,vmid = <15>;
	119	+ };
	120	+
	121	+ qseecom_mem: memory@8ab00000 {
	122	+ reg = <0 0x8ab00000 0 0x1400000>;
	123	+ no-map;
	124	+ };
	125	+
	126	+ camera_mem: memory@8bf00000 {
	127	+ reg = <0 0x8bf00000 0 0x500000>;
	128	+ no-map;
	129	+ };
	130	+
	131	+ ipa_fw_mem: memory@8c400000 {
	132	+ reg = <0 0x8c400000 0 0x10000>;
	133	+ no-map;
	134	+ };
	135	+
	136	+ ipa_gsi_mem: memory@8c410000 {
	137	+ reg = <0 0x8c410000 0 0x5000>;
	138	+ no-map;
	139	+ };
	140	+
	141	+ gpu_mem: memory@8c415000 {
	142	+ reg = <0 0x8c415000 0 0x2000>;
	143	+ no-map;
	144	+ };
	145	+
	146	+ adsp_mem: memory@8c500000 {
	147	+ reg = <0 0x8c500000 0 0x1a00000>;
	148	+ no-map;
	149	+ };
	150	+
	151	+ wlan_msa_mem: memory@8df00000 {
	152	+ reg = <0 0x8df00000 0 0x100000>;
	153	+ no-map;
	154	+ };
	155	+
	156	+ mpss_region: memory@8e000000 {
	157	+ reg = <0 0x8e000000 0 0x7800000>;
	158	+ no-map;
	159	+ };
	160	+
	161	+ venus_mem: memory@95800000 {
	162	+ reg = <0 0x95800000 0 0x500000>;
	163	+ no-map;
	164	+ };
	165	+
	166	+ cdsp_mem: memory@95d00000 {
	167	+ reg = <0 0x95d00000 0 0x800000>;
	168	+ no-map;
	169	+ };
	170	+
	171	+ mba_region: memory@96500000 {
	172	+ reg = <0 0x96500000 0 0x200000>;
	173	+ no-map;
	174	+ };
	175	+
	176	+ slpi_mem: memory@96700000 {
	177	+ reg = <0 0x96700000 0 0x1400000>;
	178	+ no-map;
	179	+ };
	180	+
	181	+ spss_mem: memory@97b00000 {
	182	+ reg = <0 0x97b00000 0 0x100000>;
85	183	no-map;
86	184	};
87	185	};
..	..	@@ -95,6 +193,16 @@
95	193	compatible = "qcom,kryo385";
96	194	reg = <0x0 0x0>;
97	195	enable-method = "psci";
	196	+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
	197	+ &LITTLE_CPU_SLEEP_1
	198	+ &CLUSTER_SLEEP_0>;
	199	+ capacity-dmips-mhz = <611>;
	200	+ dynamic-power-coefficient = <154>;
	201	+ qcom,freq-domain = <&cpufreq_hw 0>;
	202	+ operating-points-v2 = <&cpu0_opp_table>;
	203	+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
	204	+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
	205	+ #cooling-cells = <2>;
98	206	next-level-cache = <&L2_0>;
99	207	L2_0: l2-cache {
100	208	compatible = "cache";
..	..	@@ -110,6 +218,16 @@
110	218	compatible = "qcom,kryo385";
111	219	reg = <0x0 0x100>;
112	220	enable-method = "psci";
	221	+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
	222	+ &LITTLE_CPU_SLEEP_1
	223	+ &CLUSTER_SLEEP_0>;
	224	+ capacity-dmips-mhz = <611>;
	225	+ dynamic-power-coefficient = <154>;
	226	+ qcom,freq-domain = <&cpufreq_hw 0>;
	227	+ operating-points-v2 = <&cpu0_opp_table>;
	228	+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
	229	+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
	230	+ #cooling-cells = <2>;
113	231	next-level-cache = <&L2_100>;
114	232	L2_100: l2-cache {
115	233	compatible = "cache";
..	..	@@ -122,6 +240,16 @@
122	240	compatible = "qcom,kryo385";
123	241	reg = <0x0 0x200>;
124	242	enable-method = "psci";
	243	+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
	244	+ &LITTLE_CPU_SLEEP_1
	245	+ &CLUSTER_SLEEP_0>;
	246	+ capacity-dmips-mhz = <611>;
	247	+ dynamic-power-coefficient = <154>;
	248	+ qcom,freq-domain = <&cpufreq_hw 0>;
	249	+ operating-points-v2 = <&cpu0_opp_table>;
	250	+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
	251	+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
	252	+ #cooling-cells = <2>;
125	253	next-level-cache = <&L2_200>;
126	254	L2_200: l2-cache {
127	255	compatible = "cache";
..	..	@@ -134,6 +262,16 @@
134	262	compatible = "qcom,kryo385";
135	263	reg = <0x0 0x300>;
136	264	enable-method = "psci";
	265	+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
	266	+ &LITTLE_CPU_SLEEP_1
	267	+ &CLUSTER_SLEEP_0>;
	268	+ capacity-dmips-mhz = <611>;
	269	+ dynamic-power-coefficient = <154>;
	270	+ qcom,freq-domain = <&cpufreq_hw 0>;
	271	+ operating-points-v2 = <&cpu0_opp_table>;
	272	+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
	273	+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
	274	+ #cooling-cells = <2>;
137	275	next-level-cache = <&L2_300>;
138	276	L2_300: l2-cache {
139	277	compatible = "cache";
..	..	@@ -146,6 +284,16 @@
146	284	compatible = "qcom,kryo385";
147	285	reg = <0x0 0x400>;
148	286	enable-method = "psci";
	287	+ capacity-dmips-mhz = <1024>;
	288	+ cpu-idle-states = <&BIG_CPU_SLEEP_0
	289	+ &BIG_CPU_SLEEP_1
	290	+ &CLUSTER_SLEEP_0>;
	291	+ dynamic-power-coefficient = <442>;
	292	+ qcom,freq-domain = <&cpufreq_hw 1>;
	293	+ operating-points-v2 = <&cpu4_opp_table>;
	294	+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
	295	+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
	296	+ #cooling-cells = <2>;
149	297	next-level-cache = <&L2_400>;
150	298	L2_400: l2-cache {
151	299	compatible = "cache";
..	..	@@ -158,6 +306,16 @@
158	306	compatible = "qcom,kryo385";
159	307	reg = <0x0 0x500>;
160	308	enable-method = "psci";
	309	+ capacity-dmips-mhz = <1024>;
	310	+ cpu-idle-states = <&BIG_CPU_SLEEP_0
	311	+ &BIG_CPU_SLEEP_1
	312	+ &CLUSTER_SLEEP_0>;
	313	+ dynamic-power-coefficient = <442>;
	314	+ qcom,freq-domain = <&cpufreq_hw 1>;
	315	+ operating-points-v2 = <&cpu4_opp_table>;
	316	+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
	317	+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
	318	+ #cooling-cells = <2>;
161	319	next-level-cache = <&L2_500>;
162	320	L2_500: l2-cache {
163	321	compatible = "cache";
..	..	@@ -170,6 +328,16 @@
170	328	compatible = "qcom,kryo385";
171	329	reg = <0x0 0x600>;
172	330	enable-method = "psci";
	331	+ capacity-dmips-mhz = <1024>;
	332	+ cpu-idle-states = <&BIG_CPU_SLEEP_0
	333	+ &BIG_CPU_SLEEP_1
	334	+ &CLUSTER_SLEEP_0>;
	335	+ dynamic-power-coefficient = <442>;
	336	+ qcom,freq-domain = <&cpufreq_hw 1>;
	337	+ operating-points-v2 = <&cpu4_opp_table>;
	338	+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
	339	+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
	340	+ #cooling-cells = <2>;
173	341	next-level-cache = <&L2_600>;
174	342	L2_600: l2-cache {
175	343	compatible = "cache";
..	..	@@ -182,11 +350,371 @@
182	350	compatible = "qcom,kryo385";
183	351	reg = <0x0 0x700>;
184	352	enable-method = "psci";
	353	+ capacity-dmips-mhz = <1024>;
	354	+ cpu-idle-states = <&BIG_CPU_SLEEP_0
	355	+ &BIG_CPU_SLEEP_1
	356	+ &CLUSTER_SLEEP_0>;
	357	+ dynamic-power-coefficient = <442>;
	358	+ qcom,freq-domain = <&cpufreq_hw 1>;
	359	+ operating-points-v2 = <&cpu4_opp_table>;
	360	+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
	361	+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
	362	+ #cooling-cells = <2>;
185	363	next-level-cache = <&L2_700>;
186	364	L2_700: l2-cache {
187	365	compatible = "cache";
188	366	next-level-cache = <&L3_0>;
189	367	};
	368	+ };
	369	+
	370	+ cpu-map {
	371	+ cluster0 {
	372	+ core0 {
	373	+ cpu = <&CPU0>;
	374	+ };
	375	+
	376	+ core1 {
	377	+ cpu = <&CPU1>;
	378	+ };
	379	+
	380	+ core2 {
	381	+ cpu = <&CPU2>;
	382	+ };
	383	+
	384	+ core3 {
	385	+ cpu = <&CPU3>;
	386	+ };
	387	+
	388	+ core4 {
	389	+ cpu = <&CPU4>;
	390	+ };
	391	+
	392	+ core5 {
	393	+ cpu = <&CPU5>;
	394	+ };
	395	+
	396	+ core6 {
	397	+ cpu = <&CPU6>;
	398	+ };
	399	+
	400	+ core7 {
	401	+ cpu = <&CPU7>;
	402	+ };
	403	+ };
	404	+ };
	405	+
	406	+ idle-states {
	407	+ entry-method = "psci";
	408	+
	409	+ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
	410	+ compatible = "arm,idle-state";
	411	+ idle-state-name = "little-power-down";
	412	+ arm,psci-suspend-param = <0x40000003>;
	413	+ entry-latency-us = <350>;
	414	+ exit-latency-us = <461>;
	415	+ min-residency-us = <1890>;
	416	+ local-timer-stop;
	417	+ };
	418	+
	419	+ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
	420	+ compatible = "arm,idle-state";
	421	+ idle-state-name = "little-rail-power-down";
	422	+ arm,psci-suspend-param = <0x40000004>;
	423	+ entry-latency-us = <360>;
	424	+ exit-latency-us = <531>;
	425	+ min-residency-us = <3934>;
	426	+ local-timer-stop;
	427	+ };
	428	+
	429	+ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
	430	+ compatible = "arm,idle-state";
	431	+ idle-state-name = "big-power-down";
	432	+ arm,psci-suspend-param = <0x40000003>;
	433	+ entry-latency-us = <264>;
	434	+ exit-latency-us = <621>;
	435	+ min-residency-us = <952>;
	436	+ local-timer-stop;
	437	+ };
	438	+
	439	+ BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
	440	+ compatible = "arm,idle-state";
	441	+ idle-state-name = "big-rail-power-down";
	442	+ arm,psci-suspend-param = <0x40000004>;
	443	+ entry-latency-us = <702>;
	444	+ exit-latency-us = <1061>;
	445	+ min-residency-us = <4488>;
	446	+ local-timer-stop;
	447	+ };
	448	+
	449	+ CLUSTER_SLEEP_0: cluster-sleep-0 {
	450	+ compatible = "arm,idle-state";
	451	+ idle-state-name = "cluster-power-down";
	452	+ arm,psci-suspend-param = <0x400000F4>;
	453	+ entry-latency-us = <3263>;
	454	+ exit-latency-us = <6562>;
	455	+ min-residency-us = <9987>;
	456	+ local-timer-stop;
	457	+ };
	458	+ };
	459	+ };
	460	+
	461	+ cpu0_opp_table: cpu0_opp_table {
	462	+ compatible = "operating-points-v2";
	463	+ opp-shared;
	464	+
	465	+ cpu0_opp1: opp-300000000 {
	466	+ opp-hz = /bits/ 64 <300000000>;
	467	+ opp-peak-kBps = <800000 4800000>;
	468	+ };
	469	+
	470	+ cpu0_opp2: opp-403200000 {
	471	+ opp-hz = /bits/ 64 <403200000>;
	472	+ opp-peak-kBps = <800000 4800000>;
	473	+ };
	474	+
	475	+ cpu0_opp3: opp-480000000 {
	476	+ opp-hz = /bits/ 64 <480000000>;
	477	+ opp-peak-kBps = <800000 6451200>;
	478	+ };
	479	+
	480	+ cpu0_opp4: opp-576000000 {
	481	+ opp-hz = /bits/ 64 <576000000>;
	482	+ opp-peak-kBps = <800000 6451200>;
	483	+ };
	484	+
	485	+ cpu0_opp5: opp-652800000 {
	486	+ opp-hz = /bits/ 64 <652800000>;
	487	+ opp-peak-kBps = <800000 7680000>;
	488	+ };
	489	+
	490	+ cpu0_opp6: opp-748800000 {
	491	+ opp-hz = /bits/ 64 <748800000>;
	492	+ opp-peak-kBps = <1804000 9216000>;
	493	+ };
	494	+
	495	+ cpu0_opp7: opp-825600000 {
	496	+ opp-hz = /bits/ 64 <825600000>;
	497	+ opp-peak-kBps = <1804000 9216000>;
	498	+ };
	499	+
	500	+ cpu0_opp8: opp-902400000 {
	501	+ opp-hz = /bits/ 64 <902400000>;
	502	+ opp-peak-kBps = <1804000 10444800>;
	503	+ };
	504	+
	505	+ cpu0_opp9: opp-979200000 {
	506	+ opp-hz = /bits/ 64 <979200000>;
	507	+ opp-peak-kBps = <1804000 11980800>;
	508	+ };
	509	+
	510	+ cpu0_opp10: opp-1056000000 {
	511	+ opp-hz = /bits/ 64 <1056000000>;
	512	+ opp-peak-kBps = <1804000 11980800>;
	513	+ };
	514	+
	515	+ cpu0_opp11: opp-1132800000 {
	516	+ opp-hz = /bits/ 64 <1132800000>;
	517	+ opp-peak-kBps = <2188000 13516800>;
	518	+ };
	519	+
	520	+ cpu0_opp12: opp-1228800000 {
	521	+ opp-hz = /bits/ 64 <1228800000>;
	522	+ opp-peak-kBps = <2188000 15052800>;
	523	+ };
	524	+
	525	+ cpu0_opp13: opp-1324800000 {
	526	+ opp-hz = /bits/ 64 <1324800000>;
	527	+ opp-peak-kBps = <2188000 16588800>;
	528	+ };
	529	+
	530	+ cpu0_opp14: opp-1420800000 {
	531	+ opp-hz = /bits/ 64 <1420800000>;
	532	+ opp-peak-kBps = <3072000 18124800>;
	533	+ };
	534	+
	535	+ cpu0_opp15: opp-1516800000 {
	536	+ opp-hz = /bits/ 64 <1516800000>;
	537	+ opp-peak-kBps = <3072000 19353600>;
	538	+ };
	539	+
	540	+ cpu0_opp16: opp-1612800000 {
	541	+ opp-hz = /bits/ 64 <1612800000>;
	542	+ opp-peak-kBps = <4068000 19353600>;
	543	+ };
	544	+
	545	+ cpu0_opp17: opp-1689600000 {
	546	+ opp-hz = /bits/ 64 <1689600000>;
	547	+ opp-peak-kBps = <4068000 20889600>;
	548	+ };
	549	+
	550	+ cpu0_opp18: opp-1766400000 {
	551	+ opp-hz = /bits/ 64 <1766400000>;
	552	+ opp-peak-kBps = <4068000 22425600>;
	553	+ };
	554	+ };
	555	+
	556	+ cpu4_opp_table: cpu4_opp_table {
	557	+ compatible = "operating-points-v2";
	558	+ opp-shared;
	559	+
	560	+ cpu4_opp1: opp-300000000 {
	561	+ opp-hz = /bits/ 64 <300000000>;
	562	+ opp-peak-kBps = <800000 4800000>;
	563	+ };
	564	+
	565	+ cpu4_opp2: opp-403200000 {
	566	+ opp-hz = /bits/ 64 <403200000>;
	567	+ opp-peak-kBps = <800000 4800000>;
	568	+ };
	569	+
	570	+ cpu4_opp3: opp-480000000 {
	571	+ opp-hz = /bits/ 64 <480000000>;
	572	+ opp-peak-kBps = <1804000 4800000>;
	573	+ };
	574	+
	575	+ cpu4_opp4: opp-576000000 {
	576	+ opp-hz = /bits/ 64 <576000000>;
	577	+ opp-peak-kBps = <1804000 4800000>;
	578	+ };
	579	+
	580	+ cpu4_opp5: opp-652800000 {
	581	+ opp-hz = /bits/ 64 <652800000>;
	582	+ opp-peak-kBps = <1804000 4800000>;
	583	+ };
	584	+
	585	+ cpu4_opp6: opp-748800000 {
	586	+ opp-hz = /bits/ 64 <748800000>;
	587	+ opp-peak-kBps = <1804000 4800000>;
	588	+ };
	589	+
	590	+ cpu4_opp7: opp-825600000 {
	591	+ opp-hz = /bits/ 64 <825600000>;
	592	+ opp-peak-kBps = <2188000 9216000>;
	593	+ };
	594	+
	595	+ cpu4_opp8: opp-902400000 {
	596	+ opp-hz = /bits/ 64 <902400000>;
	597	+ opp-peak-kBps = <2188000 9216000>;
	598	+ };
	599	+
	600	+ cpu4_opp9: opp-979200000 {
	601	+ opp-hz = /bits/ 64 <979200000>;
	602	+ opp-peak-kBps = <2188000 9216000>;
	603	+ };
	604	+
	605	+ cpu4_opp10: opp-1056000000 {
	606	+ opp-hz = /bits/ 64 <1056000000>;
	607	+ opp-peak-kBps = <3072000 9216000>;
	608	+ };
	609	+
	610	+ cpu4_opp11: opp-1132800000 {
	611	+ opp-hz = /bits/ 64 <1132800000>;
	612	+ opp-peak-kBps = <3072000 11980800>;
	613	+ };
	614	+
	615	+ cpu4_opp12: opp-1209600000 {
	616	+ opp-hz = /bits/ 64 <1209600000>;
	617	+ opp-peak-kBps = <4068000 11980800>;
	618	+ };
	619	+
	620	+ cpu4_opp13: opp-1286400000 {
	621	+ opp-hz = /bits/ 64 <1286400000>;
	622	+ opp-peak-kBps = <4068000 11980800>;
	623	+ };
	624	+
	625	+ cpu4_opp14: opp-1363200000 {
	626	+ opp-hz = /bits/ 64 <1363200000>;
	627	+ opp-peak-kBps = <4068000 15052800>;
	628	+ };
	629	+
	630	+ cpu4_opp15: opp-1459200000 {
	631	+ opp-hz = /bits/ 64 <1459200000>;
	632	+ opp-peak-kBps = <4068000 15052800>;
	633	+ };
	634	+
	635	+ cpu4_opp16: opp-1536000000 {
	636	+ opp-hz = /bits/ 64 <1536000000>;
	637	+ opp-peak-kBps = <5412000 15052800>;
	638	+ };
	639	+
	640	+ cpu4_opp17: opp-1612800000 {
	641	+ opp-hz = /bits/ 64 <1612800000>;
	642	+ opp-peak-kBps = <5412000 15052800>;
	643	+ };
	644	+
	645	+ cpu4_opp18: opp-1689600000 {
	646	+ opp-hz = /bits/ 64 <1689600000>;
	647	+ opp-peak-kBps = <5412000 19353600>;
	648	+ };
	649	+
	650	+ cpu4_opp19: opp-1766400000 {
	651	+ opp-hz = /bits/ 64 <1766400000>;
	652	+ opp-peak-kBps = <6220000 19353600>;
	653	+ };
	654	+
	655	+ cpu4_opp20: opp-1843200000 {
	656	+ opp-hz = /bits/ 64 <1843200000>;
	657	+ opp-peak-kBps = <6220000 19353600>;
	658	+ };
	659	+
	660	+ cpu4_opp21: opp-1920000000 {
	661	+ opp-hz = /bits/ 64 <1920000000>;
	662	+ opp-peak-kBps = <7216000 19353600>;
	663	+ };
	664	+
	665	+ cpu4_opp22: opp-1996800000 {
	666	+ opp-hz = /bits/ 64 <1996800000>;
	667	+ opp-peak-kBps = <7216000 20889600>;
	668	+ };
	669	+
	670	+ cpu4_opp23: opp-2092800000 {
	671	+ opp-hz = /bits/ 64 <2092800000>;
	672	+ opp-peak-kBps = <7216000 20889600>;
	673	+ };
	674	+
	675	+ cpu4_opp24: opp-2169600000 {
	676	+ opp-hz = /bits/ 64 <2169600000>;
	677	+ opp-peak-kBps = <7216000 20889600>;
	678	+ };
	679	+
	680	+ cpu4_opp25: opp-2246400000 {
	681	+ opp-hz = /bits/ 64 <2246400000>;
	682	+ opp-peak-kBps = <7216000 20889600>;
	683	+ };
	684	+
	685	+ cpu4_opp26: opp-2323200000 {
	686	+ opp-hz = /bits/ 64 <2323200000>;
	687	+ opp-peak-kBps = <7216000 20889600>;
	688	+ };
	689	+
	690	+ cpu4_opp27: opp-2400000000 {
	691	+ opp-hz = /bits/ 64 <2400000000>;
	692	+ opp-peak-kBps = <7216000 22425600>;
	693	+ };
	694	+
	695	+ cpu4_opp28: opp-2476800000 {
	696	+ opp-hz = /bits/ 64 <2476800000>;
	697	+ opp-peak-kBps = <7216000 22425600>;
	698	+ };
	699	+
	700	+ cpu4_opp29: opp-2553600000 {
	701	+ opp-hz = /bits/ 64 <2553600000>;
	702	+ opp-peak-kBps = <7216000 22425600>;
	703	+ };
	704	+
	705	+ cpu4_opp30: opp-2649600000 {
	706	+ opp-hz = /bits/ 64 <2649600000>;
	707	+ opp-peak-kBps = <7216000 22425600>;
	708	+ };
	709	+
	710	+ cpu4_opp31: opp-2745600000 {
	711	+ opp-hz = /bits/ 64 <2745600000>;
	712	+ opp-peak-kBps = <7216000 25497600>;
	713	+ };
	714	+
	715	+ cpu4_opp32: opp-2803200000 {
	716	+ opp-hz = /bits/ 64 <2803200000>;
	717	+ opp-peak-kBps = <7216000 25497600>;
190	718	};
191	719	};
192	720
..	..	@@ -218,6 +746,195 @@
218	746	};
219	747	};
220	748
	749	+ firmware {
	750	+ scm {
	751	+ compatible = "qcom,scm-sdm845", "qcom,scm";
	752	+ };
	753	+ };
	754	+
	755	+ adsp_pas: remoteproc-adsp {
	756	+ compatible = "qcom,sdm845-adsp-pas";
	757	+
	758	+ interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
	759	+ <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	760	+ <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	761	+ <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	762	+ <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
	763	+ interrupt-names = "wdog", "fatal", "ready",
	764	+ "handover", "stop-ack";
	765	+
	766	+ clocks = <&rpmhcc RPMH_CXO_CLK>;
	767	+ clock-names = "xo";
	768	+
	769	+ memory-region = <&adsp_mem>;
	770	+
	771	+ qcom,smem-states = <&adsp_smp2p_out 0>;
	772	+ qcom,smem-state-names = "stop";
	773	+
	774	+ status = "disabled";
	775	+
	776	+ glink-edge {
	777	+ interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
	778	+ label = "lpass";
	779	+ qcom,remote-pid = <2>;
	780	+ mboxes = <&apss_shared 8>;
	781	+
	782	+ apr {
	783	+ compatible = "qcom,apr-v2";
	784	+ qcom,glink-channels = "apr_audio_svc";
	785	+ qcom,apr-domain = <APR_DOMAIN_ADSP>;
	786	+ #address-cells = <1>;
	787	+ #size-cells = <0>;
	788	+ qcom,intents = <512 20>;
	789	+
	790	+ apr-service@3 {
	791	+ reg = <APR_SVC_ADSP_CORE>;
	792	+ compatible = "qcom,q6core";
	793	+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
	794	+ };
	795	+
	796	+ q6afe: apr-service@4 {
	797	+ compatible = "qcom,q6afe";
	798	+ reg = <APR_SVC_AFE>;
	799	+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
	800	+ q6afedai: dais {
	801	+ compatible = "qcom,q6afe-dais";
	802	+ #address-cells = <1>;
	803	+ #size-cells = <0>;
	804	+ #sound-dai-cells = <1>;
	805	+ };
	806	+ };
	807	+
	808	+ q6asm: apr-service@7 {
	809	+ compatible = "qcom,q6asm";
	810	+ reg = <APR_SVC_ASM>;
	811	+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
	812	+ q6asmdai: dais {
	813	+ compatible = "qcom,q6asm-dais";
	814	+ #address-cells = <1>;
	815	+ #size-cells = <0>;
	816	+ #sound-dai-cells = <1>;
	817	+ iommus = <&apps_smmu 0x1821 0x0>;
	818	+ };
	819	+ };
	820	+
	821	+ q6adm: apr-service@8 {
	822	+ compatible = "qcom,q6adm";
	823	+ reg = <APR_SVC_ADM>;
	824	+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
	825	+ q6routing: routing {
	826	+ compatible = "qcom,q6adm-routing";
	827	+ #sound-dai-cells = <0>;
	828	+ };
	829	+ };
	830	+ };
	831	+
	832	+ fastrpc {
	833	+ compatible = "qcom,fastrpc";
	834	+ qcom,glink-channels = "fastrpcglink-apps-dsp";
	835	+ label = "adsp";
	836	+ #address-cells = <1>;
	837	+ #size-cells = <0>;
	838	+
	839	+ compute-cb@3 {
	840	+ compatible = "qcom,fastrpc-compute-cb";
	841	+ reg = <3>;
	842	+ iommus = <&apps_smmu 0x1823 0x0>;
	843	+ };
	844	+
	845	+ compute-cb@4 {
	846	+ compatible = "qcom,fastrpc-compute-cb";
	847	+ reg = <4>;
	848	+ iommus = <&apps_smmu 0x1824 0x0>;
	849	+ };
	850	+ };
	851	+ };
	852	+ };
	853	+
	854	+ cdsp_pas: remoteproc-cdsp {
	855	+ compatible = "qcom,sdm845-cdsp-pas";
	856	+
	857	+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
	858	+ <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	859	+ <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	860	+ <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	861	+ <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
	862	+ interrupt-names = "wdog", "fatal", "ready",
	863	+ "handover", "stop-ack";
	864	+
	865	+ clocks = <&rpmhcc RPMH_CXO_CLK>;
	866	+ clock-names = "xo";
	867	+
	868	+ memory-region = <&cdsp_mem>;
	869	+
	870	+ qcom,smem-states = <&cdsp_smp2p_out 0>;
	871	+ qcom,smem-state-names = "stop";
	872	+
	873	+ status = "disabled";
	874	+
	875	+ glink-edge {
	876	+ interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
	877	+ label = "turing";
	878	+ qcom,remote-pid = <5>;
	879	+ mboxes = <&apss_shared 4>;
	880	+ fastrpc {
	881	+ compatible = "qcom,fastrpc";
	882	+ qcom,glink-channels = "fastrpcglink-apps-dsp";
	883	+ label = "cdsp";
	884	+ #address-cells = <1>;
	885	+ #size-cells = <0>;
	886	+
	887	+ compute-cb@1 {
	888	+ compatible = "qcom,fastrpc-compute-cb";
	889	+ reg = <1>;
	890	+ iommus = <&apps_smmu 0x1401 0x30>;
	891	+ };
	892	+
	893	+ compute-cb@2 {
	894	+ compatible = "qcom,fastrpc-compute-cb";
	895	+ reg = <2>;
	896	+ iommus = <&apps_smmu 0x1402 0x30>;
	897	+ };
	898	+
	899	+ compute-cb@3 {
	900	+ compatible = "qcom,fastrpc-compute-cb";
	901	+ reg = <3>;
	902	+ iommus = <&apps_smmu 0x1403 0x30>;
	903	+ };
	904	+
	905	+ compute-cb@4 {
	906	+ compatible = "qcom,fastrpc-compute-cb";
	907	+ reg = <4>;
	908	+ iommus = <&apps_smmu 0x1404 0x30>;
	909	+ };
	910	+
	911	+ compute-cb@5 {
	912	+ compatible = "qcom,fastrpc-compute-cb";
	913	+ reg = <5>;
	914	+ iommus = <&apps_smmu 0x1405 0x30>;
	915	+ };
	916	+
	917	+ compute-cb@6 {
	918	+ compatible = "qcom,fastrpc-compute-cb";
	919	+ reg = <6>;
	920	+ iommus = <&apps_smmu 0x1406 0x30>;
	921	+ };
	922	+
	923	+ compute-cb@7 {
	924	+ compatible = "qcom,fastrpc-compute-cb";
	925	+ reg = <7>;
	926	+ iommus = <&apps_smmu 0x1407 0x30>;
	927	+ };
	928	+
	929	+ compute-cb@8 {
	930	+ compatible = "qcom,fastrpc-compute-cb";
	931	+ reg = <8>;
	932	+ iommus = <&apps_smmu 0x1408 0x30>;
	933	+ };
	934	+ };
	935	+ };
	936	+ };
	937	+
221	938	tcsr_mutex: hwlock {
222	939	compatible = "qcom,tcsr-mutex";
223	940	syscon = <&tcsr_mutex_regs 0 0x1000>;
..	..	@@ -230,39 +947,188 @@
230	947	hwlocks = <&tcsr_mutex 3>;
231	948	};
232	949
	950	+ smp2p-cdsp {
	951	+ compatible = "qcom,smp2p";
	952	+ qcom,smem = <94>, <432>;
	953	+
	954	+ interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
	955	+
	956	+ mboxes = <&apss_shared 6>;
	957	+
	958	+ qcom,local-pid = <0>;
	959	+ qcom,remote-pid = <5>;
	960	+
	961	+ cdsp_smp2p_out: master-kernel {
	962	+ qcom,entry-name = "master-kernel";
	963	+ #qcom,smem-state-cells = <1>;
	964	+ };
	965	+
	966	+ cdsp_smp2p_in: slave-kernel {
	967	+ qcom,entry-name = "slave-kernel";
	968	+
	969	+ interrupt-controller;
	970	+ #interrupt-cells = <2>;
	971	+ };
	972	+ };
	973	+
	974	+ smp2p-lpass {
	975	+ compatible = "qcom,smp2p";
	976	+ qcom,smem = <443>, <429>;
	977	+
	978	+ interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
	979	+
	980	+ mboxes = <&apss_shared 10>;
	981	+
	982	+ qcom,local-pid = <0>;
	983	+ qcom,remote-pid = <2>;
	984	+
	985	+ adsp_smp2p_out: master-kernel {
	986	+ qcom,entry-name = "master-kernel";
	987	+ #qcom,smem-state-cells = <1>;
	988	+ };
	989	+
	990	+ adsp_smp2p_in: slave-kernel {
	991	+ qcom,entry-name = "slave-kernel";
	992	+
	993	+ interrupt-controller;
	994	+ #interrupt-cells = <2>;
	995	+ };
	996	+ };
	997	+
	998	+ smp2p-mpss {
	999	+ compatible = "qcom,smp2p";
	1000	+ qcom,smem = <435>, <428>;
	1001	+ interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
	1002	+ mboxes = <&apss_shared 14>;
	1003	+ qcom,local-pid = <0>;
	1004	+ qcom,remote-pid = <1>;
	1005	+
	1006	+ modem_smp2p_out: master-kernel {
	1007	+ qcom,entry-name = "master-kernel";
	1008	+ #qcom,smem-state-cells = <1>;
	1009	+ };
	1010	+
	1011	+ modem_smp2p_in: slave-kernel {
	1012	+ qcom,entry-name = "slave-kernel";
	1013	+ interrupt-controller;
	1014	+ #interrupt-cells = <2>;
	1015	+ };
	1016	+
	1017	+ ipa_smp2p_out: ipa-ap-to-modem {
	1018	+ qcom,entry-name = "ipa";
	1019	+ #qcom,smem-state-cells = <1>;
	1020	+ };
	1021	+
	1022	+ ipa_smp2p_in: ipa-modem-to-ap {
	1023	+ qcom,entry-name = "ipa";
	1024	+ interrupt-controller;
	1025	+ #interrupt-cells = <2>;
	1026	+ };
	1027	+ };
	1028	+
	1029	+ smp2p-slpi {
	1030	+ compatible = "qcom,smp2p";
	1031	+ qcom,smem = <481>, <430>;
	1032	+ interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
	1033	+ mboxes = <&apss_shared 26>;
	1034	+ qcom,local-pid = <0>;
	1035	+ qcom,remote-pid = <3>;
	1036	+
	1037	+ slpi_smp2p_out: master-kernel {
	1038	+ qcom,entry-name = "master-kernel";
	1039	+ #qcom,smem-state-cells = <1>;
	1040	+ };
	1041	+
	1042	+ slpi_smp2p_in: slave-kernel {
	1043	+ qcom,entry-name = "slave-kernel";
	1044	+ interrupt-controller;
	1045	+ #interrupt-cells = <2>;
	1046	+ };
	1047	+ };
	1048	+
233	1049	psci {
234	1050	compatible = "arm,psci-1.0";
235	1051	method = "smc";
236	1052	};
237	1053
238		- soc: soc {
239		- #address-cells = <1>;
240		- #size-cells = <1>;
241		- ranges = <0 0 0 0xffffffff>;
	1054	+ soc: soc@0 {
	1055	+ #address-cells = <2>;
	1056	+ #size-cells = <2>;
	1057	+ ranges = <0 0 0 0 0x10 0>;
	1058	+ dma-ranges = <0 0 0 0 0x10 0>;
242	1059	compatible = "simple-bus";
243	1060
244	1061	gcc: clock-controller@100000 {
245	1062	compatible = "qcom,gcc-sdm845";
246		- reg = <0x100000 0x1f0000>;
	1063	+ reg = <0 0x00100000 0 0x1f0000>;
247	1064	#clock-cells = <1>;
248	1065	#reset-cells = <1>;
249	1066	#power-domain-cells = <1>;
	1067	+ power-domains = <&rpmhpd SDM845_CX>;
	1068	+ };
	1069	+
	1070	+ qfprom@784000 {
	1071	+ compatible = "qcom,qfprom";
	1072	+ reg = <0 0x00784000 0 0x8ff>;
	1073	+ #address-cells = <1>;
	1074	+ #size-cells = <1>;
	1075	+
	1076	+ qusb2p_hstx_trim: hstx-trim-primary@1eb {
	1077	+ reg = <0x1eb 0x1>;
	1078	+ bits = <1 4>;
	1079	+ };
	1080	+
	1081	+ qusb2s_hstx_trim: hstx-trim-secondary@1eb {
	1082	+ reg = <0x1eb 0x2>;
	1083	+ bits = <6 4>;
	1084	+ };
	1085	+ };
	1086	+
	1087	+ rng: rng@793000 {
	1088	+ compatible = "qcom,prng-ee";
	1089	+ reg = <0 0x00793000 0 0x1000>;
	1090	+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
	1091	+ clock-names = "core";
	1092	+ };
	1093	+
	1094	+ qup_opp_table: qup-opp-table {
	1095	+ compatible = "operating-points-v2";
	1096	+
	1097	+ opp-50000000 {
	1098	+ opp-hz = /bits/ 64 <50000000>;
	1099	+ required-opps = <&rpmhpd_opp_min_svs>;
	1100	+ };
	1101	+
	1102	+ opp-75000000 {
	1103	+ opp-hz = /bits/ 64 <75000000>;
	1104	+ required-opps = <&rpmhpd_opp_low_svs>;
	1105	+ };
	1106	+
	1107	+ opp-100000000 {
	1108	+ opp-hz = /bits/ 64 <100000000>;
	1109	+ required-opps = <&rpmhpd_opp_svs>;
	1110	+ };
	1111	+
	1112	+ opp-128000000 {
	1113	+ opp-hz = /bits/ 64 <128000000>;
	1114	+ required-opps = <&rpmhpd_opp_nom>;
	1115	+ };
250	1116	};
251	1117
252	1118	qupv3_id_0: geniqup@8c0000 {
253	1119	compatible = "qcom,geni-se-qup";
254		- reg = <0x8c0000 0x6000>;
	1120	+ reg = <0 0x008c0000 0 0x6000>;
255	1121	clock-names = "m-ahb", "s-ahb";
256	1122	clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
257	1123	<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
258		- #address-cells = <1>;
259		- #size-cells = <1>;
	1124	+ #address-cells = <2>;
	1125	+ #size-cells = <2>;
260	1126	ranges;
261	1127	status = "disabled";
262	1128
263	1129	i2c0: i2c@880000 {
264	1130	compatible = "qcom,geni-i2c";
265		- reg = <0x880000 0x4000>;
	1131	+ reg = <0 0x00880000 0 0x4000>;
266	1132	clock-names = "se";
267	1133	clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
268	1134	pinctrl-names = "default";
..	..	@@ -270,12 +1136,14 @@
270	1136	interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
271	1137	#address-cells = <1>;
272	1138	#size-cells = <0>;
	1139	+ power-domains = <&rpmhpd SDM845_CX>;
	1140	+ operating-points-v2 = <&qup_opp_table>;
273	1141	status = "disabled";
274	1142	};
275	1143
276	1144	spi0: spi@880000 {
277	1145	compatible = "qcom,geni-spi";
278		- reg = <0x880000 0x4000>;
	1146	+ reg = <0 0x00880000 0 0x4000>;
279	1147	clock-names = "se";
280	1148	clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
281	1149	pinctrl-names = "default";
..	..	@@ -286,9 +1154,22 @@
286	1154	status = "disabled";
287	1155	};
288	1156
	1157	+ uart0: serial@880000 {
	1158	+ compatible = "qcom,geni-uart";
	1159	+ reg = <0 0x00880000 0 0x4000>;
	1160	+ clock-names = "se";
	1161	+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
	1162	+ pinctrl-names = "default";
	1163	+ pinctrl-0 = <&qup_uart0_default>;
	1164	+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
	1165	+ power-domains = <&rpmhpd SDM845_CX>;
	1166	+ operating-points-v2 = <&qup_opp_table>;
	1167	+ status = "disabled";
	1168	+ };
	1169	+
289	1170	i2c1: i2c@884000 {
290	1171	compatible = "qcom,geni-i2c";
291		- reg = <0x884000 0x4000>;
	1172	+ reg = <0 0x00884000 0 0x4000>;
292	1173	clock-names = "se";
293	1174	clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
294	1175	pinctrl-names = "default";
..	..	@@ -296,12 +1177,14 @@
296	1177	interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
297	1178	#address-cells = <1>;
298	1179	#size-cells = <0>;
	1180	+ power-domains = <&rpmhpd SDM845_CX>;
	1181	+ operating-points-v2 = <&qup_opp_table>;
299	1182	status = "disabled";
300	1183	};
301	1184
302	1185	spi1: spi@884000 {
303	1186	compatible = "qcom,geni-spi";
304		- reg = <0x884000 0x4000>;
	1187	+ reg = <0 0x00884000 0 0x4000>;
305	1188	clock-names = "se";
306	1189	clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
307	1190	pinctrl-names = "default";
..	..	@@ -312,9 +1195,22 @@
312	1195	status = "disabled";
313	1196	};
314	1197
	1198	+ uart1: serial@884000 {
	1199	+ compatible = "qcom,geni-uart";
	1200	+ reg = <0 0x00884000 0 0x4000>;
	1201	+ clock-names = "se";
	1202	+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
	1203	+ pinctrl-names = "default";
	1204	+ pinctrl-0 = <&qup_uart1_default>;
	1205	+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
	1206	+ power-domains = <&rpmhpd SDM845_CX>;
	1207	+ operating-points-v2 = <&qup_opp_table>;
	1208	+ status = "disabled";
	1209	+ };
	1210	+
315	1211	i2c2: i2c@888000 {
316	1212	compatible = "qcom,geni-i2c";
317		- reg = <0x888000 0x4000>;
	1213	+ reg = <0 0x00888000 0 0x4000>;
318	1214	clock-names = "se";
319	1215	clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
320	1216	pinctrl-names = "default";
..	..	@@ -322,12 +1218,14 @@
322	1218	interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
323	1219	#address-cells = <1>;
324	1220	#size-cells = <0>;
	1221	+ power-domains = <&rpmhpd SDM845_CX>;
	1222	+ operating-points-v2 = <&qup_opp_table>;
325	1223	status = "disabled";
326	1224	};
327	1225
328	1226	spi2: spi@888000 {
329	1227	compatible = "qcom,geni-spi";
330		- reg = <0x888000 0x4000>;
	1228	+ reg = <0 0x00888000 0 0x4000>;
331	1229	clock-names = "se";
332	1230	clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
333	1231	pinctrl-names = "default";
..	..	@@ -338,9 +1236,22 @@
338	1236	status = "disabled";
339	1237	};
340	1238
	1239	+ uart2: serial@888000 {
	1240	+ compatible = "qcom,geni-uart";
	1241	+ reg = <0 0x00888000 0 0x4000>;
	1242	+ clock-names = "se";
	1243	+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
	1244	+ pinctrl-names = "default";
	1245	+ pinctrl-0 = <&qup_uart2_default>;
	1246	+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
	1247	+ power-domains = <&rpmhpd SDM845_CX>;
	1248	+ operating-points-v2 = <&qup_opp_table>;
	1249	+ status = "disabled";
	1250	+ };
	1251	+
341	1252	i2c3: i2c@88c000 {
342	1253	compatible = "qcom,geni-i2c";
343		- reg = <0x88c000 0x4000>;
	1254	+ reg = <0 0x0088c000 0 0x4000>;
344	1255	clock-names = "se";
345	1256	clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
346	1257	pinctrl-names = "default";
..	..	@@ -348,12 +1259,14 @@
348	1259	interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
349	1260	#address-cells = <1>;
350	1261	#size-cells = <0>;
	1262	+ power-domains = <&rpmhpd SDM845_CX>;
	1263	+ operating-points-v2 = <&qup_opp_table>;
351	1264	status = "disabled";
352	1265	};
353	1266
354	1267	spi3: spi@88c000 {
355	1268	compatible = "qcom,geni-spi";
356		- reg = <0x88c000 0x4000>;
	1269	+ reg = <0 0x0088c000 0 0x4000>;
357	1270	clock-names = "se";
358	1271	clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
359	1272	pinctrl-names = "default";
..	..	@@ -364,9 +1277,22 @@
364	1277	status = "disabled";
365	1278	};
366	1279
	1280	+ uart3: serial@88c000 {
	1281	+ compatible = "qcom,geni-uart";
	1282	+ reg = <0 0x0088c000 0 0x4000>;
	1283	+ clock-names = "se";
	1284	+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
	1285	+ pinctrl-names = "default";
	1286	+ pinctrl-0 = <&qup_uart3_default>;
	1287	+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
	1288	+ power-domains = <&rpmhpd SDM845_CX>;
	1289	+ operating-points-v2 = <&qup_opp_table>;
	1290	+ status = "disabled";
	1291	+ };
	1292	+
367	1293	i2c4: i2c@890000 {
368	1294	compatible = "qcom,geni-i2c";
369		- reg = <0x890000 0x4000>;
	1295	+ reg = <0 0x00890000 0 0x4000>;
370	1296	clock-names = "se";
371	1297	clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
372	1298	pinctrl-names = "default";
..	..	@@ -374,12 +1300,14 @@
374	1300	interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
375	1301	#address-cells = <1>;
376	1302	#size-cells = <0>;
	1303	+ power-domains = <&rpmhpd SDM845_CX>;
	1304	+ operating-points-v2 = <&qup_opp_table>;
377	1305	status = "disabled";
378	1306	};
379	1307
380	1308	spi4: spi@890000 {
381	1309	compatible = "qcom,geni-spi";
382		- reg = <0x890000 0x4000>;
	1310	+ reg = <0 0x00890000 0 0x4000>;
383	1311	clock-names = "se";
384	1312	clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
385	1313	pinctrl-names = "default";
..	..	@@ -390,9 +1318,22 @@
390	1318	status = "disabled";
391	1319	};
392	1320
	1321	+ uart4: serial@890000 {
	1322	+ compatible = "qcom,geni-uart";
	1323	+ reg = <0 0x00890000 0 0x4000>;
	1324	+ clock-names = "se";
	1325	+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
	1326	+ pinctrl-names = "default";
	1327	+ pinctrl-0 = <&qup_uart4_default>;
	1328	+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
	1329	+ power-domains = <&rpmhpd SDM845_CX>;
	1330	+ operating-points-v2 = <&qup_opp_table>;
	1331	+ status = "disabled";
	1332	+ };
	1333	+
393	1334	i2c5: i2c@894000 {
394	1335	compatible = "qcom,geni-i2c";
395		- reg = <0x894000 0x4000>;
	1336	+ reg = <0 0x00894000 0 0x4000>;
396	1337	clock-names = "se";
397	1338	clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
398	1339	pinctrl-names = "default";
..	..	@@ -400,12 +1341,14 @@
400	1341	interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
401	1342	#address-cells = <1>;
402	1343	#size-cells = <0>;
	1344	+ power-domains = <&rpmhpd SDM845_CX>;
	1345	+ operating-points-v2 = <&qup_opp_table>;
403	1346	status = "disabled";
404	1347	};
405	1348
406	1349	spi5: spi@894000 {
407	1350	compatible = "qcom,geni-spi";
408		- reg = <0x894000 0x4000>;
	1351	+ reg = <0 0x00894000 0 0x4000>;
409	1352	clock-names = "se";
410	1353	clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
411	1354	pinctrl-names = "default";
..	..	@@ -416,9 +1359,22 @@
416	1359	status = "disabled";
417	1360	};
418	1361
	1362	+ uart5: serial@894000 {
	1363	+ compatible = "qcom,geni-uart";
	1364	+ reg = <0 0x00894000 0 0x4000>;
	1365	+ clock-names = "se";
	1366	+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
	1367	+ pinctrl-names = "default";
	1368	+ pinctrl-0 = <&qup_uart5_default>;
	1369	+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
	1370	+ power-domains = <&rpmhpd SDM845_CX>;
	1371	+ operating-points-v2 = <&qup_opp_table>;
	1372	+ status = "disabled";
	1373	+ };
	1374	+
419	1375	i2c6: i2c@898000 {
420	1376	compatible = "qcom,geni-i2c";
421		- reg = <0x898000 0x4000>;
	1377	+ reg = <0 0x00898000 0 0x4000>;
422	1378	clock-names = "se";
423	1379	clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
424	1380	pinctrl-names = "default";
..	..	@@ -426,12 +1382,14 @@
426	1382	interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
427	1383	#address-cells = <1>;
428	1384	#size-cells = <0>;
	1385	+ power-domains = <&rpmhpd SDM845_CX>;
	1386	+ operating-points-v2 = <&qup_opp_table>;
429	1387	status = "disabled";
430	1388	};
431	1389
432	1390	spi6: spi@898000 {
433	1391	compatible = "qcom,geni-spi";
434		- reg = <0x898000 0x4000>;
	1392	+ reg = <0 0x00898000 0 0x4000>;
435	1393	clock-names = "se";
436	1394	clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
437	1395	pinctrl-names = "default";
..	..	@@ -442,9 +1400,22 @@
442	1400	status = "disabled";
443	1401	};
444	1402
	1403	+ uart6: serial@898000 {
	1404	+ compatible = "qcom,geni-uart";
	1405	+ reg = <0 0x00898000 0 0x4000>;
	1406	+ clock-names = "se";
	1407	+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
	1408	+ pinctrl-names = "default";
	1409	+ pinctrl-0 = <&qup_uart6_default>;
	1410	+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
	1411	+ power-domains = <&rpmhpd SDM845_CX>;
	1412	+ operating-points-v2 = <&qup_opp_table>;
	1413	+ status = "disabled";
	1414	+ };
	1415	+
445	1416	i2c7: i2c@89c000 {
446	1417	compatible = "qcom,geni-i2c";
447		- reg = <0x89c000 0x4000>;
	1418	+ reg = <0 0x0089c000 0 0x4000>;
448	1419	clock-names = "se";
449	1420	clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
450	1421	pinctrl-names = "default";
..	..	@@ -452,12 +1423,14 @@
452	1423	interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
453	1424	#address-cells = <1>;
454	1425	#size-cells = <0>;
	1426	+ power-domains = <&rpmhpd SDM845_CX>;
	1427	+ operating-points-v2 = <&qup_opp_table>;
455	1428	status = "disabled";
456	1429	};
457	1430
458	1431	spi7: spi@89c000 {
459	1432	compatible = "qcom,geni-spi";
460		- reg = <0x89c000 0x4000>;
	1433	+ reg = <0 0x0089c000 0 0x4000>;
461	1434	clock-names = "se";
462	1435	clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
463	1436	pinctrl-names = "default";
..	..	@@ -467,22 +1440,35 @@
467	1440	#size-cells = <0>;
468	1441	status = "disabled";
469	1442	};
	1443	+
	1444	+ uart7: serial@89c000 {
	1445	+ compatible = "qcom,geni-uart";
	1446	+ reg = <0 0x0089c000 0 0x4000>;
	1447	+ clock-names = "se";
	1448	+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
	1449	+ pinctrl-names = "default";
	1450	+ pinctrl-0 = <&qup_uart7_default>;
	1451	+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
	1452	+ power-domains = <&rpmhpd SDM845_CX>;
	1453	+ operating-points-v2 = <&qup_opp_table>;
	1454	+ status = "disabled";
	1455	+ };
470	1456	};
471	1457
472	1458	qupv3_id_1: geniqup@ac0000 {
473	1459	compatible = "qcom,geni-se-qup";
474		- reg = <0xac0000 0x6000>;
	1460	+ reg = <0 0x00ac0000 0 0x6000>;
475	1461	clock-names = "m-ahb", "s-ahb";
476	1462	clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
477	1463	<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
478		- #address-cells = <1>;
479		- #size-cells = <1>;
	1464	+ #address-cells = <2>;
	1465	+ #size-cells = <2>;
480	1466	ranges;
481	1467	status = "disabled";
482	1468
483	1469	i2c8: i2c@a80000 {
484	1470	compatible = "qcom,geni-i2c";
485		- reg = <0xa80000 0x4000>;
	1471	+ reg = <0 0x00a80000 0 0x4000>;
486	1472	clock-names = "se";
487	1473	clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
488	1474	pinctrl-names = "default";
..	..	@@ -490,12 +1476,14 @@
490	1476	interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
491	1477	#address-cells = <1>;
492	1478	#size-cells = <0>;
	1479	+ power-domains = <&rpmhpd SDM845_CX>;
	1480	+ operating-points-v2 = <&qup_opp_table>;
493	1481	status = "disabled";
494	1482	};
495	1483
496	1484	spi8: spi@a80000 {
497	1485	compatible = "qcom,geni-spi";
498		- reg = <0xa80000 0x4000>;
	1486	+ reg = <0 0x00a80000 0 0x4000>;
499	1487	clock-names = "se";
500	1488	clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
501	1489	pinctrl-names = "default";
..	..	@@ -506,9 +1494,22 @@
506	1494	status = "disabled";
507	1495	};
508	1496
	1497	+ uart8: serial@a80000 {
	1498	+ compatible = "qcom,geni-uart";
	1499	+ reg = <0 0x00a80000 0 0x4000>;
	1500	+ clock-names = "se";
	1501	+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
	1502	+ pinctrl-names = "default";
	1503	+ pinctrl-0 = <&qup_uart8_default>;
	1504	+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
	1505	+ power-domains = <&rpmhpd SDM845_CX>;
	1506	+ operating-points-v2 = <&qup_opp_table>;
	1507	+ status = "disabled";
	1508	+ };
	1509	+
509	1510	i2c9: i2c@a84000 {
510	1511	compatible = "qcom,geni-i2c";
511		- reg = <0xa84000 0x4000>;
	1512	+ reg = <0 0x00a84000 0 0x4000>;
512	1513	clock-names = "se";
513	1514	clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
514	1515	pinctrl-names = "default";
..	..	@@ -516,12 +1517,14 @@
516	1517	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
517	1518	#address-cells = <1>;
518	1519	#size-cells = <0>;
	1520	+ power-domains = <&rpmhpd SDM845_CX>;
	1521	+ operating-points-v2 = <&qup_opp_table>;
519	1522	status = "disabled";
520	1523	};
521	1524
522	1525	spi9: spi@a84000 {
523	1526	compatible = "qcom,geni-spi";
524		- reg = <0xa84000 0x4000>;
	1527	+ reg = <0 0x00a84000 0 0x4000>;
525	1528	clock-names = "se";
526	1529	clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
527	1530	pinctrl-names = "default";
..	..	@@ -534,18 +1537,20 @@
534	1537
535	1538	uart9: serial@a84000 {
536	1539	compatible = "qcom,geni-debug-uart";
537		- reg = <0xa84000 0x4000>;
	1540	+ reg = <0 0x00a84000 0 0x4000>;
538	1541	clock-names = "se";
539	1542	clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
540	1543	pinctrl-names = "default";
541	1544	pinctrl-0 = <&qup_uart9_default>;
542	1545	interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
	1546	+ power-domains = <&rpmhpd SDM845_CX>;
	1547	+ operating-points-v2 = <&qup_opp_table>;
543	1548	status = "disabled";
544	1549	};
545	1550
546	1551	i2c10: i2c@a88000 {
547	1552	compatible = "qcom,geni-i2c";
548		- reg = <0xa88000 0x4000>;
	1553	+ reg = <0 0x00a88000 0 0x4000>;
549	1554	clock-names = "se";
550	1555	clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
551	1556	pinctrl-names = "default";
..	..	@@ -553,12 +1558,14 @@
553	1558	interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
554	1559	#address-cells = <1>;
555	1560	#size-cells = <0>;
	1561	+ power-domains = <&rpmhpd SDM845_CX>;
	1562	+ operating-points-v2 = <&qup_opp_table>;
556	1563	status = "disabled";
557	1564	};
558	1565
559	1566	spi10: spi@a88000 {
560	1567	compatible = "qcom,geni-spi";
561		- reg = <0xa88000 0x4000>;
	1568	+ reg = <0 0x00a88000 0 0x4000>;
562	1569	clock-names = "se";
563	1570	clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
564	1571	pinctrl-names = "default";
..	..	@@ -569,9 +1576,22 @@
569	1576	status = "disabled";
570	1577	};
571	1578
	1579	+ uart10: serial@a88000 {
	1580	+ compatible = "qcom,geni-uart";
	1581	+ reg = <0 0x00a88000 0 0x4000>;
	1582	+ clock-names = "se";
	1583	+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
	1584	+ pinctrl-names = "default";
	1585	+ pinctrl-0 = <&qup_uart10_default>;
	1586	+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
	1587	+ power-domains = <&rpmhpd SDM845_CX>;
	1588	+ operating-points-v2 = <&qup_opp_table>;
	1589	+ status = "disabled";
	1590	+ };
	1591	+
572	1592	i2c11: i2c@a8c000 {
573	1593	compatible = "qcom,geni-i2c";
574		- reg = <0xa8c000 0x4000>;
	1594	+ reg = <0 0x00a8c000 0 0x4000>;
575	1595	clock-names = "se";
576	1596	clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
577	1597	pinctrl-names = "default";
..	..	@@ -579,12 +1599,14 @@
579	1599	interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
580	1600	#address-cells = <1>;
581	1601	#size-cells = <0>;
	1602	+ power-domains = <&rpmhpd SDM845_CX>;
	1603	+ operating-points-v2 = <&qup_opp_table>;
582	1604	status = "disabled";
583	1605	};
584	1606
585	1607	spi11: spi@a8c000 {
586	1608	compatible = "qcom,geni-spi";
587		- reg = <0xa8c000 0x4000>;
	1609	+ reg = <0 0x00a8c000 0 0x4000>;
588	1610	clock-names = "se";
589	1611	clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
590	1612	pinctrl-names = "default";
..	..	@@ -595,9 +1617,22 @@
595	1617	status = "disabled";
596	1618	};
597	1619
	1620	+ uart11: serial@a8c000 {
	1621	+ compatible = "qcom,geni-uart";
	1622	+ reg = <0 0x00a8c000 0 0x4000>;
	1623	+ clock-names = "se";
	1624	+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
	1625	+ pinctrl-names = "default";
	1626	+ pinctrl-0 = <&qup_uart11_default>;
	1627	+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
	1628	+ power-domains = <&rpmhpd SDM845_CX>;
	1629	+ operating-points-v2 = <&qup_opp_table>;
	1630	+ status = "disabled";
	1631	+ };
	1632	+
598	1633	i2c12: i2c@a90000 {
599	1634	compatible = "qcom,geni-i2c";
600		- reg = <0xa90000 0x4000>;
	1635	+ reg = <0 0x00a90000 0 0x4000>;
601	1636	clock-names = "se";
602	1637	clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
603	1638	pinctrl-names = "default";
..	..	@@ -605,12 +1640,14 @@
605	1640	interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
606	1641	#address-cells = <1>;
607	1642	#size-cells = <0>;
	1643	+ power-domains = <&rpmhpd SDM845_CX>;
	1644	+ operating-points-v2 = <&qup_opp_table>;
608	1645	status = "disabled";
609	1646	};
610	1647
611	1648	spi12: spi@a90000 {
612	1649	compatible = "qcom,geni-spi";
613		- reg = <0xa90000 0x4000>;
	1650	+ reg = <0 0x00a90000 0 0x4000>;
614	1651	clock-names = "se";
615	1652	clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
616	1653	pinctrl-names = "default";
..	..	@@ -621,9 +1658,22 @@
621	1658	status = "disabled";
622	1659	};
623	1660
	1661	+ uart12: serial@a90000 {
	1662	+ compatible = "qcom,geni-uart";
	1663	+ reg = <0 0x00a90000 0 0x4000>;
	1664	+ clock-names = "se";
	1665	+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
	1666	+ pinctrl-names = "default";
	1667	+ pinctrl-0 = <&qup_uart12_default>;
	1668	+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
	1669	+ power-domains = <&rpmhpd SDM845_CX>;
	1670	+ operating-points-v2 = <&qup_opp_table>;
	1671	+ status = "disabled";
	1672	+ };
	1673	+
624	1674	i2c13: i2c@a94000 {
625	1675	compatible = "qcom,geni-i2c";
626		- reg = <0xa94000 0x4000>;
	1676	+ reg = <0 0x00a94000 0 0x4000>;
627	1677	clock-names = "se";
628	1678	clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
629	1679	pinctrl-names = "default";
..	..	@@ -631,12 +1681,14 @@
631	1681	interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
632	1682	#address-cells = <1>;
633	1683	#size-cells = <0>;
	1684	+ power-domains = <&rpmhpd SDM845_CX>;
	1685	+ operating-points-v2 = <&qup_opp_table>;
634	1686	status = "disabled";
635	1687	};
636	1688
637	1689	spi13: spi@a94000 {
638	1690	compatible = "qcom,geni-spi";
639		- reg = <0xa94000 0x4000>;
	1691	+ reg = <0 0x00a94000 0 0x4000>;
640	1692	clock-names = "se";
641	1693	clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
642	1694	pinctrl-names = "default";
..	..	@@ -647,9 +1699,22 @@
647	1699	status = "disabled";
648	1700	};
649	1701
	1702	+ uart13: serial@a94000 {
	1703	+ compatible = "qcom,geni-uart";
	1704	+ reg = <0 0x00a94000 0 0x4000>;
	1705	+ clock-names = "se";
	1706	+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
	1707	+ pinctrl-names = "default";
	1708	+ pinctrl-0 = <&qup_uart13_default>;
	1709	+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
	1710	+ power-domains = <&rpmhpd SDM845_CX>;
	1711	+ operating-points-v2 = <&qup_opp_table>;
	1712	+ status = "disabled";
	1713	+ };
	1714	+
650	1715	i2c14: i2c@a98000 {
651	1716	compatible = "qcom,geni-i2c";
652		- reg = <0xa98000 0x4000>;
	1717	+ reg = <0 0x00a98000 0 0x4000>;
653	1718	clock-names = "se";
654	1719	clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
655	1720	pinctrl-names = "default";
..	..	@@ -657,12 +1722,14 @@
657	1722	interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
658	1723	#address-cells = <1>;
659	1724	#size-cells = <0>;
	1725	+ power-domains = <&rpmhpd SDM845_CX>;
	1726	+ operating-points-v2 = <&qup_opp_table>;
660	1727	status = "disabled";
661	1728	};
662	1729
663	1730	spi14: spi@a98000 {
664	1731	compatible = "qcom,geni-spi";
665		- reg = <0xa98000 0x4000>;
	1732	+ reg = <0 0x00a98000 0 0x4000>;
666	1733	clock-names = "se";
667	1734	clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
668	1735	pinctrl-names = "default";
..	..	@@ -673,9 +1740,22 @@
673	1740	status = "disabled";
674	1741	};
675	1742
	1743	+ uart14: serial@a98000 {
	1744	+ compatible = "qcom,geni-uart";
	1745	+ reg = <0 0x00a98000 0 0x4000>;
	1746	+ clock-names = "se";
	1747	+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
	1748	+ pinctrl-names = "default";
	1749	+ pinctrl-0 = <&qup_uart14_default>;
	1750	+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	1751	+ power-domains = <&rpmhpd SDM845_CX>;
	1752	+ operating-points-v2 = <&qup_opp_table>;
	1753	+ status = "disabled";
	1754	+ };
	1755	+
676	1756	i2c15: i2c@a9c000 {
677	1757	compatible = "qcom,geni-i2c";
678		- reg = <0xa9c000 0x4000>;
	1758	+ reg = <0 0x00a9c000 0 0x4000>;
679	1759	clock-names = "se";
680	1760	clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
681	1761	pinctrl-names = "default";
..	..	@@ -683,12 +1763,14 @@
683	1763	interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
684	1764	#address-cells = <1>;
685	1765	#size-cells = <0>;
	1766	+ power-domains = <&rpmhpd SDM845_CX>;
	1767	+ operating-points-v2 = <&qup_opp_table>;
686	1768	status = "disabled";
687	1769	};
688	1770
689	1771	spi15: spi@a9c000 {
690	1772	compatible = "qcom,geni-spi";
691		- reg = <0xa9c000 0x4000>;
	1773	+ reg = <0 0x00a9c000 0 0x4000>;
692	1774	clock-names = "se";
693	1775	clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
694	1776	pinctrl-names = "default";
..	..	@@ -698,21 +1780,492 @@
698	1780	#size-cells = <0>;
699	1781	status = "disabled";
700	1782	};
	1783	+
	1784	+ uart15: serial@a9c000 {
	1785	+ compatible = "qcom,geni-uart";
	1786	+ reg = <0 0x00a9c000 0 0x4000>;
	1787	+ clock-names = "se";
	1788	+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
	1789	+ pinctrl-names = "default";
	1790	+ pinctrl-0 = <&qup_uart15_default>;
	1791	+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	1792	+ power-domains = <&rpmhpd SDM845_CX>;
	1793	+ operating-points-v2 = <&qup_opp_table>;
	1794	+ status = "disabled";
	1795	+ };
	1796	+ };
	1797	+
	1798	+ system-cache-controller@1100000 {
	1799	+ compatible = "qcom,sdm845-llcc";
	1800	+ reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
	1801	+ reg-names = "llcc_base", "llcc_broadcast_base";
	1802	+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
	1803	+ };
	1804	+
	1805	+ pcie0: pci@1c00000 {
	1806	+ compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
	1807	+ reg = <0 0x01c00000 0 0x2000>,
	1808	+ <0 0x60000000 0 0xf1d>,
	1809	+ <0 0x60000f20 0 0xa8>,
	1810	+ <0 0x60100000 0 0x100000>;
	1811	+ reg-names = "parf", "dbi", "elbi", "config";
	1812	+ device_type = "pci";
	1813	+ linux,pci-domain = <0>;
	1814	+ bus-range = <0x00 0xff>;
	1815	+ num-lanes = <1>;
	1816	+
	1817	+ #address-cells = <3>;
	1818	+ #size-cells = <2>;
	1819	+
	1820	+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
	1821	+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
	1822	+
	1823	+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
	1824	+ interrupt-names = "msi";
	1825	+ #interrupt-cells = <1>;
	1826	+ interrupt-map-mask = <0 0 0 0x7>;
	1827	+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	1828	+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	1829	+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	1830	+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
	1831	+
	1832	+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
	1833	+ <&gcc GCC_PCIE_0_AUX_CLK>,
	1834	+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
	1835	+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
	1836	+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
	1837	+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
	1838	+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
	1839	+ clock-names = "pipe",
	1840	+ "aux",
	1841	+ "cfg",
	1842	+ "bus_master",
	1843	+ "bus_slave",
	1844	+ "slave_q2a",
	1845	+ "tbu";
	1846	+
	1847	+ iommus = <&apps_smmu 0x1c10 0xf>;
	1848	+ iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
	1849	+ <0x100 &apps_smmu 0x1c11 0x1>,
	1850	+ <0x200 &apps_smmu 0x1c12 0x1>,
	1851	+ <0x300 &apps_smmu 0x1c13 0x1>,
	1852	+ <0x400 &apps_smmu 0x1c14 0x1>,
	1853	+ <0x500 &apps_smmu 0x1c15 0x1>,
	1854	+ <0x600 &apps_smmu 0x1c16 0x1>,
	1855	+ <0x700 &apps_smmu 0x1c17 0x1>,
	1856	+ <0x800 &apps_smmu 0x1c18 0x1>,
	1857	+ <0x900 &apps_smmu 0x1c19 0x1>,
	1858	+ <0xa00 &apps_smmu 0x1c1a 0x1>,
	1859	+ <0xb00 &apps_smmu 0x1c1b 0x1>,
	1860	+ <0xc00 &apps_smmu 0x1c1c 0x1>,
	1861	+ <0xd00 &apps_smmu 0x1c1d 0x1>,
	1862	+ <0xe00 &apps_smmu 0x1c1e 0x1>,
	1863	+ <0xf00 &apps_smmu 0x1c1f 0x1>;
	1864	+
	1865	+ resets = <&gcc GCC_PCIE_0_BCR>;
	1866	+ reset-names = "pci";
	1867	+
	1868	+ power-domains = <&gcc PCIE_0_GDSC>;
	1869	+
	1870	+ phys = <&pcie0_lane>;
	1871	+ phy-names = "pciephy";
	1872	+
	1873	+ status = "disabled";
	1874	+ };
	1875	+
	1876	+ pcie0_phy: phy@1c06000 {
	1877	+ compatible = "qcom,sdm845-qmp-pcie-phy";
	1878	+ reg = <0 0x01c06000 0 0x18c>;
	1879	+ #address-cells = <2>;
	1880	+ #size-cells = <2>;
	1881	+ ranges;
	1882	+ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
	1883	+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
	1884	+ <&gcc GCC_PCIE_0_CLKREF_CLK>,
	1885	+ <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
	1886	+ clock-names = "aux", "cfg_ahb", "ref", "refgen";
	1887	+
	1888	+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
	1889	+ reset-names = "phy";
	1890	+
	1891	+ assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
	1892	+ assigned-clock-rates = <100000000>;
	1893	+
	1894	+ status = "disabled";
	1895	+
	1896	+ pcie0_lane: lanes@1c06200 {
	1897	+ reg = <0 0x01c06200 0 0x128>,
	1898	+ <0 0x01c06400 0 0x1fc>,
	1899	+ <0 0x01c06800 0 0x218>,
	1900	+ <0 0x01c06600 0 0x70>;
	1901	+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
	1902	+ clock-names = "pipe0";
	1903	+
	1904	+ #phy-cells = <0>;
	1905	+ clock-output-names = "pcie_0_pipe_clk";
	1906	+ };
	1907	+ };
	1908	+
	1909	+ pcie1: pci@1c08000 {
	1910	+ compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
	1911	+ reg = <0 0x01c08000 0 0x2000>,
	1912	+ <0 0x40000000 0 0xf1d>,
	1913	+ <0 0x40000f20 0 0xa8>,
	1914	+ <0 0x40100000 0 0x100000>;
	1915	+ reg-names = "parf", "dbi", "elbi", "config";
	1916	+ device_type = "pci";
	1917	+ linux,pci-domain = <1>;
	1918	+ bus-range = <0x00 0xff>;
	1919	+ num-lanes = <1>;
	1920	+
	1921	+ #address-cells = <3>;
	1922	+ #size-cells = <2>;
	1923	+
	1924	+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
	1925	+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
	1926	+
	1927	+ interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
	1928	+ interrupt-names = "msi";
	1929	+ #interrupt-cells = <1>;
	1930	+ interrupt-map-mask = <0 0 0 0x7>;
	1931	+ interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	1932	+ <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	1933	+ <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	1934	+ <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
	1935	+
	1936	+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
	1937	+ <&gcc GCC_PCIE_1_AUX_CLK>,
	1938	+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
	1939	+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
	1940	+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
	1941	+ <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
	1942	+ <&gcc GCC_PCIE_1_CLKREF_CLK>,
	1943	+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
	1944	+ clock-names = "pipe",
	1945	+ "aux",
	1946	+ "cfg",
	1947	+ "bus_master",
	1948	+ "bus_slave",
	1949	+ "slave_q2a",
	1950	+ "ref",
	1951	+ "tbu";
	1952	+
	1953	+ assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
	1954	+ assigned-clock-rates = <19200000>;
	1955	+
	1956	+ iommus = <&apps_smmu 0x1c00 0xf>;
	1957	+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
	1958	+ <0x100 &apps_smmu 0x1c01 0x1>,
	1959	+ <0x200 &apps_smmu 0x1c02 0x1>,
	1960	+ <0x300 &apps_smmu 0x1c03 0x1>,
	1961	+ <0x400 &apps_smmu 0x1c04 0x1>,
	1962	+ <0x500 &apps_smmu 0x1c05 0x1>,
	1963	+ <0x600 &apps_smmu 0x1c06 0x1>,
	1964	+ <0x700 &apps_smmu 0x1c07 0x1>,
	1965	+ <0x800 &apps_smmu 0x1c08 0x1>,
	1966	+ <0x900 &apps_smmu 0x1c09 0x1>,
	1967	+ <0xa00 &apps_smmu 0x1c0a 0x1>,
	1968	+ <0xb00 &apps_smmu 0x1c0b 0x1>,
	1969	+ <0xc00 &apps_smmu 0x1c0c 0x1>,
	1970	+ <0xd00 &apps_smmu 0x1c0d 0x1>,
	1971	+ <0xe00 &apps_smmu 0x1c0e 0x1>,
	1972	+ <0xf00 &apps_smmu 0x1c0f 0x1>;
	1973	+
	1974	+ resets = <&gcc GCC_PCIE_1_BCR>;
	1975	+ reset-names = "pci";
	1976	+
	1977	+ power-domains = <&gcc PCIE_1_GDSC>;
	1978	+
	1979	+ phys = <&pcie1_lane>;
	1980	+ phy-names = "pciephy";
	1981	+
	1982	+ status = "disabled";
	1983	+ };
	1984	+
	1985	+ pcie1_phy: phy@1c0a000 {
	1986	+ compatible = "qcom,sdm845-qhp-pcie-phy";
	1987	+ reg = <0 0x01c0a000 0 0x800>;
	1988	+ #address-cells = <2>;
	1989	+ #size-cells = <2>;
	1990	+ ranges;
	1991	+ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
	1992	+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
	1993	+ <&gcc GCC_PCIE_1_CLKREF_CLK>,
	1994	+ <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
	1995	+ clock-names = "aux", "cfg_ahb", "ref", "refgen";
	1996	+
	1997	+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
	1998	+ reset-names = "phy";
	1999	+
	2000	+ assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
	2001	+ assigned-clock-rates = <100000000>;
	2002	+
	2003	+ status = "disabled";
	2004	+
	2005	+ pcie1_lane: lanes@1c06200 {
	2006	+ reg = <0 0x01c0a800 0 0x800>,
	2007	+ <0 0x01c0a800 0 0x800>,
	2008	+ <0 0x01c0b800 0 0x400>;
	2009	+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
	2010	+ clock-names = "pipe0";
	2011	+
	2012	+ #phy-cells = <0>;
	2013	+ clock-output-names = "pcie_1_pipe_clk";
	2014	+ };
	2015	+ };
	2016	+
	2017	+ mem_noc: interconnect@1380000 {
	2018	+ compatible = "qcom,sdm845-mem-noc";
	2019	+ reg = <0 0x01380000 0 0x27200>;
	2020	+ #interconnect-cells = <2>;
	2021	+ qcom,bcm-voters = <&apps_bcm_voter>;
	2022	+ };
	2023	+
	2024	+ dc_noc: interconnect@14e0000 {
	2025	+ compatible = "qcom,sdm845-dc-noc";
	2026	+ reg = <0 0x014e0000 0 0x400>;
	2027	+ #interconnect-cells = <2>;
	2028	+ qcom,bcm-voters = <&apps_bcm_voter>;
	2029	+ };
	2030	+
	2031	+ config_noc: interconnect@1500000 {
	2032	+ compatible = "qcom,sdm845-config-noc";
	2033	+ reg = <0 0x01500000 0 0x5080>;
	2034	+ #interconnect-cells = <2>;
	2035	+ qcom,bcm-voters = <&apps_bcm_voter>;
	2036	+ };
	2037	+
	2038	+ system_noc: interconnect@1620000 {
	2039	+ compatible = "qcom,sdm845-system-noc";
	2040	+ reg = <0 0x01620000 0 0x18080>;
	2041	+ #interconnect-cells = <2>;
	2042	+ qcom,bcm-voters = <&apps_bcm_voter>;
	2043	+ };
	2044	+
	2045	+ aggre1_noc: interconnect@16e0000 {
	2046	+ compatible = "qcom,sdm845-aggre1-noc";
	2047	+ reg = <0 0x016e0000 0 0x15080>;
	2048	+ #interconnect-cells = <2>;
	2049	+ qcom,bcm-voters = <&apps_bcm_voter>;
	2050	+ };
	2051	+
	2052	+ aggre2_noc: interconnect@1700000 {
	2053	+ compatible = "qcom,sdm845-aggre2-noc";
	2054	+ reg = <0 0x01700000 0 0x1f300>;
	2055	+ #interconnect-cells = <2>;
	2056	+ qcom,bcm-voters = <&apps_bcm_voter>;
	2057	+ };
	2058	+
	2059	+ mmss_noc: interconnect@1740000 {
	2060	+ compatible = "qcom,sdm845-mmss-noc";
	2061	+ reg = <0 0x01740000 0 0x1c100>;
	2062	+ #interconnect-cells = <2>;
	2063	+ qcom,bcm-voters = <&apps_bcm_voter>;
	2064	+ };
	2065	+
	2066	+ ufs_mem_hc: ufshc@1d84000 {
	2067	+ compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
	2068	+ "jedec,ufs-2.0";
	2069	+ reg = <0 0x01d84000 0 0x2500>,
	2070	+ <0 0x01d90000 0 0x8000>;
	2071	+ reg-names = "std", "ice";
	2072	+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
	2073	+ phys = <&ufs_mem_phy_lanes>;
	2074	+ phy-names = "ufsphy";
	2075	+ lanes-per-direction = <2>;
	2076	+ power-domains = <&gcc UFS_PHY_GDSC>;
	2077	+ #reset-cells = <1>;
	2078	+ resets = <&gcc GCC_UFS_PHY_BCR>;
	2079	+ reset-names = "rst";
	2080	+
	2081	+ iommus = <&apps_smmu 0x100 0xf>;
	2082	+
	2083	+ clock-names =
	2084	+ "core_clk",
	2085	+ "bus_aggr_clk",
	2086	+ "iface_clk",
	2087	+ "core_clk_unipro",
	2088	+ "ref_clk",
	2089	+ "tx_lane0_sync_clk",
	2090	+ "rx_lane0_sync_clk",
	2091	+ "rx_lane1_sync_clk",
	2092	+ "ice_core_clk";
	2093	+ clocks =
	2094	+ <&gcc GCC_UFS_PHY_AXI_CLK>,
	2095	+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
	2096	+ <&gcc GCC_UFS_PHY_AHB_CLK>,
	2097	+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
	2098	+ <&rpmhcc RPMH_CXO_CLK>,
	2099	+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
	2100	+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
	2101	+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
	2102	+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
	2103	+ freq-table-hz =
	2104	+ <50000000 200000000>,
	2105	+ <0 0>,
	2106	+ <0 0>,
	2107	+ <37500000 150000000>,
	2108	+ <0 0>,
	2109	+ <0 0>,
	2110	+ <0 0>,
	2111	+ <0 0>,
	2112	+ <75000000 300000000>;
	2113	+
	2114	+ status = "disabled";
	2115	+ };
	2116	+
	2117	+ ufs_mem_phy: phy@1d87000 {
	2118	+ compatible = "qcom,sdm845-qmp-ufs-phy";
	2119	+ reg = <0 0x01d87000 0 0x18c>;
	2120	+ #address-cells = <2>;
	2121	+ #size-cells = <2>;
	2122	+ ranges;
	2123	+ clock-names = "ref",
	2124	+ "ref_aux";
	2125	+ clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
	2126	+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
	2127	+
	2128	+ resets = <&ufs_mem_hc 0>;
	2129	+ reset-names = "ufsphy";
	2130	+ status = "disabled";
	2131	+
	2132	+ ufs_mem_phy_lanes: lanes@1d87400 {
	2133	+ reg = <0 0x01d87400 0 0x108>,
	2134	+ <0 0x01d87600 0 0x1e0>,
	2135	+ <0 0x01d87c00 0 0x1dc>,
	2136	+ <0 0x01d87800 0 0x108>,
	2137	+ <0 0x01d87a00 0 0x1e0>;
	2138	+ #phy-cells = <0>;
	2139	+ };
	2140	+ };
	2141	+
	2142	+ ipa: ipa@1e40000 {
	2143	+ compatible = "qcom,sdm845-ipa";
	2144	+
	2145	+ iommus = <&apps_smmu 0x720 0x0>,
	2146	+ <&apps_smmu 0x722 0x0>;
	2147	+ reg = <0 0x1e40000 0 0x7000>,
	2148	+ <0 0x1e47000 0 0x2000>,
	2149	+ <0 0x1e04000 0 0x2c000>;
	2150	+ reg-names = "ipa-reg",
	2151	+ "ipa-shared",
	2152	+ "gsi";
	2153	+
	2154	+ interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
	2155	+ <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
	2156	+ <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	2157	+ <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
	2158	+ interrupt-names = "ipa",
	2159	+ "gsi",
	2160	+ "ipa-clock-query",
	2161	+ "ipa-setup-ready";
	2162	+
	2163	+ clocks = <&rpmhcc RPMH_IPA_CLK>;
	2164	+ clock-names = "core";
	2165	+
	2166	+ interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
	2167	+ <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
	2168	+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
	2169	+ interconnect-names = "memory",
	2170	+ "imem",
	2171	+ "config";
	2172	+
	2173	+ qcom,smem-states = <&ipa_smp2p_out 0>,
	2174	+ <&ipa_smp2p_out 1>;
	2175	+ qcom,smem-state-names = "ipa-clock-enabled-valid",
	2176	+ "ipa-clock-enabled";
	2177	+
	2178	+ modem-remoteproc = <&mss_pil>;
	2179	+
	2180	+ status = "disabled";
701	2181	};
702	2182
703	2183	tcsr_mutex_regs: syscon@1f40000 {
704	2184	compatible = "syscon";
705		- reg = <0x1f40000 0x40000>;
	2185	+ reg = <0 0x01f40000 0 0x40000>;
706	2186	};
707	2187
708	2188	tlmm: pinctrl@3400000 {
709	2189	compatible = "qcom,sdm845-pinctrl";
710		- reg = <0x03400000 0xc00000>;
	2190	+ reg = <0 0x03400000 0 0xc00000>;
711	2191	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
712	2192	gpio-controller;
713	2193	#gpio-cells = <2>;
714	2194	interrupt-controller;
715	2195	#interrupt-cells = <2>;
	2196	+ gpio-ranges = <&tlmm 0 0 151>;
	2197	+ wakeup-parent = <&pdc_intc>;
	2198	+
	2199	+ cci0_default: cci0-default {
	2200	+ /* SDA, SCL */
	2201	+ pins = "gpio17", "gpio18";
	2202	+ function = "cci_i2c";
	2203	+
	2204	+ bias-pull-up;
	2205	+ drive-strength = <2>; /* 2 mA */
	2206	+ };
	2207	+
	2208	+ cci0_sleep: cci0-sleep {
	2209	+ /* SDA, SCL */
	2210	+ pins = "gpio17", "gpio18";
	2211	+ function = "cci_i2c";
	2212	+
	2213	+ drive-strength = <2>; /* 2 mA */
	2214	+ bias-pull-down;
	2215	+ };
	2216	+
	2217	+ cci1_default: cci1-default {
	2218	+ /* SDA, SCL */
	2219	+ pins = "gpio19", "gpio20";
	2220	+ function = "cci_i2c";
	2221	+
	2222	+ bias-pull-up;
	2223	+ drive-strength = <2>; /* 2 mA */
	2224	+ };
	2225	+
	2226	+ cci1_sleep: cci1-sleep {
	2227	+ /* SDA, SCL */
	2228	+ pins = "gpio19", "gpio20";
	2229	+ function = "cci_i2c";
	2230	+
	2231	+ drive-strength = <2>; /* 2 mA */
	2232	+ bias-pull-down;
	2233	+ };
	2234	+
	2235	+ qspi_clk: qspi-clk {
	2236	+ pinmux {
	2237	+ pins = "gpio95";
	2238	+ function = "qspi_clk";
	2239	+ };
	2240	+ };
	2241	+
	2242	+ qspi_cs0: qspi-cs0 {
	2243	+ pinmux {
	2244	+ pins = "gpio90";
	2245	+ function = "qspi_cs";
	2246	+ };
	2247	+ };
	2248	+
	2249	+ qspi_cs1: qspi-cs1 {
	2250	+ pinmux {
	2251	+ pins = "gpio89";
	2252	+ function = "qspi_cs";
	2253	+ };
	2254	+ };
	2255	+
	2256	+ qspi_data01: qspi-data01 {
	2257	+ pinmux-data {
	2258	+ pins = "gpio91", "gpio92";
	2259	+ function = "qspi_data";
	2260	+ };
	2261	+ };
	2262	+
	2263	+ qspi_data12: qspi-data12 {
	2264	+ pinmux-data {
	2265	+ pins = "gpio93", "gpio94";
	2266	+ function = "qspi_data";
	2267	+ };
	2268	+ };
716	2269
717	2270	qup_i2c0_default: qup-i2c0-default {
718	2271	pinmux {
..	..	@@ -954,37 +2507,1760 @@
954	2507	};
955	2508	};
956	2509
	2510	+ qup_uart0_default: qup-uart0-default {
	2511	+ pinmux {
	2512	+ pins = "gpio2", "gpio3";
	2513	+ function = "qup0";
	2514	+ };
	2515	+ };
	2516	+
	2517	+ qup_uart1_default: qup-uart1-default {
	2518	+ pinmux {
	2519	+ pins = "gpio19", "gpio20";
	2520	+ function = "qup1";
	2521	+ };
	2522	+ };
	2523	+
	2524	+ qup_uart2_default: qup-uart2-default {
	2525	+ pinmux {
	2526	+ pins = "gpio29", "gpio30";
	2527	+ function = "qup2";
	2528	+ };
	2529	+ };
	2530	+
	2531	+ qup_uart3_default: qup-uart3-default {
	2532	+ pinmux {
	2533	+ pins = "gpio43", "gpio44";
	2534	+ function = "qup3";
	2535	+ };
	2536	+ };
	2537	+
	2538	+ qup_uart4_default: qup-uart4-default {
	2539	+ pinmux {
	2540	+ pins = "gpio91", "gpio92";
	2541	+ function = "qup4";
	2542	+ };
	2543	+ };
	2544	+
	2545	+ qup_uart5_default: qup-uart5-default {
	2546	+ pinmux {
	2547	+ pins = "gpio87", "gpio88";
	2548	+ function = "qup5";
	2549	+ };
	2550	+ };
	2551	+
	2552	+ qup_uart6_default: qup-uart6-default {
	2553	+ pinmux {
	2554	+ pins = "gpio47", "gpio48";
	2555	+ function = "qup6";
	2556	+ };
	2557	+ };
	2558	+
	2559	+ qup_uart7_default: qup-uart7-default {
	2560	+ pinmux {
	2561	+ pins = "gpio95", "gpio96";
	2562	+ function = "qup7";
	2563	+ };
	2564	+ };
	2565	+
	2566	+ qup_uart8_default: qup-uart8-default {
	2567	+ pinmux {
	2568	+ pins = "gpio67", "gpio68";
	2569	+ function = "qup8";
	2570	+ };
	2571	+ };
	2572	+
957	2573	qup_uart9_default: qup-uart9-default {
958	2574	pinmux {
959	2575	pins = "gpio4", "gpio5";
960	2576	function = "qup9";
961	2577	};
962	2578	};
	2579	+
	2580	+ qup_uart10_default: qup-uart10-default {
	2581	+ pinmux {
	2582	+ pins = "gpio53", "gpio54";
	2583	+ function = "qup10";
	2584	+ };
	2585	+ };
	2586	+
	2587	+ qup_uart11_default: qup-uart11-default {
	2588	+ pinmux {
	2589	+ pins = "gpio33", "gpio34";
	2590	+ function = "qup11";
	2591	+ };
	2592	+ };
	2593	+
	2594	+ qup_uart12_default: qup-uart12-default {
	2595	+ pinmux {
	2596	+ pins = "gpio51", "gpio52";
	2597	+ function = "qup12";
	2598	+ };
	2599	+ };
	2600	+
	2601	+ qup_uart13_default: qup-uart13-default {
	2602	+ pinmux {
	2603	+ pins = "gpio107", "gpio108";
	2604	+ function = "qup13";
	2605	+ };
	2606	+ };
	2607	+
	2608	+ qup_uart14_default: qup-uart14-default {
	2609	+ pinmux {
	2610	+ pins = "gpio31", "gpio32";
	2611	+ function = "qup14";
	2612	+ };
	2613	+ };
	2614	+
	2615	+ qup_uart15_default: qup-uart15-default {
	2616	+ pinmux {
	2617	+ pins = "gpio83", "gpio84";
	2618	+ function = "qup15";
	2619	+ };
	2620	+ };
	2621	+
	2622	+ quat_mi2s_sleep: quat_mi2s_sleep {
	2623	+ mux {
	2624	+ pins = "gpio58", "gpio59";
	2625	+ function = "gpio";
	2626	+ };
	2627	+
	2628	+ config {
	2629	+ pins = "gpio58", "gpio59";
	2630	+ drive-strength = <2>;
	2631	+ bias-pull-down;
	2632	+ input-enable;
	2633	+ };
	2634	+ };
	2635	+
	2636	+ quat_mi2s_active: quat_mi2s_active {
	2637	+ mux {
	2638	+ pins = "gpio58", "gpio59";
	2639	+ function = "qua_mi2s";
	2640	+ };
	2641	+
	2642	+ config {
	2643	+ pins = "gpio58", "gpio59";
	2644	+ drive-strength = <8>;
	2645	+ bias-disable;
	2646	+ output-high;
	2647	+ };
	2648	+ };
	2649	+
	2650	+ quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
	2651	+ mux {
	2652	+ pins = "gpio60";
	2653	+ function = "gpio";
	2654	+ };
	2655	+
	2656	+ config {
	2657	+ pins = "gpio60";
	2658	+ drive-strength = <2>;
	2659	+ bias-pull-down;
	2660	+ input-enable;
	2661	+ };
	2662	+ };
	2663	+
	2664	+ quat_mi2s_sd0_active: quat_mi2s_sd0_active {
	2665	+ mux {
	2666	+ pins = "gpio60";
	2667	+ function = "qua_mi2s";
	2668	+ };
	2669	+
	2670	+ config {
	2671	+ pins = "gpio60";
	2672	+ drive-strength = <8>;
	2673	+ bias-disable;
	2674	+ };
	2675	+ };
	2676	+
	2677	+ quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
	2678	+ mux {
	2679	+ pins = "gpio61";
	2680	+ function = "gpio";
	2681	+ };
	2682	+
	2683	+ config {
	2684	+ pins = "gpio61";
	2685	+ drive-strength = <2>;
	2686	+ bias-pull-down;
	2687	+ input-enable;
	2688	+ };
	2689	+ };
	2690	+
	2691	+ quat_mi2s_sd1_active: quat_mi2s_sd1_active {
	2692	+ mux {
	2693	+ pins = "gpio61";
	2694	+ function = "qua_mi2s";
	2695	+ };
	2696	+
	2697	+ config {
	2698	+ pins = "gpio61";
	2699	+ drive-strength = <8>;
	2700	+ bias-disable;
	2701	+ };
	2702	+ };
	2703	+
	2704	+ quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
	2705	+ mux {
	2706	+ pins = "gpio62";
	2707	+ function = "gpio";
	2708	+ };
	2709	+
	2710	+ config {
	2711	+ pins = "gpio62";
	2712	+ drive-strength = <2>;
	2713	+ bias-pull-down;
	2714	+ input-enable;
	2715	+ };
	2716	+ };
	2717	+
	2718	+ quat_mi2s_sd2_active: quat_mi2s_sd2_active {
	2719	+ mux {
	2720	+ pins = "gpio62";
	2721	+ function = "qua_mi2s";
	2722	+ };
	2723	+
	2724	+ config {
	2725	+ pins = "gpio62";
	2726	+ drive-strength = <8>;
	2727	+ bias-disable;
	2728	+ };
	2729	+ };
	2730	+
	2731	+ quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
	2732	+ mux {
	2733	+ pins = "gpio63";
	2734	+ function = "gpio";
	2735	+ };
	2736	+
	2737	+ config {
	2738	+ pins = "gpio63";
	2739	+ drive-strength = <2>;
	2740	+ bias-pull-down;
	2741	+ input-enable;
	2742	+ };
	2743	+ };
	2744	+
	2745	+ quat_mi2s_sd3_active: quat_mi2s_sd3_active {
	2746	+ mux {
	2747	+ pins = "gpio63";
	2748	+ function = "qua_mi2s";
	2749	+ };
	2750	+
	2751	+ config {
	2752	+ pins = "gpio63";
	2753	+ drive-strength = <8>;
	2754	+ bias-disable;
	2755	+ };
	2756	+ };
	2757	+ };
	2758	+
	2759	+ mss_pil: remoteproc@4080000 {
	2760	+ compatible = "qcom,sdm845-mss-pil";
	2761	+ reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
	2762	+ reg-names = "qdsp6", "rmb";
	2763	+
	2764	+ interrupts-extended =
	2765	+ <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
	2766	+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	2767	+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	2768	+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	2769	+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
	2770	+ <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
	2771	+ interrupt-names = "wdog", "fatal", "ready",
	2772	+ "handover", "stop-ack",
	2773	+ "shutdown-ack";
	2774	+
	2775	+ clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
	2776	+ <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
	2777	+ <&gcc GCC_BOOT_ROM_AHB_CLK>,
	2778	+ <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
	2779	+ <&gcc GCC_MSS_SNOC_AXI_CLK>,
	2780	+ <&gcc GCC_MSS_MFAB_AXIS_CLK>,
	2781	+ <&gcc GCC_PRNG_AHB_CLK>,
	2782	+ <&rpmhcc RPMH_CXO_CLK>;
	2783	+ clock-names = "iface", "bus", "mem", "gpll0_mss",
	2784	+ "snoc_axi", "mnoc_axi", "prng", "xo";
	2785	+
	2786	+ qcom,smem-states = <&modem_smp2p_out 0>;
	2787	+ qcom,smem-state-names = "stop";
	2788	+
	2789	+ resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
	2790	+ <&pdc_reset PDC_MODEM_SYNC_RESET>;
	2791	+ reset-names = "mss_restart", "pdc_reset";
	2792	+
	2793	+ qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
	2794	+
	2795	+ power-domains = <&aoss_qmp 2>,
	2796	+ <&rpmhpd SDM845_CX>,
	2797	+ <&rpmhpd SDM845_MX>,
	2798	+ <&rpmhpd SDM845_MSS>;
	2799	+ power-domain-names = "load_state", "cx", "mx", "mss";
	2800	+
	2801	+ mba {
	2802	+ memory-region = <&mba_region>;
	2803	+ };
	2804	+
	2805	+ mpss {
	2806	+ memory-region = <&mpss_region>;
	2807	+ };
	2808	+
	2809	+ glink-edge {
	2810	+ interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
	2811	+ label = "modem";
	2812	+ qcom,remote-pid = <1>;
	2813	+ mboxes = <&apss_shared 12>;
	2814	+ };
	2815	+ };
	2816	+
	2817	+ gpucc: clock-controller@5090000 {
	2818	+ compatible = "qcom,sdm845-gpucc";
	2819	+ reg = <0 0x05090000 0 0x9000>;
	2820	+ #clock-cells = <1>;
	2821	+ #reset-cells = <1>;
	2822	+ #power-domain-cells = <1>;
	2823	+ clocks = <&rpmhcc RPMH_CXO_CLK>,
	2824	+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
	2825	+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
	2826	+ clock-names = "bi_tcxo",
	2827	+ "gcc_gpu_gpll0_clk_src",
	2828	+ "gcc_gpu_gpll0_div_clk_src";
	2829	+ };
	2830	+
	2831	+ stm@6002000 {
	2832	+ compatible = "arm,coresight-stm", "arm,primecell";
	2833	+ reg = <0 0x06002000 0 0x1000>,
	2834	+ <0 0x16280000 0 0x180000>;
	2835	+ reg-names = "stm-base", "stm-stimulus-base";
	2836	+
	2837	+ clocks = <&aoss_qmp>;
	2838	+ clock-names = "apb_pclk";
	2839	+
	2840	+ out-ports {
	2841	+ port {
	2842	+ stm_out: endpoint {
	2843	+ remote-endpoint =
	2844	+ <&funnel0_in7>;
	2845	+ };
	2846	+ };
	2847	+ };
	2848	+ };
	2849	+
	2850	+ funnel@6041000 {
	2851	+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	2852	+ reg = <0 0x06041000 0 0x1000>;
	2853	+
	2854	+ clocks = <&aoss_qmp>;
	2855	+ clock-names = "apb_pclk";
	2856	+
	2857	+ out-ports {
	2858	+ port {
	2859	+ funnel0_out: endpoint {
	2860	+ remote-endpoint =
	2861	+ <&merge_funnel_in0>;
	2862	+ };
	2863	+ };
	2864	+ };
	2865	+
	2866	+ in-ports {
	2867	+ #address-cells = <1>;
	2868	+ #size-cells = <0>;
	2869	+
	2870	+ port@7 {
	2871	+ reg = <7>;
	2872	+ funnel0_in7: endpoint {
	2873	+ remote-endpoint = <&stm_out>;
	2874	+ };
	2875	+ };
	2876	+ };
	2877	+ };
	2878	+
	2879	+ funnel@6043000 {
	2880	+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	2881	+ reg = <0 0x06043000 0 0x1000>;
	2882	+
	2883	+ clocks = <&aoss_qmp>;
	2884	+ clock-names = "apb_pclk";
	2885	+
	2886	+ out-ports {
	2887	+ port {
	2888	+ funnel2_out: endpoint {
	2889	+ remote-endpoint =
	2890	+ <&merge_funnel_in2>;
	2891	+ };
	2892	+ };
	2893	+ };
	2894	+
	2895	+ in-ports {
	2896	+ #address-cells = <1>;
	2897	+ #size-cells = <0>;
	2898	+
	2899	+ port@5 {
	2900	+ reg = <5>;
	2901	+ funnel2_in5: endpoint {
	2902	+ remote-endpoint =
	2903	+ <&apss_merge_funnel_out>;
	2904	+ };
	2905	+ };
	2906	+ };
	2907	+ };
	2908	+
	2909	+ funnel@6045000 {
	2910	+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	2911	+ reg = <0 0x06045000 0 0x1000>;
	2912	+
	2913	+ clocks = <&aoss_qmp>;
	2914	+ clock-names = "apb_pclk";
	2915	+
	2916	+ out-ports {
	2917	+ port {
	2918	+ merge_funnel_out: endpoint {
	2919	+ remote-endpoint = <&etf_in>;
	2920	+ };
	2921	+ };
	2922	+ };
	2923	+
	2924	+ in-ports {
	2925	+ #address-cells = <1>;
	2926	+ #size-cells = <0>;
	2927	+
	2928	+ port@0 {
	2929	+ reg = <0>;
	2930	+ merge_funnel_in0: endpoint {
	2931	+ remote-endpoint =
	2932	+ <&funnel0_out>;
	2933	+ };
	2934	+ };
	2935	+
	2936	+ port@2 {
	2937	+ reg = <2>;
	2938	+ merge_funnel_in2: endpoint {
	2939	+ remote-endpoint =
	2940	+ <&funnel2_out>;
	2941	+ };
	2942	+ };
	2943	+ };
	2944	+ };
	2945	+
	2946	+ replicator@6046000 {
	2947	+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
	2948	+ reg = <0 0x06046000 0 0x1000>;
	2949	+
	2950	+ clocks = <&aoss_qmp>;
	2951	+ clock-names = "apb_pclk";
	2952	+
	2953	+ out-ports {
	2954	+ port {
	2955	+ replicator_out: endpoint {
	2956	+ remote-endpoint = <&etr_in>;
	2957	+ };
	2958	+ };
	2959	+ };
	2960	+
	2961	+ in-ports {
	2962	+ port {
	2963	+ replicator_in: endpoint {
	2964	+ remote-endpoint = <&etf_out>;
	2965	+ };
	2966	+ };
	2967	+ };
	2968	+ };
	2969	+
	2970	+ etf@6047000 {
	2971	+ compatible = "arm,coresight-tmc", "arm,primecell";
	2972	+ reg = <0 0x06047000 0 0x1000>;
	2973	+
	2974	+ clocks = <&aoss_qmp>;
	2975	+ clock-names = "apb_pclk";
	2976	+
	2977	+ out-ports {
	2978	+ port {
	2979	+ etf_out: endpoint {
	2980	+ remote-endpoint =
	2981	+ <&replicator_in>;
	2982	+ };
	2983	+ };
	2984	+ };
	2985	+
	2986	+ in-ports {
	2987	+ #address-cells = <1>;
	2988	+ #size-cells = <0>;
	2989	+
	2990	+ port@1 {
	2991	+ reg = <1>;
	2992	+ etf_in: endpoint {
	2993	+ remote-endpoint =
	2994	+ <&merge_funnel_out>;
	2995	+ };
	2996	+ };
	2997	+ };
	2998	+ };
	2999	+
	3000	+ etr@6048000 {
	3001	+ compatible = "arm,coresight-tmc", "arm,primecell";
	3002	+ reg = <0 0x06048000 0 0x1000>;
	3003	+
	3004	+ clocks = <&aoss_qmp>;
	3005	+ clock-names = "apb_pclk";
	3006	+ arm,scatter-gather;
	3007	+
	3008	+ in-ports {
	3009	+ port {
	3010	+ etr_in: endpoint {
	3011	+ remote-endpoint =
	3012	+ <&replicator_out>;
	3013	+ };
	3014	+ };
	3015	+ };
	3016	+ };
	3017	+
	3018	+ etm@7040000 {
	3019	+ compatible = "arm,coresight-etm4x", "arm,primecell";
	3020	+ reg = <0 0x07040000 0 0x1000>;
	3021	+
	3022	+ cpu = <&CPU0>;
	3023	+
	3024	+ clocks = <&aoss_qmp>;
	3025	+ clock-names = "apb_pclk";
	3026	+ arm,coresight-loses-context-with-cpu;
	3027	+
	3028	+ out-ports {
	3029	+ port {
	3030	+ etm0_out: endpoint {
	3031	+ remote-endpoint =
	3032	+ <&apss_funnel_in0>;
	3033	+ };
	3034	+ };
	3035	+ };
	3036	+ };
	3037	+
	3038	+ etm@7140000 {
	3039	+ compatible = "arm,coresight-etm4x", "arm,primecell";
	3040	+ reg = <0 0x07140000 0 0x1000>;
	3041	+
	3042	+ cpu = <&CPU1>;
	3043	+
	3044	+ clocks = <&aoss_qmp>;
	3045	+ clock-names = "apb_pclk";
	3046	+ arm,coresight-loses-context-with-cpu;
	3047	+
	3048	+ out-ports {
	3049	+ port {
	3050	+ etm1_out: endpoint {
	3051	+ remote-endpoint =
	3052	+ <&apss_funnel_in1>;
	3053	+ };
	3054	+ };
	3055	+ };
	3056	+ };
	3057	+
	3058	+ etm@7240000 {
	3059	+ compatible = "arm,coresight-etm4x", "arm,primecell";
	3060	+ reg = <0 0x07240000 0 0x1000>;
	3061	+
	3062	+ cpu = <&CPU2>;
	3063	+
	3064	+ clocks = <&aoss_qmp>;
	3065	+ clock-names = "apb_pclk";
	3066	+ arm,coresight-loses-context-with-cpu;
	3067	+
	3068	+ out-ports {
	3069	+ port {
	3070	+ etm2_out: endpoint {
	3071	+ remote-endpoint =
	3072	+ <&apss_funnel_in2>;
	3073	+ };
	3074	+ };
	3075	+ };
	3076	+ };
	3077	+
	3078	+ etm@7340000 {
	3079	+ compatible = "arm,coresight-etm4x", "arm,primecell";
	3080	+ reg = <0 0x07340000 0 0x1000>;
	3081	+
	3082	+ cpu = <&CPU3>;
	3083	+
	3084	+ clocks = <&aoss_qmp>;
	3085	+ clock-names = "apb_pclk";
	3086	+ arm,coresight-loses-context-with-cpu;
	3087	+
	3088	+ out-ports {
	3089	+ port {
	3090	+ etm3_out: endpoint {
	3091	+ remote-endpoint =
	3092	+ <&apss_funnel_in3>;
	3093	+ };
	3094	+ };
	3095	+ };
	3096	+ };
	3097	+
	3098	+ etm@7440000 {
	3099	+ compatible = "arm,coresight-etm4x", "arm,primecell";
	3100	+ reg = <0 0x07440000 0 0x1000>;
	3101	+
	3102	+ cpu = <&CPU4>;
	3103	+
	3104	+ clocks = <&aoss_qmp>;
	3105	+ clock-names = "apb_pclk";
	3106	+ arm,coresight-loses-context-with-cpu;
	3107	+
	3108	+ out-ports {
	3109	+ port {
	3110	+ etm4_out: endpoint {
	3111	+ remote-endpoint =
	3112	+ <&apss_funnel_in4>;
	3113	+ };
	3114	+ };
	3115	+ };
	3116	+ };
	3117	+
	3118	+ etm@7540000 {
	3119	+ compatible = "arm,coresight-etm4x", "arm,primecell";
	3120	+ reg = <0 0x07540000 0 0x1000>;
	3121	+
	3122	+ cpu = <&CPU5>;
	3123	+
	3124	+ clocks = <&aoss_qmp>;
	3125	+ clock-names = "apb_pclk";
	3126	+ arm,coresight-loses-context-with-cpu;
	3127	+
	3128	+ out-ports {
	3129	+ port {
	3130	+ etm5_out: endpoint {
	3131	+ remote-endpoint =
	3132	+ <&apss_funnel_in5>;
	3133	+ };
	3134	+ };
	3135	+ };
	3136	+ };
	3137	+
	3138	+ etm@7640000 {
	3139	+ compatible = "arm,coresight-etm4x", "arm,primecell";
	3140	+ reg = <0 0x07640000 0 0x1000>;
	3141	+
	3142	+ cpu = <&CPU6>;
	3143	+
	3144	+ clocks = <&aoss_qmp>;
	3145	+ clock-names = "apb_pclk";
	3146	+ arm,coresight-loses-context-with-cpu;
	3147	+
	3148	+ out-ports {
	3149	+ port {
	3150	+ etm6_out: endpoint {
	3151	+ remote-endpoint =
	3152	+ <&apss_funnel_in6>;
	3153	+ };
	3154	+ };
	3155	+ };
	3156	+ };
	3157	+
	3158	+ etm@7740000 {
	3159	+ compatible = "arm,coresight-etm4x", "arm,primecell";
	3160	+ reg = <0 0x07740000 0 0x1000>;
	3161	+
	3162	+ cpu = <&CPU7>;
	3163	+
	3164	+ clocks = <&aoss_qmp>;
	3165	+ clock-names = "apb_pclk";
	3166	+ arm,coresight-loses-context-with-cpu;
	3167	+
	3168	+ out-ports {
	3169	+ port {
	3170	+ etm7_out: endpoint {
	3171	+ remote-endpoint =
	3172	+ <&apss_funnel_in7>;
	3173	+ };
	3174	+ };
	3175	+ };
	3176	+ };
	3177	+
	3178	+ funnel@7800000 { /* APSS Funnel */
	3179	+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	3180	+ reg = <0 0x07800000 0 0x1000>;
	3181	+
	3182	+ clocks = <&aoss_qmp>;
	3183	+ clock-names = "apb_pclk";
	3184	+
	3185	+ out-ports {
	3186	+ port {
	3187	+ apss_funnel_out: endpoint {
	3188	+ remote-endpoint =
	3189	+ <&apss_merge_funnel_in>;
	3190	+ };
	3191	+ };
	3192	+ };
	3193	+
	3194	+ in-ports {
	3195	+ #address-cells = <1>;
	3196	+ #size-cells = <0>;
	3197	+
	3198	+ port@0 {
	3199	+ reg = <0>;
	3200	+ apss_funnel_in0: endpoint {
	3201	+ remote-endpoint =
	3202	+ <&etm0_out>;
	3203	+ };
	3204	+ };
	3205	+
	3206	+ port@1 {
	3207	+ reg = <1>;
	3208	+ apss_funnel_in1: endpoint {
	3209	+ remote-endpoint =
	3210	+ <&etm1_out>;
	3211	+ };
	3212	+ };
	3213	+
	3214	+ port@2 {
	3215	+ reg = <2>;
	3216	+ apss_funnel_in2: endpoint {
	3217	+ remote-endpoint =
	3218	+ <&etm2_out>;
	3219	+ };
	3220	+ };
	3221	+
	3222	+ port@3 {
	3223	+ reg = <3>;
	3224	+ apss_funnel_in3: endpoint {
	3225	+ remote-endpoint =
	3226	+ <&etm3_out>;
	3227	+ };
	3228	+ };
	3229	+
	3230	+ port@4 {
	3231	+ reg = <4>;
	3232	+ apss_funnel_in4: endpoint {
	3233	+ remote-endpoint =
	3234	+ <&etm4_out>;
	3235	+ };
	3236	+ };
	3237	+
	3238	+ port@5 {
	3239	+ reg = <5>;
	3240	+ apss_funnel_in5: endpoint {
	3241	+ remote-endpoint =
	3242	+ <&etm5_out>;
	3243	+ };
	3244	+ };
	3245	+
	3246	+ port@6 {
	3247	+ reg = <6>;
	3248	+ apss_funnel_in6: endpoint {
	3249	+ remote-endpoint =
	3250	+ <&etm6_out>;
	3251	+ };
	3252	+ };
	3253	+
	3254	+ port@7 {
	3255	+ reg = <7>;
	3256	+ apss_funnel_in7: endpoint {
	3257	+ remote-endpoint =
	3258	+ <&etm7_out>;
	3259	+ };
	3260	+ };
	3261	+ };
	3262	+ };
	3263	+
	3264	+ funnel@7810000 {
	3265	+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	3266	+ reg = <0 0x07810000 0 0x1000>;
	3267	+
	3268	+ clocks = <&aoss_qmp>;
	3269	+ clock-names = "apb_pclk";
	3270	+
	3271	+ out-ports {
	3272	+ port {
	3273	+ apss_merge_funnel_out: endpoint {
	3274	+ remote-endpoint =
	3275	+ <&funnel2_in5>;
	3276	+ };
	3277	+ };
	3278	+ };
	3279	+
	3280	+ in-ports {
	3281	+ port {
	3282	+ apss_merge_funnel_in: endpoint {
	3283	+ remote-endpoint =
	3284	+ <&apss_funnel_out>;
	3285	+ };
	3286	+ };
	3287	+ };
	3288	+ };
	3289	+
	3290	+ sdhc_2: sdhci@8804000 {
	3291	+ compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
	3292	+ reg = <0 0x08804000 0 0x1000>;
	3293	+
	3294	+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
	3295	+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
	3296	+ interrupt-names = "hc_irq", "pwr_irq";
	3297	+
	3298	+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
	3299	+ <&gcc GCC_SDCC2_APPS_CLK>;
	3300	+ clock-names = "iface", "core";
	3301	+ iommus = <&apps_smmu 0xa0 0xf>;
	3302	+ power-domains = <&rpmhpd SDM845_CX>;
	3303	+ operating-points-v2 = <&sdhc2_opp_table>;
	3304	+
	3305	+ status = "disabled";
	3306	+
	3307	+ sdhc2_opp_table: sdhc2-opp-table {
	3308	+ compatible = "operating-points-v2";
	3309	+
	3310	+ opp-9600000 {
	3311	+ opp-hz = /bits/ 64 <9600000>;
	3312	+ required-opps = <&rpmhpd_opp_min_svs>;
	3313	+ };
	3314	+
	3315	+ opp-19200000 {
	3316	+ opp-hz = /bits/ 64 <19200000>;
	3317	+ required-opps = <&rpmhpd_opp_low_svs>;
	3318	+ };
	3319	+
	3320	+ opp-100000000 {
	3321	+ opp-hz = /bits/ 64 <100000000>;
	3322	+ required-opps = <&rpmhpd_opp_svs>;
	3323	+ };
	3324	+
	3325	+ opp-201500000 {
	3326	+ opp-hz = /bits/ 64 <201500000>;
	3327	+ required-opps = <&rpmhpd_opp_svs_l1>;
	3328	+ };
	3329	+ };
	3330	+ };
	3331	+
	3332	+ qspi_opp_table: qspi-opp-table {
	3333	+ compatible = "operating-points-v2";
	3334	+
	3335	+ opp-19200000 {
	3336	+ opp-hz = /bits/ 64 <19200000>;
	3337	+ required-opps = <&rpmhpd_opp_min_svs>;
	3338	+ };
	3339	+
	3340	+ opp-100000000 {
	3341	+ opp-hz = /bits/ 64 <100000000>;
	3342	+ required-opps = <&rpmhpd_opp_low_svs>;
	3343	+ };
	3344	+
	3345	+ opp-150000000 {
	3346	+ opp-hz = /bits/ 64 <150000000>;
	3347	+ required-opps = <&rpmhpd_opp_svs>;
	3348	+ };
	3349	+
	3350	+ opp-300000000 {
	3351	+ opp-hz = /bits/ 64 <300000000>;
	3352	+ required-opps = <&rpmhpd_opp_nom>;
	3353	+ };
	3354	+ };
	3355	+
	3356	+ qspi: spi@88df000 {
	3357	+ compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
	3358	+ reg = <0 0x088df000 0 0x600>;
	3359	+ #address-cells = <1>;
	3360	+ #size-cells = <0>;
	3361	+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	3362	+ clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
	3363	+ <&gcc GCC_QSPI_CORE_CLK>;
	3364	+ clock-names = "iface", "core";
	3365	+ power-domains = <&rpmhpd SDM845_CX>;
	3366	+ operating-points-v2 = <&qspi_opp_table>;
	3367	+ status = "disabled";
	3368	+ };
	3369	+
	3370	+ slim: slim@171c0000 {
	3371	+ compatible = "qcom,slim-ngd-v2.1.0";
	3372	+ reg = <0 0x171c0000 0 0x2c000>;
	3373	+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
	3374	+
	3375	+ qcom,apps-ch-pipes = <0x780000>;
	3376	+ qcom,ea-pc = <0x270>;
	3377	+ status = "okay";
	3378	+ dmas = <&slimbam 3>, <&slimbam 4>,
	3379	+ <&slimbam 5>, <&slimbam 6>;
	3380	+ dma-names = "rx", "tx", "tx2", "rx2";
	3381	+
	3382	+ iommus = <&apps_smmu 0x1806 0x0>;
	3383	+ #address-cells = <1>;
	3384	+ #size-cells = <0>;
	3385	+
	3386	+ ngd@1 {
	3387	+ reg = <1>;
	3388	+ #address-cells = <2>;
	3389	+ #size-cells = <0>;
	3390	+
	3391	+ wcd9340_ifd: ifd@0{
	3392	+ compatible = "slim217,250";
	3393	+ reg = <0 0>;
	3394	+ };
	3395	+
	3396	+ wcd9340: codec@1{
	3397	+ compatible = "slim217,250";
	3398	+ reg = <1 0>;
	3399	+ slim-ifc-dev = <&wcd9340_ifd>;
	3400	+
	3401	+ #sound-dai-cells = <1>;
	3402	+
	3403	+ interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
	3404	+ interrupt-controller;
	3405	+ #interrupt-cells = <1>;
	3406	+
	3407	+ #clock-cells = <0>;
	3408	+ clock-frequency = <9600000>;
	3409	+ clock-output-names = "mclk";
	3410	+ qcom,micbias1-microvolt = <1800000>;
	3411	+ qcom,micbias2-microvolt = <1800000>;
	3412	+ qcom,micbias3-microvolt = <1800000>;
	3413	+ qcom,micbias4-microvolt = <1800000>;
	3414	+
	3415	+ #address-cells = <1>;
	3416	+ #size-cells = <1>;
	3417	+
	3418	+ wcdgpio: gpio-controller@42 {
	3419	+ compatible = "qcom,wcd9340-gpio";
	3420	+ gpio-controller;
	3421	+ #gpio-cells = <2>;
	3422	+ reg = <0x42 0x2>;
	3423	+ };
	3424	+
	3425	+ swm: swm@c85 {
	3426	+ compatible = "qcom,soundwire-v1.3.0";
	3427	+ reg = <0xc85 0x40>;
	3428	+ interrupts-extended = <&wcd9340 20>;
	3429	+
	3430	+ qcom,dout-ports = <6>;
	3431	+ qcom,din-ports = <2>;
	3432	+ qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
	3433	+ qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
	3434	+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
	3435	+
	3436	+ #sound-dai-cells = <1>;
	3437	+ clocks = <&wcd9340>;
	3438	+ clock-names = "iface";
	3439	+ #address-cells = <2>;
	3440	+ #size-cells = <0>;
	3441	+
	3442	+
	3443	+ };
	3444	+ };
	3445	+ };
	3446	+ };
	3447	+
	3448	+ sound: sound {
	3449	+ };
	3450	+
	3451	+ usb_1_hsphy: phy@88e2000 {
	3452	+ compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
	3453	+ reg = <0 0x088e2000 0 0x400>;
	3454	+ status = "disabled";
	3455	+ #phy-cells = <0>;
	3456	+
	3457	+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	3458	+ <&rpmhcc RPMH_CXO_CLK>;
	3459	+ clock-names = "cfg_ahb", "ref";
	3460	+
	3461	+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
	3462	+
	3463	+ nvmem-cells = <&qusb2p_hstx_trim>;
	3464	+ };
	3465	+
	3466	+ usb_2_hsphy: phy@88e3000 {
	3467	+ compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
	3468	+ reg = <0 0x088e3000 0 0x400>;
	3469	+ status = "disabled";
	3470	+ #phy-cells = <0>;
	3471	+
	3472	+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	3473	+ <&rpmhcc RPMH_CXO_CLK>;
	3474	+ clock-names = "cfg_ahb", "ref";
	3475	+
	3476	+ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
	3477	+
	3478	+ nvmem-cells = <&qusb2s_hstx_trim>;
	3479	+ };
	3480	+
	3481	+ usb_1_qmpphy: phy@88e9000 {
	3482	+ compatible = "qcom,sdm845-qmp-usb3-phy";
	3483	+ reg = <0 0x088e9000 0 0x18c>,
	3484	+ <0 0x088e8000 0 0x10>;
	3485	+ reg-names = "reg-base", "dp_com";
	3486	+ status = "disabled";
	3487	+ #clock-cells = <1>;
	3488	+ #address-cells = <2>;
	3489	+ #size-cells = <2>;
	3490	+ ranges;
	3491	+
	3492	+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
	3493	+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	3494	+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
	3495	+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
	3496	+ clock-names = "aux", "cfg_ahb", "ref", "com_aux";
	3497	+
	3498	+ resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
	3499	+ <&gcc GCC_USB3_PHY_PRIM_BCR>;
	3500	+ reset-names = "phy", "common";
	3501	+
	3502	+ usb_1_ssphy: lanes@88e9200 {
	3503	+ reg = <0 0x088e9200 0 0x128>,
	3504	+ <0 0x088e9400 0 0x200>,
	3505	+ <0 0x088e9c00 0 0x218>,
	3506	+ <0 0x088e9600 0 0x128>,
	3507	+ <0 0x088e9800 0 0x200>,
	3508	+ <0 0x088e9a00 0 0x100>;
	3509	+ #phy-cells = <0>;
	3510	+ clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
	3511	+ clock-names = "pipe0";
	3512	+ clock-output-names = "usb3_phy_pipe_clk_src";
	3513	+ };
	3514	+ };
	3515	+
	3516	+ usb_2_qmpphy: phy@88eb000 {
	3517	+ compatible = "qcom,sdm845-qmp-usb3-uni-phy";
	3518	+ reg = <0 0x088eb000 0 0x18c>;
	3519	+ status = "disabled";
	3520	+ #clock-cells = <1>;
	3521	+ #address-cells = <2>;
	3522	+ #size-cells = <2>;
	3523	+ ranges;
	3524	+
	3525	+ clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
	3526	+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
	3527	+ <&gcc GCC_USB3_SEC_CLKREF_CLK>,
	3528	+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
	3529	+ clock-names = "aux", "cfg_ahb", "ref", "com_aux";
	3530	+
	3531	+ resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
	3532	+ <&gcc GCC_USB3_PHY_SEC_BCR>;
	3533	+ reset-names = "phy", "common";
	3534	+
	3535	+ usb_2_ssphy: lane@88eb200 {
	3536	+ reg = <0 0x088eb200 0 0x128>,
	3537	+ <0 0x088eb400 0 0x1fc>,
	3538	+ <0 0x088eb800 0 0x218>,
	3539	+ <0 0x088eb600 0 0x70>;
	3540	+ #phy-cells = <0>;
	3541	+ clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
	3542	+ clock-names = "pipe0";
	3543	+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
	3544	+ };
	3545	+ };
	3546	+
	3547	+ usb_1: usb@a6f8800 {
	3548	+ compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
	3549	+ reg = <0 0x0a6f8800 0 0x400>;
	3550	+ status = "disabled";
	3551	+ #address-cells = <2>;
	3552	+ #size-cells = <2>;
	3553	+ ranges;
	3554	+ dma-ranges;
	3555	+
	3556	+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
	3557	+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
	3558	+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
	3559	+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
	3560	+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
	3561	+ clock-names = "cfg_noc", "core", "iface", "mock_utmi",
	3562	+ "sleep";
	3563	+
	3564	+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
	3565	+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
	3566	+ assigned-clock-rates = <19200000>, <150000000>;
	3567	+
	3568	+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	3569	+ <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
	3570	+ <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
	3571	+ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
	3572	+ interrupt-names = "hs_phy_irq", "ss_phy_irq",
	3573	+ "dm_hs_phy_irq", "dp_hs_phy_irq";
	3574	+
	3575	+ power-domains = <&gcc USB30_PRIM_GDSC>;
	3576	+
	3577	+ resets = <&gcc GCC_USB30_PRIM_BCR>;
	3578	+
	3579	+ interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
	3580	+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
	3581	+ interconnect-names = "usb-ddr", "apps-usb";
	3582	+
	3583	+ usb_1_dwc3: dwc3@a600000 {
	3584	+ compatible = "snps,dwc3";
	3585	+ reg = <0 0x0a600000 0 0xcd00>;
	3586	+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
	3587	+ iommus = <&apps_smmu 0x740 0>;
	3588	+ snps,dis_u2_susphy_quirk;
	3589	+ snps,dis_enblslpm_quirk;
	3590	+ phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
	3591	+ phy-names = "usb2-phy", "usb3-phy";
	3592	+ };
	3593	+ };
	3594	+
	3595	+ usb_2: usb@a8f8800 {
	3596	+ compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
	3597	+ reg = <0 0x0a8f8800 0 0x400>;
	3598	+ status = "disabled";
	3599	+ #address-cells = <2>;
	3600	+ #size-cells = <2>;
	3601	+ ranges;
	3602	+ dma-ranges;
	3603	+
	3604	+ clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
	3605	+ <&gcc GCC_USB30_SEC_MASTER_CLK>,
	3606	+ <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
	3607	+ <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
	3608	+ <&gcc GCC_USB30_SEC_SLEEP_CLK>;
	3609	+ clock-names = "cfg_noc", "core", "iface", "mock_utmi",
	3610	+ "sleep";
	3611	+
	3612	+ assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
	3613	+ <&gcc GCC_USB30_SEC_MASTER_CLK>;
	3614	+ assigned-clock-rates = <19200000>, <150000000>;
	3615	+
	3616	+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	3617	+ <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
	3618	+ <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
	3619	+ <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
	3620	+ interrupt-names = "hs_phy_irq", "ss_phy_irq",
	3621	+ "dm_hs_phy_irq", "dp_hs_phy_irq";
	3622	+
	3623	+ power-domains = <&gcc USB30_SEC_GDSC>;
	3624	+
	3625	+ resets = <&gcc GCC_USB30_SEC_BCR>;
	3626	+
	3627	+ interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
	3628	+ <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
	3629	+ interconnect-names = "usb-ddr", "apps-usb";
	3630	+
	3631	+ usb_2_dwc3: dwc3@a800000 {
	3632	+ compatible = "snps,dwc3";
	3633	+ reg = <0 0x0a800000 0 0xcd00>;
	3634	+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	3635	+ iommus = <&apps_smmu 0x760 0>;
	3636	+ snps,dis_u2_susphy_quirk;
	3637	+ snps,dis_enblslpm_quirk;
	3638	+ phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
	3639	+ phy-names = "usb2-phy", "usb3-phy";
	3640	+ };
	3641	+ };
	3642	+
	3643	+ venus: video-codec@aa00000 {
	3644	+ compatible = "qcom,sdm845-venus-v2";
	3645	+ reg = <0 0x0aa00000 0 0xff000>;
	3646	+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	3647	+ power-domains = <&videocc VENUS_GDSC>,
	3648	+ <&videocc VCODEC0_GDSC>,
	3649	+ <&videocc VCODEC1_GDSC>,
	3650	+ <&rpmhpd SDM845_CX>;
	3651	+ power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
	3652	+ operating-points-v2 = <&venus_opp_table>;
	3653	+ clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
	3654	+ <&videocc VIDEO_CC_VENUS_AHB_CLK>,
	3655	+ <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
	3656	+ <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
	3657	+ <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
	3658	+ <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
	3659	+ <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
	3660	+ clock-names = "core", "iface", "bus",
	3661	+ "vcodec0_core", "vcodec0_bus",
	3662	+ "vcodec1_core", "vcodec1_bus";
	3663	+ iommus = <&apps_smmu 0x10a0 0x8>,
	3664	+ <&apps_smmu 0x10b0 0x0>;
	3665	+ memory-region = <&venus_mem>;
	3666	+
	3667	+ video-core0 {
	3668	+ compatible = "venus-decoder";
	3669	+ };
	3670	+
	3671	+ video-core1 {
	3672	+ compatible = "venus-encoder";
	3673	+ };
	3674	+
	3675	+ venus_opp_table: venus-opp-table {
	3676	+ compatible = "operating-points-v2";
	3677	+
	3678	+ opp-100000000 {
	3679	+ opp-hz = /bits/ 64 <100000000>;
	3680	+ required-opps = <&rpmhpd_opp_min_svs>;
	3681	+ };
	3682	+
	3683	+ opp-200000000 {
	3684	+ opp-hz = /bits/ 64 <200000000>;
	3685	+ required-opps = <&rpmhpd_opp_low_svs>;
	3686	+ };
	3687	+
	3688	+ opp-320000000 {
	3689	+ opp-hz = /bits/ 64 <320000000>;
	3690	+ required-opps = <&rpmhpd_opp_svs>;
	3691	+ };
	3692	+
	3693	+ opp-380000000 {
	3694	+ opp-hz = /bits/ 64 <380000000>;
	3695	+ required-opps = <&rpmhpd_opp_svs_l1>;
	3696	+ };
	3697	+
	3698	+ opp-444000000 {
	3699	+ opp-hz = /bits/ 64 <444000000>;
	3700	+ required-opps = <&rpmhpd_opp_nom>;
	3701	+ };
	3702	+
	3703	+ opp-533000097 {
	3704	+ opp-hz = /bits/ 64 <533000097>;
	3705	+ required-opps = <&rpmhpd_opp_turbo>;
	3706	+ };
	3707	+ };
	3708	+ };
	3709	+
	3710	+ videocc: clock-controller@ab00000 {
	3711	+ compatible = "qcom,sdm845-videocc";
	3712	+ reg = <0 0x0ab00000 0 0x10000>;
	3713	+ clocks = <&rpmhcc RPMH_CXO_CLK>;
	3714	+ clock-names = "bi_tcxo";
	3715	+ #clock-cells = <1>;
	3716	+ #power-domain-cells = <1>;
	3717	+ #reset-cells = <1>;
	3718	+ };
	3719	+
	3720	+ cci: cci@ac4a000 {
	3721	+ compatible = "qcom,sdm845-cci";
	3722	+ #address-cells = <1>;
	3723	+ #size-cells = <0>;
	3724	+
	3725	+ reg = <0 0x0ac4a000 0 0x4000>;
	3726	+ interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
	3727	+ power-domains = <&clock_camcc TITAN_TOP_GDSC>;
	3728	+
	3729	+ clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
	3730	+ <&clock_camcc CAM_CC_SOC_AHB_CLK>,
	3731	+ <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
	3732	+ <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
	3733	+ <&clock_camcc CAM_CC_CCI_CLK>,
	3734	+ <&clock_camcc CAM_CC_CCI_CLK_SRC>;
	3735	+ clock-names = "camnoc_axi",
	3736	+ "soc_ahb",
	3737	+ "slow_ahb_src",
	3738	+ "cpas_ahb",
	3739	+ "cci",
	3740	+ "cci_src";
	3741	+
	3742	+ assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
	3743	+ <&clock_camcc CAM_CC_CCI_CLK>;
	3744	+ assigned-clock-rates = <80000000>, <37500000>;
	3745	+
	3746	+ pinctrl-names = "default", "sleep";
	3747	+ pinctrl-0 = <&cci0_default &cci1_default>;
	3748	+ pinctrl-1 = <&cci0_sleep &cci1_sleep>;
	3749	+
	3750	+ status = "disabled";
	3751	+
	3752	+ cci_i2c0: i2c-bus@0 {
	3753	+ reg = <0>;
	3754	+ clock-frequency = <1000000>;
	3755	+ #address-cells = <1>;
	3756	+ #size-cells = <0>;
	3757	+ };
	3758	+
	3759	+ cci_i2c1: i2c-bus@1 {
	3760	+ reg = <1>;
	3761	+ clock-frequency = <1000000>;
	3762	+ #address-cells = <1>;
	3763	+ #size-cells = <0>;
	3764	+ };
	3765	+ };
	3766	+
	3767	+ clock_camcc: clock-controller@ad00000 {
	3768	+ compatible = "qcom,sdm845-camcc";
	3769	+ reg = <0 0x0ad00000 0 0x10000>;
	3770	+ #clock-cells = <1>;
	3771	+ #reset-cells = <1>;
	3772	+ #power-domain-cells = <1>;
	3773	+ };
	3774	+
	3775	+ dsi_opp_table: dsi-opp-table {
	3776	+ compatible = "operating-points-v2";
	3777	+
	3778	+ opp-19200000 {
	3779	+ opp-hz = /bits/ 64 <19200000>;
	3780	+ required-opps = <&rpmhpd_opp_min_svs>;
	3781	+ };
	3782	+
	3783	+ opp-180000000 {
	3784	+ opp-hz = /bits/ 64 <180000000>;
	3785	+ required-opps = <&rpmhpd_opp_low_svs>;
	3786	+ };
	3787	+
	3788	+ opp-275000000 {
	3789	+ opp-hz = /bits/ 64 <275000000>;
	3790	+ required-opps = <&rpmhpd_opp_svs>;
	3791	+ };
	3792	+
	3793	+ opp-328580000 {
	3794	+ opp-hz = /bits/ 64 <328580000>;
	3795	+ required-opps = <&rpmhpd_opp_svs_l1>;
	3796	+ };
	3797	+
	3798	+ opp-358000000 {
	3799	+ opp-hz = /bits/ 64 <358000000>;
	3800	+ required-opps = <&rpmhpd_opp_nom>;
	3801	+ };
	3802	+ };
	3803	+
	3804	+ mdss: mdss@ae00000 {
	3805	+ compatible = "qcom,sdm845-mdss";
	3806	+ reg = <0 0x0ae00000 0 0x1000>;
	3807	+ reg-names = "mdss";
	3808	+
	3809	+ power-domains = <&dispcc MDSS_GDSC>;
	3810	+
	3811	+ clocks = <&gcc GCC_DISP_AHB_CLK>,
	3812	+ <&gcc GCC_DISP_AXI_CLK>,
	3813	+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
	3814	+ clock-names = "iface", "bus", "core";
	3815	+
	3816	+ assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
	3817	+ assigned-clock-rates = <300000000>;
	3818	+
	3819	+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	3820	+ interrupt-controller;
	3821	+ #interrupt-cells = <1>;
	3822	+
	3823	+ interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
	3824	+ <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
	3825	+ interconnect-names = "mdp0-mem", "mdp1-mem";
	3826	+
	3827	+ iommus = <&apps_smmu 0x880 0x8>,
	3828	+ <&apps_smmu 0xc80 0x8>;
	3829	+
	3830	+ status = "disabled";
	3831	+
	3832	+ #address-cells = <2>;
	3833	+ #size-cells = <2>;
	3834	+ ranges;
	3835	+
	3836	+ mdss_mdp: mdp@ae01000 {
	3837	+ compatible = "qcom,sdm845-dpu";
	3838	+ reg = <0 0x0ae01000 0 0x8f000>,
	3839	+ <0 0x0aeb0000 0 0x2008>;
	3840	+ reg-names = "mdp", "vbif";
	3841	+
	3842	+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	3843	+ <&dispcc DISP_CC_MDSS_AXI_CLK>,
	3844	+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
	3845	+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
	3846	+ clock-names = "iface", "bus", "core", "vsync";
	3847	+
	3848	+ assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
	3849	+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
	3850	+ assigned-clock-rates = <300000000>,
	3851	+ <19200000>;
	3852	+ operating-points-v2 = <&mdp_opp_table>;
	3853	+ power-domains = <&rpmhpd SDM845_CX>;
	3854	+
	3855	+ interrupt-parent = <&mdss>;
	3856	+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
	3857	+
	3858	+ status = "disabled";
	3859	+
	3860	+ ports {
	3861	+ #address-cells = <1>;
	3862	+ #size-cells = <0>;
	3863	+
	3864	+ port@0 {
	3865	+ reg = <0>;
	3866	+ dpu_intf1_out: endpoint {
	3867	+ remote-endpoint = <&dsi0_in>;
	3868	+ };
	3869	+ };
	3870	+
	3871	+ port@1 {
	3872	+ reg = <1>;
	3873	+ dpu_intf2_out: endpoint {
	3874	+ remote-endpoint = <&dsi1_in>;
	3875	+ };
	3876	+ };
	3877	+ };
	3878	+
	3879	+ mdp_opp_table: mdp-opp-table {
	3880	+ compatible = "operating-points-v2";
	3881	+
	3882	+ opp-19200000 {
	3883	+ opp-hz = /bits/ 64 <19200000>;
	3884	+ required-opps = <&rpmhpd_opp_min_svs>;
	3885	+ };
	3886	+
	3887	+ opp-171428571 {
	3888	+ opp-hz = /bits/ 64 <171428571>;
	3889	+ required-opps = <&rpmhpd_opp_low_svs>;
	3890	+ };
	3891	+
	3892	+ opp-344000000 {
	3893	+ opp-hz = /bits/ 64 <344000000>;
	3894	+ required-opps = <&rpmhpd_opp_svs_l1>;
	3895	+ };
	3896	+
	3897	+ opp-430000000 {
	3898	+ opp-hz = /bits/ 64 <430000000>;
	3899	+ required-opps = <&rpmhpd_opp_nom>;
	3900	+ };
	3901	+ };
	3902	+ };
	3903	+
	3904	+ dsi0: dsi@ae94000 {
	3905	+ compatible = "qcom,mdss-dsi-ctrl";
	3906	+ reg = <0 0x0ae94000 0 0x400>;
	3907	+ reg-names = "dsi_ctrl";
	3908	+
	3909	+ interrupt-parent = <&mdss>;
	3910	+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
	3911	+
	3912	+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
	3913	+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
	3914	+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
	3915	+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
	3916	+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
	3917	+ <&dispcc DISP_CC_MDSS_AXI_CLK>;
	3918	+ clock-names = "byte",
	3919	+ "byte_intf",
	3920	+ "pixel",
	3921	+ "core",
	3922	+ "iface",
	3923	+ "bus";
	3924	+ operating-points-v2 = <&dsi_opp_table>;
	3925	+ power-domains = <&rpmhpd SDM845_CX>;
	3926	+
	3927	+ phys = <&dsi0_phy>;
	3928	+ phy-names = "dsi";
	3929	+
	3930	+ status = "disabled";
	3931	+
	3932	+ ports {
	3933	+ #address-cells = <1>;
	3934	+ #size-cells = <0>;
	3935	+
	3936	+ port@0 {
	3937	+ reg = <0>;
	3938	+ dsi0_in: endpoint {
	3939	+ remote-endpoint = <&dpu_intf1_out>;
	3940	+ };
	3941	+ };
	3942	+
	3943	+ port@1 {
	3944	+ reg = <1>;
	3945	+ dsi0_out: endpoint {
	3946	+ };
	3947	+ };
	3948	+ };
	3949	+ };
	3950	+
	3951	+ dsi0_phy: dsi-phy@ae94400 {
	3952	+ compatible = "qcom,dsi-phy-10nm";
	3953	+ reg = <0 0x0ae94400 0 0x200>,
	3954	+ <0 0x0ae94600 0 0x280>,
	3955	+ <0 0x0ae94a00 0 0x1e0>;
	3956	+ reg-names = "dsi_phy",
	3957	+ "dsi_phy_lane",
	3958	+ "dsi_pll";
	3959	+
	3960	+ #clock-cells = <1>;
	3961	+ #phy-cells = <0>;
	3962	+
	3963	+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	3964	+ <&rpmhcc RPMH_CXO_CLK>;
	3965	+ clock-names = "iface", "ref";
	3966	+
	3967	+ status = "disabled";
	3968	+ };
	3969	+
	3970	+ dsi1: dsi@ae96000 {
	3971	+ compatible = "qcom,mdss-dsi-ctrl";
	3972	+ reg = <0 0x0ae96000 0 0x400>;
	3973	+ reg-names = "dsi_ctrl";
	3974	+
	3975	+ interrupt-parent = <&mdss>;
	3976	+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
	3977	+
	3978	+ clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
	3979	+ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
	3980	+ <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
	3981	+ <&dispcc DISP_CC_MDSS_ESC1_CLK>,
	3982	+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
	3983	+ <&dispcc DISP_CC_MDSS_AXI_CLK>;
	3984	+ clock-names = "byte",
	3985	+ "byte_intf",
	3986	+ "pixel",
	3987	+ "core",
	3988	+ "iface",
	3989	+ "bus";
	3990	+ operating-points-v2 = <&dsi_opp_table>;
	3991	+ power-domains = <&rpmhpd SDM845_CX>;
	3992	+
	3993	+ phys = <&dsi1_phy>;
	3994	+ phy-names = "dsi";
	3995	+
	3996	+ status = "disabled";
	3997	+
	3998	+ ports {
	3999	+ #address-cells = <1>;
	4000	+ #size-cells = <0>;
	4001	+
	4002	+ port@0 {
	4003	+ reg = <0>;
	4004	+ dsi1_in: endpoint {
	4005	+ remote-endpoint = <&dpu_intf2_out>;
	4006	+ };
	4007	+ };
	4008	+
	4009	+ port@1 {
	4010	+ reg = <1>;
	4011	+ dsi1_out: endpoint {
	4012	+ };
	4013	+ };
	4014	+ };
	4015	+ };
	4016	+
	4017	+ dsi1_phy: dsi-phy@ae96400 {
	4018	+ compatible = "qcom,dsi-phy-10nm";
	4019	+ reg = <0 0x0ae96400 0 0x200>,
	4020	+ <0 0x0ae96600 0 0x280>,
	4021	+ <0 0x0ae96a00 0 0x10e>;
	4022	+ reg-names = "dsi_phy",
	4023	+ "dsi_phy_lane",
	4024	+ "dsi_pll";
	4025	+
	4026	+ #clock-cells = <1>;
	4027	+ #phy-cells = <0>;
	4028	+
	4029	+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
	4030	+ <&rpmhcc RPMH_CXO_CLK>;
	4031	+ clock-names = "iface", "ref";
	4032	+
	4033	+ status = "disabled";
	4034	+ };
	4035	+ };
	4036	+
	4037	+ gpu: gpu@5000000 {
	4038	+ compatible = "qcom,adreno-630.2", "qcom,adreno";
	4039	+ #stream-id-cells = <16>;
	4040	+
	4041	+ reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
	4042	+ reg-names = "kgsl_3d0_reg_memory", "cx_mem";
	4043	+
	4044	+ /*
	4045	+ * Look ma, no clocks! The GPU clocks and power are
	4046	+ * controlled entirely by the GMU
	4047	+ */
	4048	+
	4049	+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
	4050	+
	4051	+ iommus = <&adreno_smmu 0>;
	4052	+
	4053	+ operating-points-v2 = <&gpu_opp_table>;
	4054	+
	4055	+ qcom,gmu = <&gmu>;
	4056	+
	4057	+ interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
	4058	+ interconnect-names = "gfx-mem";
	4059	+
	4060	+ gpu_opp_table: opp-table {
	4061	+ compatible = "operating-points-v2";
	4062	+
	4063	+ opp-710000000 {
	4064	+ opp-hz = /bits/ 64 <710000000>;
	4065	+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
	4066	+ opp-peak-kBps = <7216000>;
	4067	+ };
	4068	+
	4069	+ opp-675000000 {
	4070	+ opp-hz = /bits/ 64 <675000000>;
	4071	+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
	4072	+ opp-peak-kBps = <7216000>;
	4073	+ };
	4074	+
	4075	+ opp-596000000 {
	4076	+ opp-hz = /bits/ 64 <596000000>;
	4077	+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
	4078	+ opp-peak-kBps = <6220000>;
	4079	+ };
	4080	+
	4081	+ opp-520000000 {
	4082	+ opp-hz = /bits/ 64 <520000000>;
	4083	+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
	4084	+ opp-peak-kBps = <6220000>;
	4085	+ };
	4086	+
	4087	+ opp-414000000 {
	4088	+ opp-hz = /bits/ 64 <414000000>;
	4089	+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
	4090	+ opp-peak-kBps = <4068000>;
	4091	+ };
	4092	+
	4093	+ opp-342000000 {
	4094	+ opp-hz = /bits/ 64 <342000000>;
	4095	+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
	4096	+ opp-peak-kBps = <2724000>;
	4097	+ };
	4098	+
	4099	+ opp-257000000 {
	4100	+ opp-hz = /bits/ 64 <257000000>;
	4101	+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
	4102	+ opp-peak-kBps = <1648000>;
	4103	+ };
	4104	+ };
	4105	+ };
	4106	+
	4107	+ adreno_smmu: iommu@5040000 {
	4108	+ compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
	4109	+ reg = <0 0x5040000 0 0x10000>;
	4110	+ #iommu-cells = <1>;
	4111	+ #global-interrupts = <2>;
	4112	+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
	4113	+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
	4114	+ <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
	4115	+ <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
	4116	+ <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
	4117	+ <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
	4118	+ <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
	4119	+ <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
	4120	+ <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
	4121	+ <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
	4122	+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
	4123	+ <&gcc GCC_GPU_CFG_AHB_CLK>;
	4124	+ clock-names = "bus", "iface";
	4125	+
	4126	+ power-domains = <&gpucc GPU_CX_GDSC>;
	4127	+ };
	4128	+
	4129	+ gmu: gmu@506a000 {
	4130	+ compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
	4131	+
	4132	+ reg = <0 0x506a000 0 0x30000>,
	4133	+ <0 0xb280000 0 0x10000>,
	4134	+ <0 0xb480000 0 0x10000>;
	4135	+ reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
	4136	+
	4137	+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
	4138	+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
	4139	+ interrupt-names = "hfi", "gmu";
	4140	+
	4141	+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
	4142	+ <&gpucc GPU_CC_CXO_CLK>,
	4143	+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
	4144	+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
	4145	+ clock-names = "gmu", "cxo", "axi", "memnoc";
	4146	+
	4147	+ power-domains = <&gpucc GPU_CX_GDSC>,
	4148	+ <&gpucc GPU_GX_GDSC>;
	4149	+ power-domain-names = "cx", "gx";
	4150	+
	4151	+ iommus = <&adreno_smmu 5>;
	4152	+
	4153	+ operating-points-v2 = <&gmu_opp_table>;
	4154	+
	4155	+ gmu_opp_table: opp-table {
	4156	+ compatible = "operating-points-v2";
	4157	+
	4158	+ opp-400000000 {
	4159	+ opp-hz = /bits/ 64 <400000000>;
	4160	+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
	4161	+ };
	4162	+
	4163	+ opp-200000000 {
	4164	+ opp-hz = /bits/ 64 <200000000>;
	4165	+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
	4166	+ };
	4167	+ };
	4168	+ };
	4169	+
	4170	+ dispcc: clock-controller@af00000 {
	4171	+ compatible = "qcom,sdm845-dispcc";
	4172	+ reg = <0 0x0af00000 0 0x10000>;
	4173	+ clocks = <&rpmhcc RPMH_CXO_CLK>,
	4174	+ <&gcc GCC_DISP_GPLL0_CLK_SRC>,
	4175	+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
	4176	+ <&dsi0_phy 0>,
	4177	+ <&dsi0_phy 1>,
	4178	+ <&dsi1_phy 0>,
	4179	+ <&dsi1_phy 1>,
	4180	+ <0>,
	4181	+ <0>;
	4182	+ clock-names = "bi_tcxo",
	4183	+ "gcc_disp_gpll0_clk_src",
	4184	+ "gcc_disp_gpll0_div_clk_src",
	4185	+ "dsi0_phy_pll_out_byteclk",
	4186	+ "dsi0_phy_pll_out_dsiclk",
	4187	+ "dsi1_phy_pll_out_byteclk",
	4188	+ "dsi1_phy_pll_out_dsiclk",
	4189	+ "dp_link_clk_divsel_ten",
	4190	+ "dp_vco_divided_clk_src_mux";
	4191	+ #clock-cells = <1>;
	4192	+ #reset-cells = <1>;
	4193	+ #power-domain-cells = <1>;
	4194	+ };
	4195	+
	4196	+ pdc_intc: interrupt-controller@b220000 {
	4197	+ compatible = "qcom,sdm845-pdc", "qcom,pdc";
	4198	+ reg = <0 0x0b220000 0 0x30000>;
	4199	+ qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
	4200	+ #interrupt-cells = <2>;
	4201	+ interrupt-parent = <&intc>;
	4202	+ interrupt-controller;
	4203	+ };
	4204	+
	4205	+ pdc_reset: reset-controller@b2e0000 {
	4206	+ compatible = "qcom,sdm845-pdc-global";
	4207	+ reg = <0 0x0b2e0000 0 0x20000>;
	4208	+ #reset-cells = <1>;
963	4209	};
964	4210
965	4211	tsens0: thermal-sensor@c263000 {
966	4212	compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
967		- reg = <0xc263000 0x1ff>, /* TM */
968		- <0xc222000 0x1ff>; /* SROT */
	4213	+ reg = <0 0x0c263000 0 0x1ff>, /* TM */
	4214	+ <0 0x0c222000 0 0x1ff>; /* SROT */
969	4215	#qcom,sensors = <13>;
	4216	+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
	4217	+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
	4218	+ interrupt-names = "uplow", "critical";
970	4219	#thermal-sensor-cells = <1>;
971	4220	};
972	4221
973	4222	tsens1: thermal-sensor@c265000 {
974	4223	compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
975		- reg = <0xc265000 0x1ff>, /* TM */
976		- <0xc223000 0x1ff>; /* SROT */
	4224	+ reg = <0 0x0c265000 0 0x1ff>, /* TM */
	4225	+ <0 0x0c223000 0 0x1ff>; /* SROT */
977	4226	#qcom,sensors = <8>;
	4227	+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
	4228	+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
	4229	+ interrupt-names = "uplow", "critical";
978	4230	#thermal-sensor-cells = <1>;
	4231	+ };
	4232	+
	4233	+ aoss_reset: reset-controller@c2a0000 {
	4234	+ compatible = "qcom,sdm845-aoss-cc";
	4235	+ reg = <0 0x0c2a0000 0 0x31000>;
	4236	+ #reset-cells = <1>;
	4237	+ };
	4238	+
	4239	+ aoss_qmp: qmp@c300000 {
	4240	+ compatible = "qcom,sdm845-aoss-qmp";
	4241	+ reg = <0 0x0c300000 0 0x100000>;
	4242	+ interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
	4243	+ mboxes = <&apss_shared 0>;
	4244	+
	4245	+ #clock-cells = <0>;
	4246	+ #power-domain-cells = <1>;
	4247	+
	4248	+ cx_cdev: cx {
	4249	+ #cooling-cells = <2>;
	4250	+ };
	4251	+
	4252	+ ebi_cdev: ebi {
	4253	+ #cooling-cells = <2>;
	4254	+ };
979	4255	};
980	4256
981	4257	spmi_bus: spmi@c440000 {
982	4258	compatible = "qcom,spmi-pmic-arb";
983		- reg = <0xc440000 0x1100>,
984		- <0xc600000 0x2000000>,
985		- <0xe600000 0x100000>,
986		- <0xe700000 0xa0000>,
987		- <0xc40a000 0x26000>;
	4259	+ reg = <0 0x0c440000 0 0x1100>,
	4260	+ <0 0x0c600000 0 0x2000000>,
	4261	+ <0 0x0e600000 0 0x100000>,
	4262	+ <0 0x0e700000 0 0xa0000>,
	4263	+ <0 0x0c40a000 0 0x26000>;
988	4264	reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
989	4265	interrupt-names = "periph_irq";
990	4266	interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -997,18 +4273,126 @@
997	4273	cell-index = <0>;
998	4274	};
999	4275
	4276	+ imem@146bf000 {
	4277	+ compatible = "simple-mfd";
	4278	+ reg = <0 0x146bf000 0 0x1000>;
	4279	+
	4280	+ #address-cells = <1>;
	4281	+ #size-cells = <1>;
	4282	+
	4283	+ ranges = <0 0 0x146bf000 0x1000>;
	4284	+
	4285	+ pil-reloc@94c {
	4286	+ compatible = "qcom,pil-reloc-info";
	4287	+ reg = <0x94c 0xc8>;
	4288	+ };
	4289	+ };
	4290	+
	4291	+ apps_smmu: iommu@15000000 {
	4292	+ compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
	4293	+ reg = <0 0x15000000 0 0x80000>;
	4294	+ #iommu-cells = <2>;
	4295	+ #global-interrupts = <1>;
	4296	+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
	4297	+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
	4298	+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
	4299	+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
	4300	+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
	4301	+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
	4302	+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
	4303	+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
	4304	+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
	4305	+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	4306	+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	4307	+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	4308	+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	4309	+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	4310	+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	4311	+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	4312	+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
	4313	+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	4314	+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	4315	+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	4316	+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	4317	+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	4318	+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	4319	+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	4320	+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
	4321	+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
	4322	+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
	4323	+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
	4324	+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
	4325	+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
	4326	+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
	4327	+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
	4328	+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
	4329	+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
	4330	+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
	4331	+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
	4332	+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
	4333	+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
	4334	+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
	4335	+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
	4336	+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
	4337	+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	4338	+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	4339	+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	4340	+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	4341	+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	4342	+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
	4343	+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
	4344	+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
	4345	+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
	4346	+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
	4347	+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
	4348	+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
	4349	+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
	4350	+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
	4351	+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
	4352	+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
	4353	+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
	4354	+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
	4355	+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
	4356	+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
	4357	+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
	4358	+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
	4359	+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
	4360	+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
	4361	+ };
	4362	+
	4363	+ lpasscc: clock-controller@17014000 {
	4364	+ compatible = "qcom,sdm845-lpasscc";
	4365	+ reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
	4366	+ reg-names = "cc", "qdsp6ss";
	4367	+ #clock-cells = <1>;
	4368	+ status = "disabled";
	4369	+ };
	4370	+
	4371	+ gladiator_noc: interconnect@17900000 {
	4372	+ compatible = "qcom,sdm845-gladiator-noc";
	4373	+ reg = <0 0x17900000 0 0xd080>;
	4374	+ #interconnect-cells = <2>;
	4375	+ qcom,bcm-voters = <&apps_bcm_voter>;
	4376	+ };
	4377	+
	4378	+ watchdog@17980000 {
	4379	+ compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
	4380	+ reg = <0 0x17980000 0 0x1000>;
	4381	+ clocks = <&sleep_clk>;
	4382	+ };
	4383	+
1000	4384	apss_shared: mailbox@17990000 {
1001	4385	compatible = "qcom,sdm845-apss-shared";
1002		- reg = <0x17990000 0x1000>;
	4386	+ reg = <0 0x17990000 0 0x1000>;
1003	4387	#mbox-cells = <1>;
1004	4388	};
1005	4389
1006	4390	apps_rsc: rsc@179c0000 {
1007	4391	label = "apps_rsc";
1008	4392	compatible = "qcom,rpmh-rsc";
1009		- reg = <0x179c0000 0x10000>,
1010		- <0x179d0000 0x10000>,
1011		- <0x179e0000 0x10000>;
	4393	+ reg = <0 0x179c0000 0 0x10000>,
	4394	+ <0 0x179d0000 0 0x10000>,
	4395	+ <0 0x179e0000 0 0x10000>;
1012	4396	reg-names = "drv-0", "drv-1", "drv-2";
1013	4397	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1014	4398	<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
..	..	@@ -1020,88 +4404,760 @@
1020	4404	<WAKE_TCS 3>,
1021	4405	<CONTROL_TCS 1>;
1022	4406
	4407	+ apps_bcm_voter: bcm-voter {
	4408	+ compatible = "qcom,bcm-voter";
	4409	+ };
	4410	+
1023	4411	rpmhcc: clock-controller {
1024	4412	compatible = "qcom,sdm845-rpmh-clk";
1025	4413	#clock-cells = <1>;
	4414	+ clock-names = "xo";
	4415	+ clocks = <&xo_board>;
	4416	+ };
	4417	+
	4418	+ rpmhpd: power-controller {
	4419	+ compatible = "qcom,sdm845-rpmhpd";
	4420	+ #power-domain-cells = <1>;
	4421	+ operating-points-v2 = <&rpmhpd_opp_table>;
	4422	+
	4423	+ rpmhpd_opp_table: opp-table {
	4424	+ compatible = "operating-points-v2";
	4425	+
	4426	+ rpmhpd_opp_ret: opp1 {
	4427	+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
	4428	+ };
	4429	+
	4430	+ rpmhpd_opp_min_svs: opp2 {
	4431	+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
	4432	+ };
	4433	+
	4434	+ rpmhpd_opp_low_svs: opp3 {
	4435	+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
	4436	+ };
	4437	+
	4438	+ rpmhpd_opp_svs: opp4 {
	4439	+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
	4440	+ };
	4441	+
	4442	+ rpmhpd_opp_svs_l1: opp5 {
	4443	+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
	4444	+ };
	4445	+
	4446	+ rpmhpd_opp_nom: opp6 {
	4447	+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
	4448	+ };
	4449	+
	4450	+ rpmhpd_opp_nom_l1: opp7 {
	4451	+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
	4452	+ };
	4453	+
	4454	+ rpmhpd_opp_nom_l2: opp8 {
	4455	+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
	4456	+ };
	4457	+
	4458	+ rpmhpd_opp_turbo: opp9 {
	4459	+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
	4460	+ };
	4461	+
	4462	+ rpmhpd_opp_turbo_l1: opp10 {
	4463	+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
	4464	+ };
	4465	+ };
1026	4466	};
1027	4467	};
1028	4468
1029	4469	intc: interrupt-controller@17a00000 {
1030	4470	compatible = "arm,gic-v3";
1031		- #address-cells = <1>;
1032		- #size-cells = <1>;
	4471	+ #address-cells = <2>;
	4472	+ #size-cells = <2>;
1033	4473	ranges;
1034	4474	#interrupt-cells = <3>;
1035	4475	interrupt-controller;
1036		- reg = <0x17a00000 0x10000>, /* GICD */
1037		- <0x17a60000 0x100000>; /* GICR * 8 */
	4476	+ reg = <0 0x17a00000 0 0x10000>, /* GICD */
	4477	+ <0 0x17a60000 0 0x100000>; /* GICR * 8 */
1038	4478	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1039	4479
1040		- gic-its@17a40000 {
	4480	+ msi-controller@17a40000 {
1041	4481	compatible = "arm,gic-v3-its";
1042	4482	msi-controller;
1043	4483	#msi-cells = <1>;
1044		- reg = <0x17a40000 0x20000>;
	4484	+ reg = <0 0x17a40000 0 0x20000>;
1045	4485	status = "disabled";
1046	4486	};
1047	4487	};
1048	4488
	4489	+ slimbam: dma@17184000 {
	4490	+ compatible = "qcom,bam-v1.7.0";
	4491	+ qcom,controlled-remotely;
	4492	+ reg = <0 0x17184000 0 0x2a000>;
	4493	+ num-channels = <31>;
	4494	+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	4495	+ #dma-cells = <1>;
	4496	+ qcom,ee = <1>;
	4497	+ qcom,num-ees = <2>;
	4498	+ iommus = <&apps_smmu 0x1806 0x0>;
	4499	+ };
	4500	+
1049	4501	timer@17c90000 {
1050		- #address-cells = <1>;
1051		- #size-cells = <1>;
	4502	+ #address-cells = <2>;
	4503	+ #size-cells = <2>;
1052	4504	ranges;
1053	4505	compatible = "arm,armv7-timer-mem";
1054		- reg = <0x17c90000 0x1000>;
	4506	+ reg = <0 0x17c90000 0 0x1000>;
1055	4507
1056	4508	frame@17ca0000 {
1057	4509	frame-number = <0>;
1058	4510	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1059	4511	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1060		- reg = <0x17ca0000 0x1000>,
1061		- <0x17cb0000 0x1000>;
	4512	+ reg = <0 0x17ca0000 0 0x1000>,
	4513	+ <0 0x17cb0000 0 0x1000>;
1062	4514	};
1063	4515
1064	4516	frame@17cc0000 {
1065	4517	frame-number = <1>;
1066	4518	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1067		- reg = <0x17cc0000 0x1000>;
	4519	+ reg = <0 0x17cc0000 0 0x1000>;
1068	4520	status = "disabled";
1069	4521	};
1070	4522
1071	4523	frame@17cd0000 {
1072	4524	frame-number = <2>;
1073	4525	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1074		- reg = <0x17cd0000 0x1000>;
	4526	+ reg = <0 0x17cd0000 0 0x1000>;
1075	4527	status = "disabled";
1076	4528	};
1077	4529
1078	4530	frame@17ce0000 {
1079	4531	frame-number = <3>;
1080	4532	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1081		- reg = <0x17ce0000 0x1000>;
	4533	+ reg = <0 0x17ce0000 0 0x1000>;
1082	4534	status = "disabled";
1083	4535	};
1084	4536
1085	4537	frame@17cf0000 {
1086	4538	frame-number = <4>;
1087	4539	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1088		- reg = <0x17cf0000 0x1000>;
	4540	+ reg = <0 0x17cf0000 0 0x1000>;
1089	4541	status = "disabled";
1090	4542	};
1091	4543
1092	4544	frame@17d00000 {
1093	4545	frame-number = <5>;
1094	4546	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1095		- reg = <0x17d00000 0x1000>;
	4547	+ reg = <0 0x17d00000 0 0x1000>;
1096	4548	status = "disabled";
1097	4549	};
1098	4550
1099	4551	frame@17d10000 {
1100	4552	frame-number = <6>;
1101	4553	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1102		- reg = <0x17d10000 0x1000>;
	4554	+ reg = <0 0x17d10000 0 0x1000>;
1103	4555	status = "disabled";
1104	4556	};
1105	4557	};
	4558	+
	4559	+ osm_l3: interconnect@17d41000 {
	4560	+ compatible = "qcom,sdm845-osm-l3";
	4561	+ reg = <0 0x17d41000 0 0x1400>;
	4562	+
	4563	+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
	4564	+ clock-names = "xo", "alternate";
	4565	+
	4566	+ #interconnect-cells = <1>;
	4567	+ };
	4568	+
	4569	+ cpufreq_hw: cpufreq@17d43000 {
	4570	+ compatible = "qcom,cpufreq-hw";
	4571	+ reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
	4572	+ reg-names = "freq-domain0", "freq-domain1";
	4573	+
	4574	+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
	4575	+ clock-names = "xo", "alternate";
	4576	+
	4577	+ #freq-domain-cells = <1>;
	4578	+ };
	4579	+
	4580	+ wifi: wifi@18800000 {
	4581	+ compatible = "qcom,wcn3990-wifi";
	4582	+ status = "disabled";
	4583	+ reg = <0 0x18800000 0 0x800000>;
	4584	+ reg-names = "membase";
	4585	+ memory-region = <&wlan_msa_mem>;
	4586	+ clock-names = "cxo_ref_clk_pin";
	4587	+ clocks = <&rpmhcc RPMH_RF_CLK2>;
	4588	+ interrupts =
	4589	+ <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
	4590	+ <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
	4591	+ <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
	4592	+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
	4593	+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
	4594	+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
	4595	+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
	4596	+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
	4597	+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
	4598	+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
	4599	+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
	4600	+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
	4601	+ iommus = <&apps_smmu 0x0040 0x1>;
	4602	+ };
	4603	+ };
	4604	+
	4605	+ thermal-zones {
	4606	+ cpu0-thermal {
	4607	+ polling-delay-passive = <250>;
	4608	+ polling-delay = <1000>;
	4609	+
	4610	+ thermal-sensors = <&tsens0 1>;
	4611	+
	4612	+ trips {
	4613	+ cpu0_alert0: trip-point0 {
	4614	+ temperature = <90000>;
	4615	+ hysteresis = <2000>;
	4616	+ type = "passive";
	4617	+ };
	4618	+
	4619	+ cpu0_alert1: trip-point1 {
	4620	+ temperature = <95000>;
	4621	+ hysteresis = <2000>;
	4622	+ type = "passive";
	4623	+ };
	4624	+
	4625	+ cpu0_crit: cpu_crit {
	4626	+ temperature = <110000>;
	4627	+ hysteresis = <1000>;
	4628	+ type = "critical";
	4629	+ };
	4630	+ };
	4631	+
	4632	+ cooling-maps {
	4633	+ map0 {
	4634	+ trip = <&cpu0_alert0>;
	4635	+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4636	+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4637	+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4638	+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	4639	+ };
	4640	+ map1 {
	4641	+ trip = <&cpu0_alert1>;
	4642	+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4643	+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4644	+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4645	+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	4646	+ };
	4647	+ };
	4648	+ };
	4649	+
	4650	+ cpu1-thermal {
	4651	+ polling-delay-passive = <250>;
	4652	+ polling-delay = <1000>;
	4653	+
	4654	+ thermal-sensors = <&tsens0 2>;
	4655	+
	4656	+ trips {
	4657	+ cpu1_alert0: trip-point0 {
	4658	+ temperature = <90000>;
	4659	+ hysteresis = <2000>;
	4660	+ type = "passive";
	4661	+ };
	4662	+
	4663	+ cpu1_alert1: trip-point1 {
	4664	+ temperature = <95000>;
	4665	+ hysteresis = <2000>;
	4666	+ type = "passive";
	4667	+ };
	4668	+
	4669	+ cpu1_crit: cpu_crit {
	4670	+ temperature = <110000>;
	4671	+ hysteresis = <1000>;
	4672	+ type = "critical";
	4673	+ };
	4674	+ };
	4675	+
	4676	+ cooling-maps {
	4677	+ map0 {
	4678	+ trip = <&cpu1_alert0>;
	4679	+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4680	+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4681	+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4682	+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	4683	+ };
	4684	+ map1 {
	4685	+ trip = <&cpu1_alert1>;
	4686	+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4687	+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4688	+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4689	+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	4690	+ };
	4691	+ };
	4692	+ };
	4693	+
	4694	+ cpu2-thermal {
	4695	+ polling-delay-passive = <250>;
	4696	+ polling-delay = <1000>;
	4697	+
	4698	+ thermal-sensors = <&tsens0 3>;
	4699	+
	4700	+ trips {
	4701	+ cpu2_alert0: trip-point0 {
	4702	+ temperature = <90000>;
	4703	+ hysteresis = <2000>;
	4704	+ type = "passive";
	4705	+ };
	4706	+
	4707	+ cpu2_alert1: trip-point1 {
	4708	+ temperature = <95000>;
	4709	+ hysteresis = <2000>;
	4710	+ type = "passive";
	4711	+ };
	4712	+
	4713	+ cpu2_crit: cpu_crit {
	4714	+ temperature = <110000>;
	4715	+ hysteresis = <1000>;
	4716	+ type = "critical";
	4717	+ };
	4718	+ };
	4719	+
	4720	+ cooling-maps {
	4721	+ map0 {
	4722	+ trip = <&cpu2_alert0>;
	4723	+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4724	+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4725	+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4726	+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	4727	+ };
	4728	+ map1 {
	4729	+ trip = <&cpu2_alert1>;
	4730	+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4731	+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4732	+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4733	+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	4734	+ };
	4735	+ };
	4736	+ };
	4737	+
	4738	+ cpu3-thermal {
	4739	+ polling-delay-passive = <250>;
	4740	+ polling-delay = <1000>;
	4741	+
	4742	+ thermal-sensors = <&tsens0 4>;
	4743	+
	4744	+ trips {
	4745	+ cpu3_alert0: trip-point0 {
	4746	+ temperature = <90000>;
	4747	+ hysteresis = <2000>;
	4748	+ type = "passive";
	4749	+ };
	4750	+
	4751	+ cpu3_alert1: trip-point1 {
	4752	+ temperature = <95000>;
	4753	+ hysteresis = <2000>;
	4754	+ type = "passive";
	4755	+ };
	4756	+
	4757	+ cpu3_crit: cpu_crit {
	4758	+ temperature = <110000>;
	4759	+ hysteresis = <1000>;
	4760	+ type = "critical";
	4761	+ };
	4762	+ };
	4763	+
	4764	+ cooling-maps {
	4765	+ map0 {
	4766	+ trip = <&cpu3_alert0>;
	4767	+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4768	+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4769	+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4770	+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	4771	+ };
	4772	+ map1 {
	4773	+ trip = <&cpu3_alert1>;
	4774	+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4775	+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4776	+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4777	+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	4778	+ };
	4779	+ };
	4780	+ };
	4781	+
	4782	+ cpu4-thermal {
	4783	+ polling-delay-passive = <250>;
	4784	+ polling-delay = <1000>;
	4785	+
	4786	+ thermal-sensors = <&tsens0 7>;
	4787	+
	4788	+ trips {
	4789	+ cpu4_alert0: trip-point0 {
	4790	+ temperature = <90000>;
	4791	+ hysteresis = <2000>;
	4792	+ type = "passive";
	4793	+ };
	4794	+
	4795	+ cpu4_alert1: trip-point1 {
	4796	+ temperature = <95000>;
	4797	+ hysteresis = <2000>;
	4798	+ type = "passive";
	4799	+ };
	4800	+
	4801	+ cpu4_crit: cpu_crit {
	4802	+ temperature = <110000>;
	4803	+ hysteresis = <1000>;
	4804	+ type = "critical";
	4805	+ };
	4806	+ };
	4807	+
	4808	+ cooling-maps {
	4809	+ map0 {
	4810	+ trip = <&cpu4_alert0>;
	4811	+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4812	+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4813	+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4814	+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	4815	+ };
	4816	+ map1 {
	4817	+ trip = <&cpu4_alert1>;
	4818	+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4819	+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4820	+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4821	+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	4822	+ };
	4823	+ };
	4824	+ };
	4825	+
	4826	+ cpu5-thermal {
	4827	+ polling-delay-passive = <250>;
	4828	+ polling-delay = <1000>;
	4829	+
	4830	+ thermal-sensors = <&tsens0 8>;
	4831	+
	4832	+ trips {
	4833	+ cpu5_alert0: trip-point0 {
	4834	+ temperature = <90000>;
	4835	+ hysteresis = <2000>;
	4836	+ type = "passive";
	4837	+ };
	4838	+
	4839	+ cpu5_alert1: trip-point1 {
	4840	+ temperature = <95000>;
	4841	+ hysteresis = <2000>;
	4842	+ type = "passive";
	4843	+ };
	4844	+
	4845	+ cpu5_crit: cpu_crit {
	4846	+ temperature = <110000>;
	4847	+ hysteresis = <1000>;
	4848	+ type = "critical";
	4849	+ };
	4850	+ };
	4851	+
	4852	+ cooling-maps {
	4853	+ map0 {
	4854	+ trip = <&cpu5_alert0>;
	4855	+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4856	+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4857	+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4858	+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	4859	+ };
	4860	+ map1 {
	4861	+ trip = <&cpu5_alert1>;
	4862	+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4863	+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4864	+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4865	+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	4866	+ };
	4867	+ };
	4868	+ };
	4869	+
	4870	+ cpu6-thermal {
	4871	+ polling-delay-passive = <250>;
	4872	+ polling-delay = <1000>;
	4873	+
	4874	+ thermal-sensors = <&tsens0 9>;
	4875	+
	4876	+ trips {
	4877	+ cpu6_alert0: trip-point0 {
	4878	+ temperature = <90000>;
	4879	+ hysteresis = <2000>;
	4880	+ type = "passive";
	4881	+ };
	4882	+
	4883	+ cpu6_alert1: trip-point1 {
	4884	+ temperature = <95000>;
	4885	+ hysteresis = <2000>;
	4886	+ type = "passive";
	4887	+ };
	4888	+
	4889	+ cpu6_crit: cpu_crit {
	4890	+ temperature = <110000>;
	4891	+ hysteresis = <1000>;
	4892	+ type = "critical";
	4893	+ };
	4894	+ };
	4895	+
	4896	+ cooling-maps {
	4897	+ map0 {
	4898	+ trip = <&cpu6_alert0>;
	4899	+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4900	+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4901	+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4902	+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	4903	+ };
	4904	+ map1 {
	4905	+ trip = <&cpu6_alert1>;
	4906	+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4907	+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4908	+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4909	+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	4910	+ };
	4911	+ };
	4912	+ };
	4913	+
	4914	+ cpu7-thermal {
	4915	+ polling-delay-passive = <250>;
	4916	+ polling-delay = <1000>;
	4917	+
	4918	+ thermal-sensors = <&tsens0 10>;
	4919	+
	4920	+ trips {
	4921	+ cpu7_alert0: trip-point0 {
	4922	+ temperature = <90000>;
	4923	+ hysteresis = <2000>;
	4924	+ type = "passive";
	4925	+ };
	4926	+
	4927	+ cpu7_alert1: trip-point1 {
	4928	+ temperature = <95000>;
	4929	+ hysteresis = <2000>;
	4930	+ type = "passive";
	4931	+ };
	4932	+
	4933	+ cpu7_crit: cpu_crit {
	4934	+ temperature = <110000>;
	4935	+ hysteresis = <1000>;
	4936	+ type = "critical";
	4937	+ };
	4938	+ };
	4939	+
	4940	+ cooling-maps {
	4941	+ map0 {
	4942	+ trip = <&cpu7_alert0>;
	4943	+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4944	+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4945	+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4946	+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	4947	+ };
	4948	+ map1 {
	4949	+ trip = <&cpu7_alert1>;
	4950	+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4951	+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4952	+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	4953	+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	4954	+ };
	4955	+ };
	4956	+ };
	4957	+
	4958	+ aoss0-thermal {
	4959	+ polling-delay-passive = <250>;
	4960	+ polling-delay = <1000>;
	4961	+
	4962	+ thermal-sensors = <&tsens0 0>;
	4963	+
	4964	+ trips {
	4965	+ aoss0_alert0: trip-point0 {
	4966	+ temperature = <90000>;
	4967	+ hysteresis = <2000>;
	4968	+ type = "hot";
	4969	+ };
	4970	+ };
	4971	+ };
	4972	+
	4973	+ cluster0-thermal {
	4974	+ polling-delay-passive = <250>;
	4975	+ polling-delay = <1000>;
	4976	+
	4977	+ thermal-sensors = <&tsens0 5>;
	4978	+
	4979	+ trips {
	4980	+ cluster0_alert0: trip-point0 {
	4981	+ temperature = <90000>;
	4982	+ hysteresis = <2000>;
	4983	+ type = "hot";
	4984	+ };
	4985	+ cluster0_crit: cluster0_crit {
	4986	+ temperature = <110000>;
	4987	+ hysteresis = <2000>;
	4988	+ type = "critical";
	4989	+ };
	4990	+ };
	4991	+ };
	4992	+
	4993	+ cluster1-thermal {
	4994	+ polling-delay-passive = <250>;
	4995	+ polling-delay = <1000>;
	4996	+
	4997	+ thermal-sensors = <&tsens0 6>;
	4998	+
	4999	+ trips {
	5000	+ cluster1_alert0: trip-point0 {
	5001	+ temperature = <90000>;
	5002	+ hysteresis = <2000>;
	5003	+ type = "hot";
	5004	+ };
	5005	+ cluster1_crit: cluster1_crit {
	5006	+ temperature = <110000>;
	5007	+ hysteresis = <2000>;
	5008	+ type = "critical";
	5009	+ };
	5010	+ };
	5011	+ };
	5012	+
	5013	+ gpu-thermal-top {
	5014	+ polling-delay-passive = <250>;
	5015	+ polling-delay = <1000>;
	5016	+
	5017	+ thermal-sensors = <&tsens0 11>;
	5018	+
	5019	+ trips {
	5020	+ gpu1_alert0: trip-point0 {
	5021	+ temperature = <90000>;
	5022	+ hysteresis = <2000>;
	5023	+ type = "hot";
	5024	+ };
	5025	+ };
	5026	+ };
	5027	+
	5028	+ gpu-thermal-bottom {
	5029	+ polling-delay-passive = <250>;
	5030	+ polling-delay = <1000>;
	5031	+
	5032	+ thermal-sensors = <&tsens0 12>;
	5033	+
	5034	+ trips {
	5035	+ gpu2_alert0: trip-point0 {
	5036	+ temperature = <90000>;
	5037	+ hysteresis = <2000>;
	5038	+ type = "hot";
	5039	+ };
	5040	+ };
	5041	+ };
	5042	+
	5043	+ aoss1-thermal {
	5044	+ polling-delay-passive = <250>;
	5045	+ polling-delay = <1000>;
	5046	+
	5047	+ thermal-sensors = <&tsens1 0>;
	5048	+
	5049	+ trips {
	5050	+ aoss1_alert0: trip-point0 {
	5051	+ temperature = <90000>;
	5052	+ hysteresis = <2000>;
	5053	+ type = "hot";
	5054	+ };
	5055	+ };
	5056	+ };
	5057	+
	5058	+ q6-modem-thermal {
	5059	+ polling-delay-passive = <250>;
	5060	+ polling-delay = <1000>;
	5061	+
	5062	+ thermal-sensors = <&tsens1 1>;
	5063	+
	5064	+ trips {
	5065	+ q6_modem_alert0: trip-point0 {
	5066	+ temperature = <90000>;
	5067	+ hysteresis = <2000>;
	5068	+ type = "hot";
	5069	+ };
	5070	+ };
	5071	+ };
	5072	+
	5073	+ mem-thermal {
	5074	+ polling-delay-passive = <250>;
	5075	+ polling-delay = <1000>;
	5076	+
	5077	+ thermal-sensors = <&tsens1 2>;
	5078	+
	5079	+ trips {
	5080	+ mem_alert0: trip-point0 {
	5081	+ temperature = <90000>;
	5082	+ hysteresis = <2000>;
	5083	+ type = "hot";
	5084	+ };
	5085	+ };
	5086	+ };
	5087	+
	5088	+ wlan-thermal {
	5089	+ polling-delay-passive = <250>;
	5090	+ polling-delay = <1000>;
	5091	+
	5092	+ thermal-sensors = <&tsens1 3>;
	5093	+
	5094	+ trips {
	5095	+ wlan_alert0: trip-point0 {
	5096	+ temperature = <90000>;
	5097	+ hysteresis = <2000>;
	5098	+ type = "hot";
	5099	+ };
	5100	+ };
	5101	+ };
	5102	+
	5103	+ q6-hvx-thermal {
	5104	+ polling-delay-passive = <250>;
	5105	+ polling-delay = <1000>;
	5106	+
	5107	+ thermal-sensors = <&tsens1 4>;
	5108	+
	5109	+ trips {
	5110	+ q6_hvx_alert0: trip-point0 {
	5111	+ temperature = <90000>;
	5112	+ hysteresis = <2000>;
	5113	+ type = "hot";
	5114	+ };
	5115	+ };
	5116	+ };
	5117	+
	5118	+ camera-thermal {
	5119	+ polling-delay-passive = <250>;
	5120	+ polling-delay = <1000>;
	5121	+
	5122	+ thermal-sensors = <&tsens1 5>;
	5123	+
	5124	+ trips {
	5125	+ camera_alert0: trip-point0 {
	5126	+ temperature = <90000>;
	5127	+ hysteresis = <2000>;
	5128	+ type = "hot";
	5129	+ };
	5130	+ };
	5131	+ };
	5132	+
	5133	+ video-thermal {
	5134	+ polling-delay-passive = <250>;
	5135	+ polling-delay = <1000>;
	5136	+
	5137	+ thermal-sensors = <&tsens1 6>;
	5138	+
	5139	+ trips {
	5140	+ video_alert0: trip-point0 {
	5141	+ temperature = <90000>;
	5142	+ hysteresis = <2000>;
	5143	+ type = "hot";
	5144	+ };
	5145	+ };
	5146	+ };
	5147	+
	5148	+ modem-thermal {
	5149	+ polling-delay-passive = <250>;
	5150	+ polling-delay = <1000>;
	5151	+
	5152	+ thermal-sensors = <&tsens1 7>;
	5153	+
	5154	+ trips {
	5155	+ modem_alert0: trip-point0 {
	5156	+ temperature = <90000>;
	5157	+ hysteresis = <2000>;
	5158	+ type = "hot";
	5159	+ };
	5160	+ };
	5161	+ };
1106	5162	};
1107	5163	};