.. | .. |
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775 | 775 | |
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776 | 776 | clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; |
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777 | 777 | resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, |
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778 | | - <&gcc 21>; |
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| 778 | + <&gcc GCC_PCIE_0_PIPE_ARES>; |
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779 | 779 | reset-names = "phy", "pipe"; |
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780 | 780 | |
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781 | 781 | clock-output-names = "pcie_0_pipe_clk"; |
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.. | .. |
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1305 | 1305 | <&gcc GCC_PCIE_0_SLV_AXI_CLK>; |
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1306 | 1306 | clock-names = "iface", "aux", "master_bus", "slave_bus"; |
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1307 | 1307 | |
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1308 | | - resets = <&gcc 18>, |
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1309 | | - <&gcc 17>, |
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1310 | | - <&gcc 15>, |
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1311 | | - <&gcc 19>, |
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| 1308 | + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, |
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| 1309 | + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, |
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| 1310 | + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, |
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| 1311 | + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, |
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1312 | 1312 | <&gcc GCC_PCIE_0_BCR>, |
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1313 | | - <&gcc 16>; |
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| 1313 | + <&gcc GCC_PCIE_0_AHB_ARES>; |
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1314 | 1314 | reset-names = "axi_m", |
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1315 | 1315 | "axi_s", |
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1316 | 1316 | "axi_m_sticky", |
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