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2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/arch/arm64/boot/dts/qcom/msm8992.dtsi
....@@ -1,23 +1,11 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
2
- *
3
- * This program is free software; you can redistribute it and/or modify
4
- * it under the terms of the GNU General Public License version 2 and
5
- * only version 2 as published by the Free Software Foundation.
6
- *
7
- * This program is distributed in the hope that it will be useful,
8
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
9
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10
- * GNU General Public License for more details.
113  */
124 
135 #include <dt-bindings/interrupt-controller/arm-gic.h>
146 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
157 
168 / {
17
-	model = "Qualcomm Technologies, Inc. MSM 8992";
18
-	compatible = "qcom,msm8992";
19
-	// msm-id needed by bootloader for selecting correct blob
20
-	qcom,msm-id = <251 0>, <252 0>;
219 	interrupt-parent = <&intc>;
2210 
2311 	#address-cells = <2>;
....@@ -28,55 +16,139 @@
2816 	cpus {
2917 		#address-cells = <2>;
3018 		#size-cells = <0>;
31
-		cpu-map {
32
-			cluster0 {
33
-				core0 {
34
-					cpu = <&CPU0>;
35
-				};
36
-			};
37
-		};
3819 
3920 		CPU0: cpu@0 {
4021 			device_type = "cpu";
41
-			compatible = "arm,cortex-a53", "arm,armv8";
22
+			compatible = "arm,cortex-a53";
4223 			reg = <0x0 0x0>;
4324 			next-level-cache = <&L2_0>;
25
+			enable-method = "psci";
4426 			L2_0: l2-cache {
4527 				compatible = "cache";
4628 				cache-level = <2>;
4729 			};
4830 		};
31
+
32
+		CPU1: cpu@1 {
33
+			device_type = "cpu";
34
+			compatible = "arm,cortex-a53";
35
+			reg = <0x0 0x1>;
36
+			next-level-cache = <&L2_0>;
37
+			enable-method = "psci";
38
+		};
39
+
40
+		CPU2: cpu@2 {
41
+			device_type = "cpu";
42
+			compatible = "arm,cortex-a53";
43
+			reg = <0x0 0x2>;
44
+			next-level-cache = <&L2_0>;
45
+			enable-method = "psci";
46
+		};
47
+
48
+		CPU3: cpu@3 {
49
+			device_type = "cpu";
50
+			compatible = "arm,cortex-a53";
51
+			reg = <0x0 0x3>;
52
+			next-level-cache = <&L2_0>;
53
+			enable-method = "psci";
54
+		};
55
+
56
+		CPU4: cpu@100 {
57
+			device_type = "cpu";
58
+			compatible = "arm,cortex-a57";
59
+			reg = <0x0 0x100>;
60
+			next-level-cache = <&L2_1>;
61
+			enable-method = "psci";
62
+			L2_1: l2-cache {
63
+				compatible = "cache";
64
+				cache-level = <2>;
65
+			};
66
+		};
67
+
68
+		CPU5: cpu@101 {
69
+			device_type = "cpu";
70
+			compatible = "arm,cortex-a57";
71
+			reg = <0x0 0x101>;
72
+			next-level-cache = <&L2_1>;
73
+			enable-method = "psci";
74
+		};
75
+
76
+		cpu-map {
77
+			cluster0 {
78
+				core0 {
79
+					cpu = <&CPU0>;
80
+				};
81
+
82
+				core1 {
83
+					cpu = <&CPU1>;
84
+				};
85
+
86
+				core2 {
87
+					cpu = <&CPU2>;
88
+				};
89
+
90
+				core3 {
91
+					cpu = <&CPU3>;
92
+				};
93
+			};
94
+
95
+			cluster1 {
96
+				core0 {
97
+					cpu = <&CPU4>;
98
+				};
99
+
100
+				core1 {
101
+					cpu = <&CPU5>;
102
+				};
103
+			};
104
+		};
49105 	};
50106 
51
-	timer {
52
-		compatible = "arm,armv8-timer";
53
-		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
54
-			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
55
-			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
56
-			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
107
+	clocks {
108
+		xo_board: xo_board {
109
+			compatible = "fixed-clock";
110
+			#clock-cells = <0>;
111
+			clock-frequency = <19200000>;
112
+		};
113
+
114
+		sleep_clk: sleep_clk {
115
+			compatible = "fixed-clock";
116
+			#clock-cells = <0>;
117
+			clock-frequency = <32768>;
118
+		};
57119 	};
58120 
59
-	xo_board: xo_board {
60
-		compatible = "fixed-clock";
61
-		#clock-cells = <0>;
62
-		clock-frequency = <19200000>;
121
+	firmware {
122
+		scm {
123
+			compatible = "qcom,scm-msm8994", "qcom,scm";
124
+		};
63125 	};
64126 
65
-	sleep_clk: sleep_clk {
66
-		compatible = "fixed-clock";
67
-		#clock-cells = <0>;
68
-		clock-frequency = <32768>;
127
+	memory {
128
+		device_type = "memory";
129
+		/* We expect the bootloader to fill in the reg */
130
+		reg = <0 0 0 0>;
69131 	};
70132 
71
-	vreg_vph_pwr: vreg-vph-pwr {
72
-		compatible = "regulator-fixed";
73
-		status = "okay";
74
-		regulator-name = "vph-pwr";
133
+	pmu {
134
+		compatible = "arm,cortex-a53-pmu";
135
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
136
+	};
75137 
76
-		regulator-min-microvolt = <3600000>;
77
-		regulator-max-microvolt = <3600000>;
138
+	psci {
139
+		compatible = "arm,psci-0.2";
140
+		method = "hvc";
141
+	};
78142 
79
-		regulator-always-on;
143
+	reserved-memory {
144
+		#address-cells = <2>;
145
+		#size-cells = <2>;
146
+		ranges;
147
+
148
+		smem_region: smem@6a00000 {
149
+			reg = <0x0 0x6a00000 0x0 0x200000>;
150
+			no-map;
151
+		};
80152 	};
81153 
82154 	sfpb_mutex: hwmutex {
....@@ -106,9 +178,10 @@
106178 				<0xf9002000 0x1000>;
107179 		};
108180 
109
-		apcs: syscon@f900d000 {
110
-			compatible = "syscon";
181
+		apcs: mailbox@f900d000 {
182
+			compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
111183 			reg = <0xf900d000 0x2000>;
184
+			#mbox-cells = <1>;
112185 		};
113186 
114187 		timer@f9020000 {
....@@ -169,51 +242,19 @@
169242 			};
170243 		};
171244 
172
-		restart@fc4ab000 {
173
-			compatible = "qcom,pshold";
174
-			reg = <0xfc4ab000 0x4>;
175
-		};
176
-
177
-		msmgpio: pinctrl@fd510000 {
178
-			compatible = "qcom,msm8994-pinctrl";
179
-			reg = <0xfd510000 0x4000>;
180
-			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
181
-			gpio-controller;
182
-			#gpio-cells = <2>;
183
-			interrupt-controller;
184
-			#interrupt-cells = <2>;
185
-		};
186
-
187
-		blsp1_uart2: serial@f991e000 {
188
-			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
189
-			reg = <0xf991e000 0x1000>;
190
-			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
191
-			status = "disabled";
192
-			clock-names = "core", "iface";
193
-			clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
194
-				<&clock_gcc GCC_BLSP1_AHB_CLK>;
195
-		};
196
-
197
-		clock_gcc: clock-controller@fc400000 {
198
-			compatible = "qcom,gcc-msm8994";
199
-			#clock-cells = <1>;
200
-			#reset-cells = <1>;
201
-			#power-domain-cells = <1>;
202
-			reg = <0xfc400000 0x2000>;
203
-		};
204
-
205
-		sdhci1: mmc@f9824900 {
245
+		sdhc_1: sdhci@f9824900 {
206246 			compatible = "qcom,sdhci-msm-v4";
207247 			reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
208248 			reg-names = "hc_mem", "core_mem";
209249 
210
-			interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>,
211
-					<GIC_SPI 138 IRQ_TYPE_NONE>;
250
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
251
+					<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
212252 			interrupt-names = "hc_irq", "pwr_irq";
213253 
214
-			clocks = <&clock_gcc GCC_SDCC1_APPS_CLK>,
215
-				<&clock_gcc GCC_SDCC1_AHB_CLK>;
216
-			clock-names = "core", "iface";
254
+			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
255
+				<&gcc GCC_SDCC1_AHB_CLK>,
256
+				<&xo_board>;
257
+			clock-names = "core", "iface", "xo";
217258 
218259 			pinctrl-names = "default", "sleep";
219260 			pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
....@@ -223,13 +264,151 @@
223264 
224265 			regulator-always-on;
225266 			bus-width = <8>;
226
-			mmc-hs400-1_8v;
227
-			status = "okay";
267
+			non-removable;
268
+
269
+			status = "disabled";
270
+		};
271
+
272
+		blsp1_uart2: serial@f991e000 {
273
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
274
+			reg = <0xf991e000 0x1000>;
275
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
276
+			clock-names = "core", "iface";
277
+			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
278
+				<&gcc GCC_BLSP1_AHB_CLK>;
279
+			pinctrl-names = "default", "sleep";
280
+			pinctrl-0 = <&blsp1_uart2_default>;
281
+			pinctrl-1 = <&blsp1_uart2_sleep>;
282
+			status = "disabled";
283
+		};
284
+
285
+		blsp_i2c2: i2c@f9924000 {
286
+			compatible = "qcom,i2c-qup-v2.2.1";
287
+			reg = <0xf9924000 0x500>;
288
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
289
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
290
+				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
291
+			clock-names = "iface", "core";
292
+			clock-frequency = <400000>;
293
+			pinctrl-names = "default", "sleep";
294
+			pinctrl-0 = <&i2c2_default>;
295
+			pinctrl-1 = <&i2c2_sleep>;
296
+			#address-cells = <1>;
297
+			#size-cells = <0>;
298
+			status = "disabled";
299
+		};
300
+
301
+		/* Somebody was very creative with their numbering scheme downstream... */
302
+
303
+		blsp_i2c13: i2c@f9927000 {
304
+			compatible = "qcom,i2c-qup-v2.2.1";
305
+			reg = <0xf9927000 0x500>;
306
+			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
307
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
308
+				<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
309
+			clock-names = "iface", "core";
310
+			clock-frequency = <400000>;
311
+			pinctrl-names = "default", "sleep";
312
+			pinctrl-0 = <&i2c13_default>;
313
+			pinctrl-1 = <&i2c13_sleep>;
314
+			#address-cells = <1>;
315
+			#size-cells = <0>;
316
+			status = "disabled";
317
+		};
318
+
319
+		blsp_i2c6: i2c@f9928000 {
320
+			compatible = "qcom,i2c-qup-v2.2.1";
321
+			reg = <0xf9928000 0x500>;
322
+			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
323
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
324
+				<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
325
+			clock-names = "iface", "core";
326
+			clock-frequency = <400000>;
327
+			pinctrl-names = "default", "sleep";
328
+			pinctrl-0 = <&i2c6_default>;
329
+			pinctrl-1 = <&i2c6_sleep>;
330
+			#address-cells = <1>;
331
+			#size-cells = <0>;
332
+			status = "disabled";
333
+		};
334
+
335
+		blsp2_uart2: serial@f995e000 {
336
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
337
+			reg = <0xf995e000 0x1000>;
338
+			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>;
339
+			clock-names = "core", "iface";
340
+			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
341
+				<&gcc GCC_BLSP2_AHB_CLK>;
342
+			pinctrl-names = "default", "sleep";
343
+			pinctrl-0 = <&blsp2_uart2_default>;
344
+			pinctrl-1 = <&blsp2_uart2_sleep>;
345
+			status = "disabled";
346
+		};
347
+
348
+		blsp_i2c7: i2c@f9963000 {
349
+			compatible = "qcom,i2c-qup-v2.2.1";
350
+			reg = <0xf9963000 0x500>;
351
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
352
+			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
353
+				<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
354
+			clock-names = "iface", "core";
355
+			clock-frequency = <400000>;
356
+			pinctrl-names = "default", "sleep";
357
+			pinctrl-0 = <&i2c7_default>;
358
+			pinctrl-1 = <&i2c7_sleep>;
359
+			#address-cells = <1>;
360
+			#size-cells = <0>;
361
+			status = "disabled";
362
+		};
363
+
364
+		blsp_i2c5: i2c@f9967000 {
365
+			compatible = "qcom,i2c-qup-v2.2.1";
366
+			reg = <0xf9967000 0x500>;
367
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
368
+			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
369
+				<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
370
+			clock-names = "iface", "core";
371
+			clock-frequency = <100000>;
372
+			pinctrl-names = "default", "sleep";
373
+			pinctrl-0 = <&i2c5_default>;
374
+			pinctrl-1 = <&i2c5_sleep>;
375
+			#address-cells = <1>;
376
+			#size-cells = <0>;
377
+			status = "disabled";
378
+		};
379
+
380
+		gcc: clock-controller@fc400000 {
381
+			compatible = "qcom,gcc-msm8994";
382
+			#clock-cells = <1>;
383
+			#reset-cells = <1>;
384
+			#power-domain-cells = <1>;
385
+			reg = <0xfc400000 0x2000>;
228386 		};
229387 
230388 		rpm_msg_ram: memory@fc428000 {
231389 			compatible = "qcom,rpm-msg-ram";
232390 			reg = <0xfc428000 0x4000>;
391
+		};
392
+
393
+		restart@fc4ab000 {
394
+			compatible = "qcom,pshold";
395
+			reg = <0xfc4ab000 0x4>;
396
+		};
397
+
398
+		spmi_bus: spmi@fc4c0000 {
399
+			compatible = "qcom,spmi-pmic-arb";
400
+			reg = <0xfc4cf000 0x1000>,
401
+			      <0xfc4cb000 0x1000>,
402
+			      <0xfc4ca000 0x1000>;
403
+			reg-names = "core", "intr", "cnfg";
404
+			interrupt-names = "periph_irq";
405
+			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
406
+			qcom,ee = <0>;
407
+			qcom,channel = <0>;
408
+			#address-cells = <2>;
409
+			#size-cells = <0>;
410
+			interrupt-controller;
411
+			#interrupt-cells = <4>;
233412 		};
234413 
235414 		sfpb_mutex_regs: syscon@fd484000 {
....@@ -238,21 +417,162 @@
238417 			compatible = "syscon";
239418 			reg = <0xfd484000 0x400>;
240419 		};
241
-	};
242420 
243
-	memory {
244
-		device_type = "memory";
245
-		reg = <0 0 0 0>; // bootloader will update
246
-	};
421
+		tlmm: pinctrl@fd510000 {
422
+			compatible = "qcom,msm8994-pinctrl";
423
+			reg = <0xfd510000 0x4000>;
424
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
425
+			gpio-controller;
426
+			gpio-ranges = <&tlmm 0 0 146>;
427
+			#gpio-cells = <2>;
428
+			interrupt-controller;
429
+			#interrupt-cells = <2>;
247430 
248
-	reserved-memory {
249
-		#address-cells = <2>;
250
-		#size-cells = <2>;
251
-		ranges;
431
+			blsp1_uart2_default: blsp1-uart2-default {
432
+				function = "blsp_uart2";
433
+				pins = "gpio4", "gpio5";
434
+				drive-strength = <16>;
435
+				bias-disable;
436
+			};
252437 
253
-		smem_region: smem@6a00000 {
254
-			reg = <0x0 0x6a00000 0x0 0x200000>;
255
-			no-map;
438
+			blsp1_uart2_sleep: blsp1-uart2-sleep {
439
+				function = "gpio";
440
+				pins = "gpio4", "gpio5";
441
+				drive-strength = <2>;
442
+				bias-pull-down;
443
+			};
444
+
445
+			blsp2_uart2_default: blsp2-uart2-default {
446
+				function = "blsp_uart8";
447
+				pins = "gpio45", "gpio46", "gpio47", "gpio48";
448
+				drive-strength = <16>;
449
+				bias-disable;
450
+			};
451
+
452
+			blsp2_uart2_sleep: blsp2-uart2-sleep {
453
+				function = "gpio";
454
+				pins = "gpio45", "gpio46", "gpio47", "gpio48";
455
+				drive-strength = <2>;
456
+				bias-pull-down;
457
+			};
458
+
459
+			sdc1_clk_on: clk-on {
460
+				pins = "sdc1_clk";
461
+				bias-disable;
462
+				drive-strength = <6>;
463
+			};
464
+
465
+			sdc1_clk_off: clk-off {
466
+				pins = "sdc1_clk";
467
+				bias-disable;
468
+				drive-strength = <2>;
469
+			};
470
+
471
+			sdc1_cmd_on: cmd-on {
472
+				pins = "sdc1_cmd";
473
+				bias-pull-up;
474
+				drive-strength = <6>;
475
+			};
476
+
477
+			sdc1_cmd_off: cmd-off {
478
+				pins = "sdc1_cmd";
479
+				bias-pull-up;
480
+				drive-strength = <2>;
481
+			};
482
+
483
+			sdc1_data_on: data-on {
484
+				pins = "sdc1_data";
485
+				bias-pull-up;
486
+				drive-strength = <6>;
487
+			};
488
+
489
+			sdc1_data_off: data-off {
490
+				pins = "sdc1_data";
491
+				bias-pull-up;
492
+				drive-strength = <2>;
493
+			};
494
+
495
+			sdc1_rclk_on: rclk-on {
496
+				pins = "sdc1_rclk";
497
+				bias-pull-down;
498
+			};
499
+
500
+			sdc1_rclk_off: rclk-off {
501
+				pins = "sdc1_rclk";
502
+				bias-pull-down;
503
+			};
504
+
505
+			i2c2_default: i2c2-default {
506
+				function = "blsp_i2c2";
507
+				pins = "gpio6", "gpio7";
508
+				drive-strength = <2>;
509
+				bias-disable;
510
+			};
511
+
512
+			i2c2_sleep: i2c2-sleep {
513
+				function = "gpio";
514
+				pins = "gpio6", "gpio7";
515
+				drive-strength = <2>;
516
+				bias-disable;
517
+			};
518
+
519
+			i2c5_default: i2c5-default {
520
+				/* Don't be fooled! Nobody knows the reason why though... */
521
+				function = "blsp_i2c11";
522
+				pins = "gpio83", "gpio84";
523
+				drive-strength = <2>;
524
+				bias-disable;
525
+			};
526
+
527
+			i2c5_sleep: i2c5-sleep {
528
+				function = "gpio";
529
+				pins = "gpio83", "gpio84";
530
+				drive-strength = <2>;
531
+				bias-disable;
532
+			};
533
+
534
+			i2c6_default: i2c6-default {
535
+				function = "blsp_i2c6";
536
+				pins = "gpio28", "gpio27";
537
+				drive-strength = <2>;
538
+				bias-disable;
539
+			};
540
+
541
+			i2c6_sleep: i2c6-sleep {
542
+				function = "gpio";
543
+				pins = "gpio28", "gpio27";
544
+				drive-strength = <2>;
545
+				bias-disable;
546
+			};
547
+
548
+			i2c7_default: i2c7-default {
549
+				function = "blsp_i2c7";
550
+				pins = "gpio43", "gpio44";
551
+				drive-strength = <2>;
552
+				bias-disable;
553
+			};
554
+
555
+			i2c7_sleep: i2c7-sleep {
556
+				function = "gpio";
557
+				pins = "gpio43", "gpio44";
558
+				drive-strength = <2>;
559
+				bias-disable;
560
+			};
561
+
562
+			i2c13_default: i2c13-default {
563
+				/* Not a typo either. */
564
+				function = "blsp_i2c5";
565
+				pins = "gpio23", "gpio24";
566
+				drive-strength = <2>;
567
+				bias-disable;
568
+			};
569
+
570
+			i2c13_sleep: i2c13-sleep {
571
+				function = "gpio";
572
+				pins = "gpio23", "gpio24";
573
+				drive-strength = <2>;
574
+				bias-disable;
575
+			};
256576 		};
257577 	};
258578 
....@@ -265,58 +585,35 @@
265585 			qcom,local-pid = <0>;
266586 			qcom,remote-pid = <6>;
267587 
268
-			rpm-requests {
588
+			rpm_requests: rpm-requests {
269589 				compatible = "qcom,rpm-msm8994";
270590 				qcom,smd-channels = "rpm_requests";
271591 
272
-				pm8994-regulators {
273
-					compatible = "qcom,rpm-pm8994-regulators";
274
-
275
-					pm8994_s1: s1 {};
276
-					pm8994_s2: s2 {};
277
-					pm8994_s3: s3 {};
278
-					pm8994_s4: s4 {};
279
-					pm8994_s5: s5 {};
280
-					pm8994_s6: s6 {};
281
-					pm8994_s7: s7 {};
282
-
283
-					pm8994_l1: l1 {};
284
-					pm8994_l2: l2 {};
285
-					pm8994_l3: l3 {};
286
-					pm8994_l4: l4 {};
287
-					pm8994_l6: l6 {};
288
-					pm8994_l8: l8 {};
289
-					pm8994_l9: l9 {};
290
-					pm8994_l10: l10 {};
291
-					pm8994_l11: l11 {};
292
-					pm8994_l12: l12 {};
293
-					pm8994_l13: l13 {};
294
-					pm8994_l14: l14 {};
295
-					pm8994_l15: l15 {};
296
-					pm8994_l16: l16 {};
297
-					pm8994_l17: l17 {};
298
-					pm8994_l18: l18 {};
299
-					pm8994_l19: l19 {};
300
-					pm8994_l20: l20 {};
301
-					pm8994_l21: l21 {};
302
-					pm8994_l22: l22 {};
303
-					pm8994_l23: l23 {};
304
-					pm8994_l24: l24 {};
305
-					pm8994_l25: l25 {};
306
-					pm8994_l26: l26 {};
307
-					pm8994_l27: l27 {};
308
-					pm8994_l28: l28 {};
309
-					pm8994_l29: l29 {};
310
-					pm8994_l30: l30 {};
311
-					pm8994_l31: l31 {};
312
-					pm8994_l32: l32 {};
313
-
314
-					pm8994_lvs1: lvs1 {};
315
-					pm8994_lvs2: lvs2 {};
592
+				rpmcc: rpmcc {
593
+					compatible = "qcom,rpmcc-msm8992";
594
+					#clock-cells = <1>;
316595 				};
317596 			};
318597 		};
319598 	};
599
+
600
+	timer {
601
+		compatible = "arm,armv8-timer";
602
+		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
603
+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
604
+			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
605
+			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
606
+	};
607
+
608
+	vreg_vph_pwr: vreg-vph-pwr {
609
+		compatible = "regulator-fixed";
610
+		status = "okay";
611
+		regulator-name = "vph-pwr";
612
+
613
+		regulator-min-microvolt = <3600000>;
614
+		regulator-max-microvolt = <3600000>;
615
+
616
+		regulator-always-on;
617
+	};
320618 };
321619 
322
-#include "msm8992-pins.dtsi"