forked from ~ljy/RK356X_SDK_RELEASE
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2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/arch/arm64/boot/dts/nvidia/tegra186.dtsi
....@@ -4,6 +4,7 @@
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
55 #include <dt-bindings/mailbox/tegra186-hsp.h>
66 #include <dt-bindings/memory/tegra186-mc.h>
7
+#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
78 #include <dt-bindings/power/tegra186-powergate.h>
89 #include <dt-bindings/reset/tegra186-reset.h>
910 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
....@@ -59,6 +60,10 @@
5960 		clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
6061 		resets = <&bpmp TEGRA186_RESET_EQOS>;
6162 		reset-names = "eqos";
63
+		interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>,
64
+				<&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>;
65
+		interconnect-names = "dma-mem", "write";
66
+		iommus = <&smmu TEGRA186_SID_EQOS>;
6267 		status = "disabled";
6368 
6469 		snps,write-requests = <1>;
....@@ -68,10 +73,319 @@
6873 		snps,rxpbl = <8>;
6974 	};
7075 
71
-	memory-controller@2c00000 {
76
+	aconnect {
77
+		compatible = "nvidia,tegra186-aconnect",
78
+			     "nvidia,tegra210-aconnect";
79
+		clocks = <&bpmp TEGRA186_CLK_APE>,
80
+			 <&bpmp TEGRA186_CLK_APB2APE>;
81
+		clock-names = "ape", "apb2ape";
82
+		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
83
+		#address-cells = <1>;
84
+		#size-cells = <1>;
85
+		ranges = <0x02900000 0x0 0x02900000 0x200000>;
86
+		status = "disabled";
87
+
88
+		adma: dma-controller@2930000 {
89
+			compatible = "nvidia,tegra186-adma";
90
+			reg = <0x02930000 0x20000>;
91
+			interrupt-parent = <&agic>;
92
+			interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
93
+				      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
94
+				      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
95
+				      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
96
+				      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
97
+				      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
98
+				      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
99
+				      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
100
+				      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
101
+				      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
102
+				      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
103
+				      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
104
+				      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
105
+				      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
106
+				      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
107
+				      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
108
+				      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
109
+				      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
110
+				      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
111
+				      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
112
+				      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
113
+				      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
114
+				      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
115
+				      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
116
+				      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
117
+				      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
118
+				      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
119
+				      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
120
+				      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
121
+				      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
122
+				      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
123
+				      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
124
+			#dma-cells = <1>;
125
+			clocks = <&bpmp TEGRA186_CLK_AHUB>;
126
+			clock-names = "d_audio";
127
+			status = "disabled";
128
+		};
129
+
130
+		agic: interrupt-controller@2a40000 {
131
+			compatible = "nvidia,tegra186-agic",
132
+				     "nvidia,tegra210-agic";
133
+			#interrupt-cells = <3>;
134
+			interrupt-controller;
135
+			reg = <0x02a41000 0x1000>,
136
+			      <0x02a42000 0x2000>;
137
+			interrupts = <GIC_SPI 145
138
+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
139
+			clocks = <&bpmp TEGRA186_CLK_APE>;
140
+			clock-names = "clk";
141
+			status = "disabled";
142
+		};
143
+
144
+		tegra_ahub: ahub@2900800 {
145
+			compatible = "nvidia,tegra186-ahub";
146
+			reg = <0x02900800 0x800>;
147
+			clocks = <&bpmp TEGRA186_CLK_AHUB>;
148
+			clock-names = "ahub";
149
+			assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
150
+			assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
151
+			#address-cells = <1>;
152
+			#size-cells = <1>;
153
+			ranges = <0x02900800 0x02900800 0x11800>;
154
+			status = "disabled";
155
+
156
+			tegra_admaif: admaif@290f000 {
157
+				compatible = "nvidia,tegra186-admaif";
158
+				reg = <0x0290f000 0x1000>;
159
+				dmas = <&adma 1>, <&adma 1>,
160
+				       <&adma 2>, <&adma 2>,
161
+				       <&adma 3>, <&adma 3>,
162
+				       <&adma 4>, <&adma 4>,
163
+				       <&adma 5>, <&adma 5>,
164
+				       <&adma 6>, <&adma 6>,
165
+				       <&adma 7>, <&adma 7>,
166
+				       <&adma 8>, <&adma 8>,
167
+				       <&adma 9>, <&adma 9>,
168
+				       <&adma 10>, <&adma 10>,
169
+				       <&adma 11>, <&adma 11>,
170
+				       <&adma 12>, <&adma 12>,
171
+				       <&adma 13>, <&adma 13>,
172
+				       <&adma 14>, <&adma 14>,
173
+				       <&adma 15>, <&adma 15>,
174
+				       <&adma 16>, <&adma 16>,
175
+				       <&adma 17>, <&adma 17>,
176
+				       <&adma 18>, <&adma 18>,
177
+				       <&adma 19>, <&adma 19>,
178
+				       <&adma 20>, <&adma 20>;
179
+				dma-names = "rx1", "tx1",
180
+					    "rx2", "tx2",
181
+					    "rx3", "tx3",
182
+					    "rx4", "tx4",
183
+					    "rx5", "tx5",
184
+					    "rx6", "tx6",
185
+					    "rx7", "tx7",
186
+					    "rx8", "tx8",
187
+					    "rx9", "tx9",
188
+					    "rx10", "tx10",
189
+					    "rx11", "tx11",
190
+					    "rx12", "tx12",
191
+					    "rx13", "tx13",
192
+					    "rx14", "tx14",
193
+					    "rx15", "tx15",
194
+					    "rx16", "tx16",
195
+					    "rx17", "tx17",
196
+					    "rx18", "tx18",
197
+					    "rx19", "tx19",
198
+					    "rx20", "tx20";
199
+				status = "disabled";
200
+			};
201
+
202
+			tegra_i2s1: i2s@2901000 {
203
+				compatible = "nvidia,tegra186-i2s",
204
+					     "nvidia,tegra210-i2s";
205
+				reg = <0x2901000 0x100>;
206
+				clocks = <&bpmp TEGRA186_CLK_I2S1>,
207
+					 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
208
+				clock-names = "i2s", "sync_input";
209
+				assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
210
+				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
211
+				assigned-clock-rates = <1536000>;
212
+				sound-name-prefix = "I2S1";
213
+				status = "disabled";
214
+			};
215
+
216
+			tegra_i2s2: i2s@2901100 {
217
+				compatible = "nvidia,tegra186-i2s",
218
+					     "nvidia,tegra210-i2s";
219
+				reg = <0x2901100 0x100>;
220
+				clocks = <&bpmp TEGRA186_CLK_I2S2>,
221
+					 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
222
+				clock-names = "i2s", "sync_input";
223
+				assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
224
+				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
225
+				assigned-clock-rates = <1536000>;
226
+				sound-name-prefix = "I2S2";
227
+				status = "disabled";
228
+			};
229
+
230
+			tegra_i2s3: i2s@2901200 {
231
+				compatible = "nvidia,tegra186-i2s",
232
+					     "nvidia,tegra210-i2s";
233
+				reg = <0x2901200 0x100>;
234
+				clocks = <&bpmp TEGRA186_CLK_I2S3>,
235
+					 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
236
+				clock-names = "i2s", "sync_input";
237
+				assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
238
+				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
239
+				assigned-clock-rates = <1536000>;
240
+				sound-name-prefix = "I2S3";
241
+				status = "disabled";
242
+			};
243
+
244
+			tegra_i2s4: i2s@2901300 {
245
+				compatible = "nvidia,tegra186-i2s",
246
+					     "nvidia,tegra210-i2s";
247
+				reg = <0x2901300 0x100>;
248
+				clocks = <&bpmp TEGRA186_CLK_I2S4>,
249
+					 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
250
+				clock-names = "i2s", "sync_input";
251
+				assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
252
+				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
253
+				assigned-clock-rates = <1536000>;
254
+				sound-name-prefix = "I2S4";
255
+				status = "disabled";
256
+			};
257
+
258
+			tegra_i2s5: i2s@2901400 {
259
+				compatible = "nvidia,tegra186-i2s",
260
+					     "nvidia,tegra210-i2s";
261
+				reg = <0x2901400 0x100>;
262
+				clocks = <&bpmp TEGRA186_CLK_I2S5>,
263
+					 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
264
+				clock-names = "i2s", "sync_input";
265
+				assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
266
+				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
267
+				assigned-clock-rates = <1536000>;
268
+				sound-name-prefix = "I2S5";
269
+				status = "disabled";
270
+			};
271
+
272
+			tegra_i2s6: i2s@2901500 {
273
+				compatible = "nvidia,tegra186-i2s",
274
+					     "nvidia,tegra210-i2s";
275
+				reg = <0x2901500 0x100>;
276
+				clocks = <&bpmp TEGRA186_CLK_I2S6>,
277
+					 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
278
+				clock-names = "i2s", "sync_input";
279
+				assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
280
+				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
281
+				assigned-clock-rates = <1536000>;
282
+				sound-name-prefix = "I2S6";
283
+				status = "disabled";
284
+			};
285
+
286
+			tegra_dmic1: dmic@2904000 {
287
+				compatible = "nvidia,tegra210-dmic";
288
+				reg = <0x2904000 0x100>;
289
+				clocks = <&bpmp TEGRA186_CLK_DMIC1>;
290
+				clock-names = "dmic";
291
+				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
292
+				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
293
+				assigned-clock-rates = <3072000>;
294
+				sound-name-prefix = "DMIC1";
295
+				status = "disabled";
296
+			};
297
+
298
+			tegra_dmic2: dmic@2904100 {
299
+				compatible = "nvidia,tegra210-dmic";
300
+				reg = <0x2904100 0x100>;
301
+				clocks = <&bpmp TEGRA186_CLK_DMIC2>;
302
+				clock-names = "dmic";
303
+				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
304
+				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
305
+				assigned-clock-rates = <3072000>;
306
+				sound-name-prefix = "DMIC2";
307
+				status = "disabled";
308
+			};
309
+
310
+			tegra_dmic3: dmic@2904200 {
311
+				compatible = "nvidia,tegra210-dmic";
312
+				reg = <0x2904200 0x100>;
313
+				clocks = <&bpmp TEGRA186_CLK_DMIC3>;
314
+				clock-names = "dmic";
315
+				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
316
+				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
317
+				assigned-clock-rates = <3072000>;
318
+				sound-name-prefix = "DMIC3";
319
+				status = "disabled";
320
+			};
321
+
322
+			tegra_dmic4: dmic@2904300 {
323
+				compatible = "nvidia,tegra210-dmic";
324
+				reg = <0x2904300 0x100>;
325
+				clocks = <&bpmp TEGRA186_CLK_DMIC4>;
326
+				clock-names = "dmic";
327
+				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
328
+				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
329
+				assigned-clock-rates = <3072000>;
330
+				sound-name-prefix = "DMIC4";
331
+				status = "disabled";
332
+			};
333
+
334
+			tegra_dspk1: dspk@2905000 {
335
+				compatible = "nvidia,tegra186-dspk";
336
+				reg = <0x2905000 0x100>;
337
+				clocks = <&bpmp TEGRA186_CLK_DSPK1>;
338
+				clock-names = "dspk";
339
+				assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
340
+				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
341
+				assigned-clock-rates = <12288000>;
342
+				sound-name-prefix = "DSPK1";
343
+				status = "disabled";
344
+			};
345
+
346
+			tegra_dspk2: dspk@2905100 {
347
+				compatible = "nvidia,tegra186-dspk";
348
+				reg = <0x2905100 0x100>;
349
+				clocks = <&bpmp TEGRA186_CLK_DSPK2>;
350
+				clock-names = "dspk";
351
+				assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
352
+				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
353
+				assigned-clock-rates = <12288000>;
354
+				sound-name-prefix = "DSPK2";
355
+				status = "disabled";
356
+			};
357
+		};
358
+	};
359
+
360
+	mc: memory-controller@2c00000 {
72361 		compatible = "nvidia,tegra186-mc";
73362 		reg = <0x0 0x02c00000 0x0 0xb0000>;
363
+		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
74364 		status = "disabled";
365
+
366
+		#interconnect-cells = <1>;
367
+		#address-cells = <2>;
368
+		#size-cells = <2>;
369
+
370
+		ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
371
+
372
+		/*
373
+		 * Memory clients have access to all 40 bits that the memory
374
+		 * controller can address.
375
+		 */
376
+		dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
377
+
378
+		emc: external-memory-controller@2c60000 {
379
+			compatible = "nvidia,tegra186-emc";
380
+			reg = <0x0 0x02c60000 0x0 0x50000>;
381
+			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
382
+			clocks = <&bpmp TEGRA186_CLK_EMC>;
383
+			clock-names = "emc";
384
+
385
+			#interconnect-cells = <0>;
386
+
387
+			nvidia,bpmp = <&bpmp>;
388
+		};
75389 	};
76390 
77391 	uarta: serial@3100000 {
....@@ -135,7 +449,7 @@
135449 	};
136450 
137451 	gen1_i2c: i2c@3160000 {
138
-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
452
+		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
139453 		reg = <0x0 0x03160000 0x0 0x10000>;
140454 		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
141455 		#address-cells = <1>;
....@@ -148,7 +462,7 @@
148462 	};
149463 
150464 	cam_i2c: i2c@3180000 {
151
-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
465
+		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
152466 		reg = <0x0 0x03180000 0x0 0x10000>;
153467 		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
154468 		#address-cells = <1>;
....@@ -162,7 +476,7 @@
162476 
163477 	/* shares pads with dpaux1 */
164478 	dp_aux_ch1_i2c: i2c@3190000 {
165
-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
479
+		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
166480 		reg = <0x0 0x03190000 0x0 0x10000>;
167481 		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
168482 		#address-cells = <1>;
....@@ -171,12 +485,15 @@
171485 		clock-names = "div-clk";
172486 		resets = <&bpmp TEGRA186_RESET_I2C4>;
173487 		reset-names = "i2c";
488
+		pinctrl-names = "default", "idle";
489
+		pinctrl-0 = <&state_dpaux1_i2c>;
490
+		pinctrl-1 = <&state_dpaux1_off>;
174491 		status = "disabled";
175492 	};
176493 
177494 	/* controlled by BPMP, should not be enabled */
178495 	pwr_i2c: i2c@31a0000 {
179
-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
496
+		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
180497 		reg = <0x0 0x031a0000 0x0 0x10000>;
181498 		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
182499 		#address-cells = <1>;
....@@ -190,7 +507,7 @@
190507 
191508 	/* shares pads with dpaux0 */
192509 	dp_aux_ch0_i2c: i2c@31b0000 {
193
-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
510
+		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
194511 		reg = <0x0 0x031b0000 0x0 0x10000>;
195512 		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
196513 		#address-cells = <1>;
....@@ -199,11 +516,14 @@
199516 		clock-names = "div-clk";
200517 		resets = <&bpmp TEGRA186_RESET_I2C6>;
201518 		reset-names = "i2c";
519
+		pinctrl-names = "default", "idle";
520
+		pinctrl-0 = <&state_dpaux_i2c>;
521
+		pinctrl-1 = <&state_dpaux_off>;
202522 		status = "disabled";
203523 	};
204524 
205525 	gen7_i2c: i2c@31c0000 {
206
-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
526
+		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
207527 		reg = <0x0 0x031c0000 0x0 0x10000>;
208528 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
209529 		#address-cells = <1>;
....@@ -216,7 +536,7 @@
216536 	};
217537 
218538 	gen9_i2c: i2c@31e0000 {
219
-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
539
+		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
220540 		reg = <0x0 0x031e0000 0x0 0x10000>;
221541 		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
222542 		#address-cells = <1>;
....@@ -228,47 +548,288 @@
228548 		status = "disabled";
229549 	};
230550 
231
-	sdmmc1: sdhci@3400000 {
551
+	sdmmc1: mmc@3400000 {
232552 		compatible = "nvidia,tegra186-sdhci";
233553 		reg = <0x0 0x03400000 0x0 0x10000>;
234554 		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
235
-		clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
236
-		clock-names = "sdhci";
555
+		clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
556
+			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
557
+		clock-names = "sdhci", "tmclk";
237558 		resets = <&bpmp TEGRA186_RESET_SDMMC1>;
238559 		reset-names = "sdhci";
560
+		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
561
+				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
562
+		interconnect-names = "dma-mem", "write";
563
+		iommus = <&smmu TEGRA186_SID_SDMMC1>;
564
+		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
565
+		pinctrl-0 = <&sdmmc1_3v3>;
566
+		pinctrl-1 = <&sdmmc1_1v8>;
567
+		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
568
+		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
569
+		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
570
+		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
571
+		nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
572
+		nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
573
+		nvidia,default-tap = <0x5>;
574
+		nvidia,default-trim = <0xb>;
575
+		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
576
+				  <&bpmp TEGRA186_CLK_PLLP_OUT0>;
577
+		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
239578 		status = "disabled";
240579 	};
241580 
242
-	sdmmc2: sdhci@3420000 {
581
+	sdmmc2: mmc@3420000 {
243582 		compatible = "nvidia,tegra186-sdhci";
244583 		reg = <0x0 0x03420000 0x0 0x10000>;
245584 		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
246
-		clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
247
-		clock-names = "sdhci";
585
+		clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
586
+			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
587
+		clock-names = "sdhci", "tmclk";
248588 		resets = <&bpmp TEGRA186_RESET_SDMMC2>;
249589 		reset-names = "sdhci";
590
+		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
591
+				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>;
592
+		interconnect-names = "dma-mem", "write";
593
+		iommus = <&smmu TEGRA186_SID_SDMMC2>;
594
+		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
595
+		pinctrl-0 = <&sdmmc2_3v3>;
596
+		pinctrl-1 = <&sdmmc2_1v8>;
597
+		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
598
+		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
599
+		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
600
+		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
601
+		nvidia,default-tap = <0x5>;
602
+		nvidia,default-trim = <0xb>;
250603 		status = "disabled";
251604 	};
252605 
253
-	sdmmc3: sdhci@3440000 {
606
+	sdmmc3: mmc@3440000 {
254607 		compatible = "nvidia,tegra186-sdhci";
255608 		reg = <0x0 0x03440000 0x0 0x10000>;
256609 		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
257
-		clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
258
-		clock-names = "sdhci";
610
+		clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
611
+			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
612
+		clock-names = "sdhci", "tmclk";
259613 		resets = <&bpmp TEGRA186_RESET_SDMMC3>;
260614 		reset-names = "sdhci";
615
+		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
616
+				<&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>;
617
+		interconnect-names = "dma-mem", "write";
618
+		iommus = <&smmu TEGRA186_SID_SDMMC3>;
619
+		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
620
+		pinctrl-0 = <&sdmmc3_3v3>;
621
+		pinctrl-1 = <&sdmmc3_1v8>;
622
+		nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
623
+		nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
624
+		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
625
+		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
626
+		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
627
+		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
628
+		nvidia,default-tap = <0x5>;
629
+		nvidia,default-trim = <0xb>;
261630 		status = "disabled";
262631 	};
263632 
264
-	sdmmc4: sdhci@3460000 {
633
+	sdmmc4: mmc@3460000 {
265634 		compatible = "nvidia,tegra186-sdhci";
266635 		reg = <0x0 0x03460000 0x0 0x10000>;
267636 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
268
-		clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
269
-		clock-names = "sdhci";
637
+		clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
638
+			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
639
+		clock-names = "sdhci", "tmclk";
640
+		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
641
+				  <&bpmp TEGRA186_CLK_PLLC4_VCO>;
642
+		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
270643 		resets = <&bpmp TEGRA186_RESET_SDMMC4>;
271644 		reset-names = "sdhci";
645
+		interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>,
646
+				<&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>;
647
+		interconnect-names = "dma-mem", "write";
648
+		iommus = <&smmu TEGRA186_SID_SDMMC4>;
649
+		nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
650
+		nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
651
+		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
652
+		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
653
+		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
654
+		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
655
+		nvidia,default-tap = <0x9>;
656
+		nvidia,default-trim = <0x5>;
657
+		nvidia,dqs-trim = <63>;
658
+		mmc-hs400-1_8v;
659
+		supports-cqe;
660
+		status = "disabled";
661
+	};
662
+
663
+	hda@3510000 {
664
+		compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
665
+		reg = <0x0 0x03510000 0x0 0x10000>;
666
+		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
667
+		clocks = <&bpmp TEGRA186_CLK_HDA>,
668
+			 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
669
+			 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
670
+		clock-names = "hda", "hda2hdmi", "hda2codec_2x";
671
+		resets = <&bpmp TEGRA186_RESET_HDA>,
672
+			 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
673
+			 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
674
+		reset-names = "hda", "hda2hdmi", "hda2codec_2x";
675
+		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
676
+		interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>,
677
+				<&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>;
678
+		interconnect-names = "dma-mem", "write";
679
+		iommus = <&smmu TEGRA186_SID_HDA>;
680
+		status = "disabled";
681
+	};
682
+
683
+	padctl: padctl@3520000 {
684
+		compatible = "nvidia,tegra186-xusb-padctl";
685
+		reg = <0x0 0x03520000 0x0 0x1000>,
686
+		      <0x0 0x03540000 0x0 0x1000>;
687
+		reg-names = "padctl", "ao";
688
+
689
+		resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
690
+		reset-names = "padctl";
691
+
692
+		status = "disabled";
693
+
694
+		pads {
695
+			usb2 {
696
+				clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
697
+				clock-names = "trk";
698
+				status = "disabled";
699
+
700
+				lanes {
701
+					usb2-0 {
702
+						status = "disabled";
703
+						#phy-cells = <0>;
704
+					};
705
+
706
+					usb2-1 {
707
+						status = "disabled";
708
+						#phy-cells = <0>;
709
+					};
710
+
711
+					usb2-2 {
712
+						status = "disabled";
713
+						#phy-cells = <0>;
714
+					};
715
+				};
716
+			};
717
+
718
+			hsic {
719
+				clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
720
+				clock-names = "trk";
721
+				status = "disabled";
722
+
723
+				lanes {
724
+					hsic-0 {
725
+						status = "disabled";
726
+						#phy-cells = <0>;
727
+					};
728
+				};
729
+			};
730
+
731
+			usb3 {
732
+				status = "disabled";
733
+
734
+				lanes {
735
+					usb3-0 {
736
+						status = "disabled";
737
+						#phy-cells = <0>;
738
+					};
739
+
740
+					usb3-1 {
741
+						status = "disabled";
742
+						#phy-cells = <0>;
743
+					};
744
+
745
+					usb3-2 {
746
+						status = "disabled";
747
+						#phy-cells = <0>;
748
+					};
749
+				};
750
+			};
751
+		};
752
+
753
+		ports {
754
+			usb2-0 {
755
+				status = "disabled";
756
+			};
757
+
758
+			usb2-1 {
759
+				status = "disabled";
760
+			};
761
+
762
+			usb2-2 {
763
+				status = "disabled";
764
+			};
765
+
766
+			hsic-0 {
767
+				status = "disabled";
768
+			};
769
+
770
+			usb3-0 {
771
+				status = "disabled";
772
+			};
773
+
774
+			usb3-1 {
775
+				status = "disabled";
776
+			};
777
+
778
+			usb3-2 {
779
+				status = "disabled";
780
+			};
781
+		};
782
+	};
783
+
784
+	usb@3530000 {
785
+		compatible = "nvidia,tegra186-xusb";
786
+		reg = <0x0 0x03530000 0x0 0x8000>,
787
+		      <0x0 0x03538000 0x0 0x1000>;
788
+		reg-names = "hcd", "fpci";
789
+		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
790
+			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
791
+		clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
792
+			 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
793
+			 <&bpmp TEGRA186_CLK_XUSB_SS>,
794
+			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
795
+			 <&bpmp TEGRA186_CLK_CLK_M>,
796
+			 <&bpmp TEGRA186_CLK_XUSB_FS>,
797
+			 <&bpmp TEGRA186_CLK_PLLU>,
798
+			 <&bpmp TEGRA186_CLK_CLK_M>,
799
+			 <&bpmp TEGRA186_CLK_PLLE>;
800
+		clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
801
+			      "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
802
+			      "pll_u_480m", "clk_m", "pll_e";
803
+		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
804
+				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
805
+		power-domain-names = "xusb_host", "xusb_ss";
806
+		interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
807
+				<&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
808
+		interconnect-names = "dma-mem", "write";
809
+		iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
810
+		#address-cells = <1>;
811
+		#size-cells = <0>;
812
+		status = "disabled";
813
+
814
+		nvidia,xusb-padctl = <&padctl>;
815
+	};
816
+
817
+	usb@3550000 {
818
+		compatible = "nvidia,tegra186-xudc";
819
+		reg = <0x0 0x03550000 0x0 0x8000>,
820
+		      <0x0 0x03558000 0x0 0x1000>;
821
+		reg-names = "base", "fpci";
822
+		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
823
+		clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
824
+			 <&bpmp TEGRA186_CLK_XUSB_SS>,
825
+			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
826
+			 <&bpmp TEGRA186_CLK_XUSB_FS>;
827
+		clock-names = "dev", "ss", "ss_src", "fs_src";
828
+		iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
829
+		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
830
+				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
831
+		power-domain-names = "dev", "ss";
832
+		nvidia,xusb-padctl = <&padctl>;
272833 		status = "disabled";
273834 	};
274835 
....@@ -290,6 +851,15 @@
290851 		interrupt-parent = <&gic>;
291852 	};
292853 
854
+	cec@3960000 {
855
+		compatible = "nvidia,tegra186-cec";
856
+		reg = <0x0 0x03960000 0x0 0x10000>;
857
+		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
858
+		clocks = <&bpmp TEGRA186_CLK_CEC>;
859
+		clock-names = "cec";
860
+		status = "disabled";
861
+	};
862
+
293863 	hsp_top0: hsp@3c00000 {
294864 		compatible = "nvidia,tegra186-hsp";
295865 		reg = <0x0 0x03c00000 0x0 0xa0000>;
....@@ -300,7 +870,7 @@
300870 	};
301871 
302872 	gen2_i2c: i2c@c240000 {
303
-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
873
+		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
304874 		reg = <0x0 0x0c240000 0x0 0x10000>;
305875 		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
306876 		#address-cells = <1>;
....@@ -313,7 +883,7 @@
313883 	};
314884 
315885 	gen8_i2c: i2c@c250000 {
316
-		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
886
+		compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
317887 		reg = <0x0 0x0c250000 0x0 0x10000>;
318888 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
319889 		#address-cells = <1>;
....@@ -349,6 +919,16 @@
349919 		status = "disabled";
350920 	};
351921 
922
+	rtc: rtc@c2a0000 {
923
+		compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
924
+		reg = <0 0x0c2a0000 0 0x10000>;
925
+		interrupt-parent = <&pmc>;
926
+		interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
927
+		clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
928
+		clock-names = "rtc";
929
+		status = "disabled";
930
+	};
931
+
352932 	gpio_aon: gpio@c2f0000 {
353933 		compatible = "nvidia,tegra186-gpio-aon";
354934 		reg-names = "security", "gpio";
....@@ -361,13 +941,46 @@
361941 		#interrupt-cells = <2>;
362942 	};
363943 
364
-	pmc@c360000 {
944
+	pmc: pmc@c360000 {
365945 		compatible = "nvidia,tegra186-pmc";
366946 		reg = <0 0x0c360000 0 0x10000>,
367947 		      <0 0x0c370000 0 0x10000>,
368948 		      <0 0x0c380000 0 0x10000>,
369949 		      <0 0x0c390000 0 0x10000>;
370950 		reg-names = "pmc", "wake", "aotag", "scratch";
951
+
952
+		#interrupt-cells = <2>;
953
+		interrupt-controller;
954
+
955
+		sdmmc1_3v3: sdmmc1-3v3 {
956
+			pins = "sdmmc1-hv";
957
+			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
958
+		};
959
+
960
+		sdmmc1_1v8: sdmmc1-1v8 {
961
+			pins = "sdmmc1-hv";
962
+			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
963
+		};
964
+
965
+		sdmmc2_3v3: sdmmc2-3v3 {
966
+			pins = "sdmmc2-hv";
967
+			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
968
+		};
969
+
970
+		sdmmc2_1v8: sdmmc2-1v8 {
971
+			pins = "sdmmc2-hv";
972
+			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
973
+		};
974
+
975
+		sdmmc3_3v3: sdmmc3-3v3 {
976
+			pins = "sdmmc3-hv";
977
+			power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
978
+		};
979
+
980
+		sdmmc3_1v8: sdmmc3-1v8 {
981
+			pins = "sdmmc3-hv";
982
+			power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
983
+		};
371984 	};
372985 
373986 	ccplex@e000000 {
....@@ -381,9 +994,9 @@
381994 		compatible = "nvidia,tegra186-pcie";
382995 		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
383996 		device_type = "pci";
384
-		reg = <0x0 0x10003000 0x0 0x00000800   /* PADS registers */
385
-		       0x0 0x10003800 0x0 0x00000800   /* AFI registers */
386
-		       0x0 0x40000000 0x0 0x10000000>; /* configuration space */
997
+		reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */
998
+		      <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */
999
+		      <0x0 0x40000000 0x0 0x10000000>; /* configuration space */
3871000 		reg-names = "pads", "afi", "cs";
3881001 
3891002 		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
....@@ -398,22 +1011,30 @@
3981011 		#address-cells = <3>;
3991012 		#size-cells = <2>;
4001013 
401
-		ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000   /* port 0 configuration space */
402
-			  0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000   /* port 1 configuration space */
403
-			  0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000   /* port 2 configuration space */
404
-			  0x81000000 0 0x0        0x0 0x50000000 0 0x00010000   /* downstream I/O (64 KiB) */
405
-			  0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000   /* non-prefetchable memory (127 MiB) */
406
-			  0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
1014
+		ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */
1015
+			 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */
1016
+			 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */
1017
+			 <0x01000000 0 0x0        0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */
1018
+			 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */
1019
+			 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
4071020 
408
-		clocks = <&bpmp TEGRA186_CLK_AFI>,
409
-			 <&bpmp TEGRA186_CLK_PCIE>,
1021
+		clocks = <&bpmp TEGRA186_CLK_PCIE>,
1022
+			 <&bpmp TEGRA186_CLK_AFI>,
4101023 			 <&bpmp TEGRA186_CLK_PLLE>;
411
-		clock-names = "afi", "pex", "pll_e";
1024
+		clock-names = "pex", "afi", "pll_e";
4121025 
413
-		resets = <&bpmp TEGRA186_RESET_AFI>,
414
-			 <&bpmp TEGRA186_RESET_PCIE>,
1026
+		resets = <&bpmp TEGRA186_RESET_PCIE>,
1027
+			 <&bpmp TEGRA186_RESET_AFI>,
4151028 			 <&bpmp TEGRA186_RESET_PCIEXCLK>;
416
-		reset-names = "afi", "pex", "pcie_x";
1029
+		reset-names = "pex", "afi", "pcie_x";
1030
+
1031
+		interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>,
1032
+				<&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>;
1033
+		interconnect-names = "dma-mem", "write";
1034
+
1035
+		iommus = <&smmu TEGRA186_SID_AFI>;
1036
+		iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
1037
+		iommu-map-mask = <0x0>;
4171038 
4181039 		status = "disabled";
4191040 
....@@ -531,12 +1152,13 @@
5311152 	};
5321153 
5331154 	host1x@13e00000 {
534
-		compatible = "nvidia,tegra186-host1x", "simple-bus";
1155
+		compatible = "nvidia,tegra186-host1x";
5351156 		reg = <0x0 0x13e00000 0x0 0x10000>,
5361157 		      <0x0 0x13e10000 0x0 0x10000>;
5371158 		reg-names = "hypervisor", "vm";
5381159 		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
5391160 		             <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1161
+		interrupt-names = "syncpt", "host1x";
5401162 		clocks = <&bpmp TEGRA186_CLK_HOST1X>;
5411163 		clock-names = "host1x";
5421164 		resets = <&bpmp TEGRA186_RESET_HOST1X>;
....@@ -546,6 +1168,10 @@
5461168 		#size-cells = <1>;
5471169 
5481170 		ranges = <0x15000000 0x0 0x15000000 0x01000000>;
1171
+
1172
+		interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>;
1173
+		interconnect-names = "dma-mem";
1174
+
5491175 		iommus = <&smmu TEGRA186_SID_HOST1X>;
5501176 
5511177 		dpaux1: dpaux@15040000 {
....@@ -583,7 +1209,8 @@
5831209 		};
5841210 
5851211 		display-hub@15200000 {
586
-			compatible = "nvidia,tegra186-display", "simple-bus";
1212
+			compatible = "nvidia,tegra186-display";
1213
+			reg = <0x15200000 0x00040000>;
5871214 			resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
5881215 				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
5891216 				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
....@@ -616,6 +1243,9 @@
6161243 				reset-names = "dc";
6171244 
6181245 				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1246
+				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1247
+						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1248
+				interconnect-names = "dma-mem", "read-1";
6191249 				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
6201250 
6211251 				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
....@@ -632,6 +1262,9 @@
6321262 				reset-names = "dc";
6331263 
6341264 				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1265
+				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1266
+						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1267
+				interconnect-names = "dma-mem", "read-1";
6351268 				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
6361269 
6371270 				nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
....@@ -648,6 +1281,9 @@
6481281 				reset-names = "dc";
6491282 
6501283 				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1284
+				interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
1285
+						<&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1286
+				interconnect-names = "dma-mem", "read-1";
6511287 				iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
6521288 
6531289 				nvidia,outputs = <&sor0 &sor1>;
....@@ -680,6 +1316,10 @@
6801316 			reset-names = "vic";
6811317 
6821318 			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1319
+			interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>,
1320
+					<&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>;
1321
+			interconnect-names = "dma-mem", "write";
1322
+			iommus = <&smmu TEGRA186_SID_VIC>;
6831323 		};
6841324 
6851325 		dsib: dsi@15400000 {
....@@ -722,7 +1362,7 @@
7221362 		};
7231363 
7241364 		sor1: sor@15580000 {
725
-			compatible = "nvidia,tegra186-sor1";
1365
+			compatible = "nvidia,tegra186-sor";
7261366 			reg = <0x15580000 0x10000>;
7271367 			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
7281368 			clocks = <&bpmp TEGRA186_CLK_SOR1>,
....@@ -822,8 +1462,8 @@
8221462 		compatible = "nvidia,gp10b";
8231463 		reg = <0x0 0x17000000 0x0 0x1000000>,
8241464 		      <0x0 0x18000000 0x0 0x1000000>;
825
-		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
826
-			      GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1465
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1466
+			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
8271467 		interrupt-names = "stall", "nonstall";
8281468 
8291469 		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
....@@ -834,73 +1474,41 @@
8341474 		status = "disabled";
8351475 
8361476 		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1477
+		interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>,
1478
+				<&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>,
1479
+				<&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>,
1480
+				<&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>;
1481
+		interconnect-names = "dma-mem", "write-0", "read-1", "write-1";
8371482 	};
8381483 
839
-	sysram@30000000 {
1484
+	sram@30000000 {
8401485 		compatible = "nvidia,tegra186-sysram", "mmio-sram";
8411486 		reg = <0x0 0x30000000 0x0 0x50000>;
842
-		#address-cells = <2>;
843
-		#size-cells = <2>;
844
-		ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
1487
+		#address-cells = <1>;
1488
+		#size-cells = <1>;
1489
+		ranges = <0x0 0x0 0x30000000 0x50000>;
8451490 
846
-		cpu_bpmp_tx: shmem@4e000 {
847
-			compatible = "nvidia,tegra186-bpmp-shmem";
848
-			reg = <0x0 0x4e000 0x0 0x1000>;
1491
+		cpu_bpmp_tx: sram@4e000 {
1492
+			reg = <0x4e000 0x1000>;
8491493 			label = "cpu-bpmp-tx";
8501494 			pool;
8511495 		};
8521496 
853
-		cpu_bpmp_rx: shmem@4f000 {
854
-			compatible = "nvidia,tegra186-bpmp-shmem";
855
-			reg = <0x0 0x4f000 0x0 0x1000>;
1497
+		cpu_bpmp_rx: sram@4f000 {
1498
+			reg = <0x4f000 0x1000>;
8561499 			label = "cpu-bpmp-rx";
8571500 			pool;
8581501 		};
8591502 	};
8601503 
861
-	cpus {
862
-		#address-cells = <1>;
863
-		#size-cells = <0>;
864
-
865
-		cpu@0 {
866
-			compatible = "nvidia,tegra186-denver", "arm,armv8";
867
-			device_type = "cpu";
868
-			reg = <0x000>;
869
-		};
870
-
871
-		cpu@1 {
872
-			compatible = "nvidia,tegra186-denver", "arm,armv8";
873
-			device_type = "cpu";
874
-			reg = <0x001>;
875
-		};
876
-
877
-		cpu@2 {
878
-			compatible = "arm,cortex-a57", "arm,armv8";
879
-			device_type = "cpu";
880
-			reg = <0x100>;
881
-		};
882
-
883
-		cpu@3 {
884
-			compatible = "arm,cortex-a57", "arm,armv8";
885
-			device_type = "cpu";
886
-			reg = <0x101>;
887
-		};
888
-
889
-		cpu@4 {
890
-			compatible = "arm,cortex-a57", "arm,armv8";
891
-			device_type = "cpu";
892
-			reg = <0x102>;
893
-		};
894
-
895
-		cpu@5 {
896
-			compatible = "arm,cortex-a57", "arm,armv8";
897
-			device_type = "cpu";
898
-			reg = <0x103>;
899
-		};
900
-	};
901
-
9021504 	bpmp: bpmp {
9031505 		compatible = "nvidia,tegra186-bpmp";
1506
+		interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
1507
+				<&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
1508
+				<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
1509
+				<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
1510
+		interconnect-names = "read", "write", "dma-mem", "dma-write";
1511
+		iommus = <&smmu TEGRA186_SID_BPMP>;
9041512 		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
9051513 				    TEGRA_HSP_DB_MASTER_BPMP>;
9061514 		shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
....@@ -919,6 +1527,107 @@
9191527 		bpmp_thermal: thermal {
9201528 			compatible = "nvidia,tegra186-bpmp-thermal";
9211529 			#thermal-sensor-cells = <1>;
1530
+		};
1531
+	};
1532
+
1533
+	cpus {
1534
+		#address-cells = <1>;
1535
+		#size-cells = <0>;
1536
+
1537
+		cpu@0 {
1538
+			compatible = "nvidia,tegra186-denver";
1539
+			device_type = "cpu";
1540
+			i-cache-size = <0x20000>;
1541
+			i-cache-line-size = <64>;
1542
+			i-cache-sets = <512>;
1543
+			d-cache-size = <0x10000>;
1544
+			d-cache-line-size = <64>;
1545
+			d-cache-sets = <256>;
1546
+			next-level-cache = <&L2_DENVER>;
1547
+			reg = <0x000>;
1548
+		};
1549
+
1550
+		cpu@1 {
1551
+			compatible = "nvidia,tegra186-denver";
1552
+			device_type = "cpu";
1553
+			i-cache-size = <0x20000>;
1554
+			i-cache-line-size = <64>;
1555
+			i-cache-sets = <512>;
1556
+			d-cache-size = <0x10000>;
1557
+			d-cache-line-size = <64>;
1558
+			d-cache-sets = <256>;
1559
+			next-level-cache = <&L2_DENVER>;
1560
+			reg = <0x001>;
1561
+		};
1562
+
1563
+		cpu@2 {
1564
+			compatible = "arm,cortex-a57";
1565
+			device_type = "cpu";
1566
+			i-cache-size = <0xC000>;
1567
+			i-cache-line-size = <64>;
1568
+			i-cache-sets = <256>;
1569
+			d-cache-size = <0x8000>;
1570
+			d-cache-line-size = <64>;
1571
+			d-cache-sets = <256>;
1572
+			next-level-cache = <&L2_A57>;
1573
+			reg = <0x100>;
1574
+		};
1575
+
1576
+		cpu@3 {
1577
+			compatible = "arm,cortex-a57";
1578
+			device_type = "cpu";
1579
+			i-cache-size = <0xC000>;
1580
+			i-cache-line-size = <64>;
1581
+			i-cache-sets = <256>;
1582
+			d-cache-size = <0x8000>;
1583
+			d-cache-line-size = <64>;
1584
+			d-cache-sets = <256>;
1585
+			next-level-cache = <&L2_A57>;
1586
+			reg = <0x101>;
1587
+		};
1588
+
1589
+		cpu@4 {
1590
+			compatible = "arm,cortex-a57";
1591
+			device_type = "cpu";
1592
+			i-cache-size = <0xC000>;
1593
+			i-cache-line-size = <64>;
1594
+			i-cache-sets = <256>;
1595
+			d-cache-size = <0x8000>;
1596
+			d-cache-line-size = <64>;
1597
+			d-cache-sets = <256>;
1598
+			next-level-cache = <&L2_A57>;
1599
+			reg = <0x102>;
1600
+		};
1601
+
1602
+		cpu@5 {
1603
+			compatible = "arm,cortex-a57";
1604
+			device_type = "cpu";
1605
+			i-cache-size = <0xC000>;
1606
+			i-cache-line-size = <64>;
1607
+			i-cache-sets = <256>;
1608
+			d-cache-size = <0x8000>;
1609
+			d-cache-line-size = <64>;
1610
+			d-cache-sets = <256>;
1611
+			next-level-cache = <&L2_A57>;
1612
+			reg = <0x103>;
1613
+		};
1614
+
1615
+		L2_DENVER: l2-cache0 {
1616
+			compatible = "cache";
1617
+			cache-unified;
1618
+			cache-level = <2>;
1619
+			cache-size = <0x200000>;
1620
+			cache-line-size = <64>;
1621
+			cache-sets = <2048>;
1622
+		};
1623
+
1624
+		L2_A57: l2-cache1 {
1625
+			compatible = "cache";
1626
+			cache-unified;
1627
+			cache-level = <2>;
1628
+			cache-size = <0x200000>;
1629
+			cache-line-size = <64>;
1630
+			cache-sets = <2048>;
9221631 		};
9231632 	};
9241633 
....@@ -1030,5 +1739,6 @@
10301739 			     <GIC_PPI 10
10311740 				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
10321741 		interrupt-parent = <&gic>;
1742
+		always-on;
10331743 	};
10341744 };