update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/arm64/boot/dts/mediatek/mt7622.dtsi
..
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@@ -70,7 +70,7 @@
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 		cpu0: cpu@0 {
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 			device_type = "cpu";
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			reg = <0x0 0x0>;
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 			clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
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 				 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
..
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@@ -79,11 +79,12 @@
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 			#cooling-cells = <2>;
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 			enable-method = "psci";
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 			clock-frequency = <1300000000>;
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+			cci-control-port = <&cci_control2>;
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 		};
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 		cpu1: cpu@1 {
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 			device_type = "cpu";
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			reg = <0x0 0x1>;
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 			clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
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 				 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
..
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@@ -92,6 +93,7 @@
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 			#cooling-cells = <2>;
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 			enable-method = "psci";
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 			clock-frequency = <1300000000>;
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+			cci-control-port = <&cci_control2>;
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 		};
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 	};
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..
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@@ -111,6 +113,13 @@
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 	psci {
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 		compatible  = "arm,psci-0.2";
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 		method      = "smc";
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+	};
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+
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+	pmu {
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+		compatible = "arm,cortex-a53-pmu";
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+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
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+			     <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
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+		interrupt-affinity = <&cpu0>, <&cpu1>;
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 	};
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 	reserved-memory {
..
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@@ -161,17 +170,20 @@
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 			cooling-maps {
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 				map0 {
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 					trip = <&cpu_passive>;
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-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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 				};
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 				map1 {
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 					trip = <&cpu_active>;
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-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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 				};
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 				map2 {
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 					trip = <&cpu_hot>;
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-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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 				};
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 			};
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 		};
..
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@@ -218,7 +230,7 @@
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 		#reset-cells = <1>;
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 	};
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-	scpsys: scpsys@10006000 {
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+	scpsys: power-controller@10006000 {
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 		compatible = "mediatek,mt7622-scpsys",
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 			     "syscon";
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 		#power-domain-cells = <1>;
..
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@@ -325,6 +337,42 @@
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 		      <0 0x10360000 0 0x2000>;
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 	};
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+	cci: cci@10390000 {
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+		compatible = "arm,cci-400";
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+		#address-cells = <1>;
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+		#size-cells = <1>;
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+		reg = <0 0x10390000 0 0x1000>;
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+		ranges = <0 0 0x10390000 0x10000>;
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+
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+		cci_control0: slave-if@1000 {
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+			compatible = "arm,cci-400-ctrl-if";
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+			interface-type = "ace-lite";
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+			reg = <0x1000 0x1000>;
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+		};
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+
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+		cci_control1: slave-if@4000 {
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+			compatible = "arm,cci-400-ctrl-if";
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+			interface-type = "ace";
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+			reg = <0x4000 0x1000>;
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+		};
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+
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+		cci_control2: slave-if@5000 {
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+			compatible = "arm,cci-400-ctrl-if";
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+			interface-type = "ace";
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+			reg = <0x5000 0x1000>;
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+		};
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+
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+		pmu@9000 {
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+			compatible = "arm,cci-400-pmu,r1";
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+			reg = <0x9000 0x5000>;
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+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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+		};
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+	};
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+
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 	auxadc: adc@11001000 {
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 		compatible = "mediatek,mt7622-auxadc";
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 		reg = <0 0x11001000 0 0x1000>;
..
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@@ -380,6 +428,7 @@
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 	pwm: pwm@11006000 {
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 		compatible = "mediatek,mt7622-pwm";
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 		reg = <0 0x11006000 0 0x1000>;
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+		#pwm-cells = <2>;
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 		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
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 		clocks = <&topckgen CLK_TOP_PWM_SEL>,
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 			 <&pericfg CLK_PERI_PWM_PD>,
..
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@@ -475,6 +524,13 @@
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 		reg-shift = <2>;
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 		reg-io-width = <4>;
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 		status = "disabled";
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+
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+		bluetooth {
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+			compatible = "mediatek,mt7622-bluetooth";
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+			power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
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+			clocks = <&clk25m>;
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+			clock-names = "ref";
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+		};
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 	};
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 	nandc: nfi@1100d000 {
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@@ -631,6 +687,8 @@
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 		clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
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 			 <&topckgen CLK_TOP_MSDC50_0_SEL>;
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 		clock-names = "source", "hclk";
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+		resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>;
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+		reset-names = "hrst";
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 		status = "disabled";
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 	};
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..
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@@ -644,6 +702,17 @@
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 		resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>;
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 		reset-names = "hrst";
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 		status = "disabled";
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+	};
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+
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+	wmac: wmac@18000000 {
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+		compatible = "mediatek,mt7622-wmac";
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+		reg = <0 0x18000000 0 0x100000>;
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+		interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
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+
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+		mediatek,infracfg = <&infracfg>;
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+		status = "disabled";
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+
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+		power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
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 	};
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 	ssusbsys: ssusbsys@1a000000 {
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@@ -752,7 +821,6 @@
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 			ranges;
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 			status = "disabled";
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-			num-lanes = <1>;
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 			interrupt-map-mask = <0 0 0 7>;
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 			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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 					<0 0 0 2 &pcie_intc0 1>,
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@@ -773,7 +841,6 @@
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 			ranges;
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 			status = "disabled";
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-			num-lanes = <1>;
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 			interrupt-map-mask = <0 0 0 7>;
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 			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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 					<0 0 0 2 &pcie_intc1 1>,
..
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@@ -878,7 +945,7 @@
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 	sgmiisys: sgmiisys@1b128000 {
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 		compatible = "mediatek,mt7622-sgmiisys",
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 			     "syscon";
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-		reg = <0 0x1b128000 0 0x1000>;
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+		reg = <0 0x1b128000 0 0x3000>;
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 		#clock-cells = <1>;
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 	};
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 };