update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
..
..
@@ -15,29 +15,79 @@
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 		#address-cells = <1>;
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 		#size-cells = <0>;
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-		cpu@0 {
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+		cpu0: cpu@0 {
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 			device_type = "cpu";
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-			compatible = "arm,cortex-a72", "arm,armv8";
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+			compatible = "arm,cortex-a72";
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 			reg = <0x000>;
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 			enable-method = "psci";
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+			#cooling-cells = <2>;
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+			clocks = <&cpu_clk 0>;
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+			i-cache-size = <0xc000>;
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+			i-cache-line-size = <64>;
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+			i-cache-sets = <256>;
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+			d-cache-size = <0x8000>;
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+			d-cache-line-size = <64>;
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+			d-cache-sets = <256>;
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+			next-level-cache = <&l2_0>;
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 		};
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-		cpu@1 {
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+		cpu1: cpu@1 {
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 			device_type = "cpu";
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-			compatible = "arm,cortex-a72", "arm,armv8";
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+			compatible = "arm,cortex-a72";
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 			reg = <0x001>;
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 			enable-method = "psci";
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+			#cooling-cells = <2>;
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+			clocks = <&cpu_clk 0>;
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+			i-cache-size = <0xc000>;
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+			i-cache-line-size = <64>;
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+			i-cache-sets = <256>;
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+			d-cache-size = <0x8000>;
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+			d-cache-line-size = <64>;
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+			d-cache-sets = <256>;
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+			next-level-cache = <&l2_0>;
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 		};
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-		cpu@100 {
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+		cpu2: cpu@100 {
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 			device_type = "cpu";
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-			compatible = "arm,cortex-a72", "arm,armv8";
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+			compatible = "arm,cortex-a72";
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 			reg = <0x100>;
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 			enable-method = "psci";
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+			#cooling-cells = <2>;
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+			clocks = <&cpu_clk 1>;
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+			i-cache-size = <0xc000>;
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+			i-cache-line-size = <64>;
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+			i-cache-sets = <256>;
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+			d-cache-size = <0x8000>;
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+			d-cache-line-size = <64>;
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+			d-cache-sets = <256>;
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+			next-level-cache = <&l2_1>;
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 		};
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-		cpu@101 {
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+		cpu3: cpu@101 {
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 			device_type = "cpu";
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-			compatible = "arm,cortex-a72", "arm,armv8";
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+			compatible = "arm,cortex-a72";
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 			reg = <0x101>;
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 			enable-method = "psci";
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+			#cooling-cells = <2>;
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+			clocks = <&cpu_clk 1>;
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+			i-cache-size = <0xc000>;
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+			i-cache-line-size = <64>;
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+			i-cache-sets = <256>;
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+			d-cache-size = <0x8000>;
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+			d-cache-line-size = <64>;
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+			d-cache-sets = <256>;
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+			next-level-cache = <&l2_1>;
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+		};
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+
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+		l2_0: l2-cache0 {
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+			compatible = "cache";
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+			cache-size = <0x80000>;
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+			cache-line-size = <64>;
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+			cache-sets = <512>;
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+		};
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+
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+		l2_1: l2-cache1 {
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+			compatible = "cache";
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+			cache-size = <0x80000>;
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+			cache-line-size = <64>;
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+			cache-sets = <512>;
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 		};
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 	};
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 };