.. | .. |
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40 | 40 | cpus { |
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41 | 41 | #address-cells = <1>; |
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42 | 42 | #size-cells = <0>; |
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43 | | - cpu@0 { |
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| 43 | + cpu0: cpu@0 { |
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44 | 44 | device_type = "cpu"; |
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45 | | - compatible = "arm,cortex-a53", "arm,armv8"; |
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| 45 | + compatible = "arm,cortex-a53"; |
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46 | 46 | reg = <0>; |
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47 | 47 | clocks = <&nb_periph_clk 16>; |
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48 | 48 | enable-method = "psci"; |
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.. | .. |
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79 | 79 | compatible = "simple-bus"; |
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80 | 80 | /* 32M internal register @ 0xd000_0000 */ |
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81 | 81 | ranges = <0x0 0x0 0xd0000000 0x2000000>; |
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| 82 | + |
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| 83 | + wdt: watchdog@8300 { |
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| 84 | + compatible = "marvell,armada-3700-wdt"; |
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| 85 | + reg = <0x8300 0x40>; |
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| 86 | + marvell,system-controller = <&cpu_misc>; |
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| 87 | + clocks = <&xtalclk>; |
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| 88 | + }; |
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| 89 | + |
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| 90 | + cpu_misc: system-controller@d000 { |
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| 91 | + compatible = "marvell,armada-3700-cpu-misc", |
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| 92 | + "syscon"; |
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| 93 | + reg = <0xd000 0x1000>; |
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| 94 | + }; |
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82 | 95 | |
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83 | 96 | spi0: spi@10600 { |
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84 | 97 | compatible = "marvell,armada-3700-spi"; |
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.. | .. |
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203 | 216 | function = "spi"; |
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204 | 217 | }; |
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205 | 218 | |
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| 219 | + spi_cs1_pins: spi-cs1-pins { |
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| 220 | + groups = "spi_cs1"; |
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| 221 | + function = "spi"; |
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| 222 | + }; |
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| 223 | + |
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206 | 224 | i2c1_pins: i2c1-pins { |
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207 | 225 | groups = "i2c1"; |
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208 | 226 | function = "i2c"; |
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.. | .. |
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222 | 240 | groups = "uart2"; |
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223 | 241 | function = "uart"; |
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224 | 242 | }; |
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| 243 | + |
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| 244 | + mmc_pins: mmc-pins { |
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| 245 | + groups = "emmc_nb"; |
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| 246 | + function = "emmc"; |
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| 247 | + }; |
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225 | 248 | }; |
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226 | 249 | |
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227 | 250 | nb_pm: syscon@14000 { |
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228 | 251 | compatible = "marvell,armada-3700-nb-pm", |
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229 | 252 | "syscon"; |
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230 | 253 | reg = <0x14000 0x60>; |
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| 254 | + }; |
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| 255 | + |
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| 256 | + comphy: phy@18300 { |
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| 257 | + compatible = "marvell,comphy-a3700"; |
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| 258 | + reg = <0x18300 0x300>, |
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| 259 | + <0x1F000 0x400>, |
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| 260 | + <0x5C000 0x400>, |
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| 261 | + <0xe0178 0x8>; |
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| 262 | + reg-names = "comphy", |
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| 263 | + "lane1_pcie_gbe", |
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| 264 | + "lane0_usb3_gbe", |
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| 265 | + "lane2_sata_usb3"; |
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| 266 | + #address-cells = <1>; |
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| 267 | + #size-cells = <0>; |
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| 268 | + |
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| 269 | + comphy0: phy@0 { |
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| 270 | + reg = <0>; |
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| 271 | + #phy-cells = <1>; |
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| 272 | + }; |
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| 273 | + |
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| 274 | + comphy1: phy@1 { |
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| 275 | + reg = <1>; |
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| 276 | + #phy-cells = <1>; |
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| 277 | + }; |
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| 278 | + |
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| 279 | + comphy2: phy@2 { |
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| 280 | + reg = <2>; |
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| 281 | + #phy-cells = <1>; |
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| 282 | + }; |
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231 | 283 | }; |
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232 | 284 | |
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233 | 285 | pinctrl_sb: pinctrl@18800 { |
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.. | .. |
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254 | 306 | function = "mii"; |
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255 | 307 | }; |
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256 | 308 | |
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| 309 | + smi_pins: smi-pins { |
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| 310 | + groups = "smi"; |
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| 311 | + function = "smi"; |
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| 312 | + }; |
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| 313 | + |
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| 314 | + sdio_pins: sdio-pins { |
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| 315 | + groups = "sdio_sb"; |
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| 316 | + function = "sdio"; |
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| 317 | + }; |
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| 318 | + |
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257 | 319 | pcie_reset_pins: pcie-reset-pins { |
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258 | | - groups = "pcie1"; |
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| 320 | + groups = "pcie1"; /* this actually controls "pcie1_reset" */ |
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259 | 321 | function = "gpio"; |
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260 | 322 | }; |
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261 | 323 | |
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.. | .. |
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292 | 354 | compatible = "marvell,armada3700-xhci", |
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293 | 355 | "generic-xhci"; |
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294 | 356 | reg = <0x58000 0x4000>; |
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| 357 | + marvell,usb-misc-reg = <&usb32_syscon>; |
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295 | 358 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
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296 | 359 | clocks = <&sb_periph_clk 12>; |
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| 360 | + phys = <&comphy0 0>, <&usb2_utmi_otg_phy>; |
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| 361 | + phy-names = "usb3-phy", "usb2-utmi-otg-phy"; |
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297 | 362 | status = "disabled"; |
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| 363 | + }; |
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| 364 | + |
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| 365 | + usb2_utmi_otg_phy: phy@5d000 { |
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| 366 | + compatible = "marvell,a3700-utmi-otg-phy"; |
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| 367 | + reg = <0x5d000 0x800>; |
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| 368 | + marvell,usb-misc-reg = <&usb32_syscon>; |
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| 369 | + #phy-cells = <0>; |
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| 370 | + }; |
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| 371 | + |
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| 372 | + usb32_syscon: system-controller@5d800 { |
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| 373 | + compatible = "marvell,armada-3700-usb2-host-device-misc", |
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| 374 | + "syscon"; |
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| 375 | + reg = <0x5d800 0x800>; |
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298 | 376 | }; |
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299 | 377 | |
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300 | 378 | usb2: usb@5e000 { |
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301 | 379 | compatible = "marvell,armada-3700-ehci"; |
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302 | | - reg = <0x5e000 0x2000>; |
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| 380 | + reg = <0x5e000 0x1000>; |
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| 381 | + marvell,usb-misc-reg = <&usb2_syscon>; |
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303 | 382 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
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| 383 | + phys = <&usb2_utmi_host_phy>; |
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| 384 | + phy-names = "usb2-utmi-host-phy"; |
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304 | 385 | status = "disabled"; |
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| 386 | + }; |
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| 387 | + |
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| 388 | + usb2_utmi_host_phy: phy@5f000 { |
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| 389 | + compatible = "marvell,a3700-utmi-host-phy"; |
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| 390 | + reg = <0x5f000 0x800>; |
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| 391 | + marvell,usb-misc-reg = <&usb2_syscon>; |
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| 392 | + #phy-cells = <0>; |
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| 393 | + }; |
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| 394 | + |
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| 395 | + usb2_syscon: system-controller@5f800 { |
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| 396 | + compatible = "marvell,armada-3700-usb2-host-misc", |
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| 397 | + "syscon"; |
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| 398 | + reg = <0x5f800 0x800>; |
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305 | 399 | }; |
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306 | 400 | |
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307 | 401 | xor@60900 { |
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.. | .. |
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331 | 425 | clocks = <&nb_periph_clk 15>; |
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332 | 426 | }; |
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333 | 427 | |
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| 428 | + rwtm: mailbox@b0000 { |
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| 429 | + compatible = "marvell,armada-3700-rwtm-mailbox"; |
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| 430 | + reg = <0xb0000 0x100>; |
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| 431 | + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; |
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| 432 | + #mbox-cells = <1>; |
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| 433 | + }; |
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| 434 | + |
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334 | 435 | sdhci1: sdhci@d0000 { |
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335 | 436 | compatible = "marvell,armada-3700-sdhci", |
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336 | 437 | "marvell,sdhci-xenon"; |
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.. | .. |
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355 | 456 | |
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356 | 457 | sata: sata@e0000 { |
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357 | 458 | compatible = "marvell,armada-3700-ahci"; |
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358 | | - reg = <0xe0000 0x2000>; |
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| 459 | + reg = <0xe0000 0x178>; |
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359 | 460 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
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| 461 | + clocks = <&nb_periph_clk 1>; |
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360 | 462 | status = "disabled"; |
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361 | 463 | }; |
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362 | 464 | |
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.. | .. |
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393 | 495 | * (totaling 127 MiB) for MEM. |
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394 | 496 | */ |
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395 | 497 | ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */ |
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396 | | - 0x81000000 0 0xefff0000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */ |
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| 498 | + 0x81000000 0 0x00000000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */ |
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397 | 499 | interrupt-map-mask = <0 0 0 7>; |
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398 | 500 | interrupt-map = <0 0 0 1 &pcie_intc 0>, |
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399 | 501 | <0 0 0 2 &pcie_intc 1>, |
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400 | 502 | <0 0 0 3 &pcie_intc 2>, |
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401 | 503 | <0 0 0 4 &pcie_intc 3>; |
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| 504 | + max-link-speed = <2>; |
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| 505 | + phys = <&comphy1 0>; |
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402 | 506 | pcie_intc: interrupt-controller { |
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403 | 507 | interrupt-controller; |
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404 | 508 | #interrupt-cells = <1>; |
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405 | 509 | }; |
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406 | 510 | }; |
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407 | 511 | }; |
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| 512 | + |
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| 513 | + firmware { |
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| 514 | + armada-3700-rwtm { |
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| 515 | + compatible = "marvell,armada-3700-rwtm-firmware"; |
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| 516 | + mboxes = <&rwtm 0>; |
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| 517 | + status = "okay"; |
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| 518 | + }; |
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| 519 | + }; |
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408 | 520 | }; |
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