update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/arm64/boot/dts/lg/lg1312.dtsi
..
..
@@ -21,27 +21,27 @@
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 		cpu0: cpu@0 {
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 			device_type = "cpu";
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			reg = <0x0 0x0>;
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 			next-level-cache = <&L2_0>;
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 		};
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 		cpu1: cpu@1 {
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 			device_type = "cpu";
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			reg = <0x0 0x1>;
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 			enable-method = "psci";
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 			next-level-cache = <&L2_0>;
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 		};
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 		cpu2: cpu@2 {
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 			device_type = "cpu";
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			reg = <0x0 0x2>;
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 			enable-method = "psci";
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 			next-level-cache = <&L2_0>;
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 		};
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 		cpu3: cpu@3 {
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 			device_type = "cpu";
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-			compatible = "arm,cortex-a53", "arm,armv8";
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+			compatible = "arm,cortex-a53";
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 			reg = <0x0 0x3>;
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 			enable-method = "psci";
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 			next-level-cache = <&L2_0>;
..
..
@@ -124,25 +124,25 @@
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 	amba {
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 		#address-cells = <2>;
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 		#size-cells = <1>;
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-		#interrupts-cells = <3>;
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+		#interrupt-cells = <3>;
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 		compatible = "simple-bus";
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 		interrupt-parent = <&gic>;
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 		ranges;
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 		timers: timer@fd100000 {
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-			compatible = "arm,sp804";
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+			compatible = "arm,sp804", "arm,primecell";
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 			reg = <0x0 0xfd100000 0x1000>;
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 			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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-			clocks = <&clk_bus>;
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-			clock-names = "apb_pclk";
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+			clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>;
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+			clock-names = "timer0clk", "timer1clk", "apb_pclk";
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 		};
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 		wdog: watchdog@fd200000 {
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 			compatible = "arm,sp805", "arm,primecell";
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 			reg = <0x0 0xfd200000 0x1000>;
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 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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-			clocks = <&clk_bus>;
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-			clock-names = "apb_pclk";
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+			clocks = <&clk_bus>, <&clk_bus>;
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+			clock-names = "wdog_clk", "apb_pclk";
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 		};
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 		uart0: serial@fe000000 {
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 			compatible = "arm,pl011", "arm,primecell";