update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/arm64/boot/dts/arm/foundation-v8.dtsi
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@@ -7,6 +7,8 @@
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 /dts-v1/;
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+
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 /memreserve/ 0x80000000 0x00010000;
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 / {
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@@ -67,30 +69,51 @@
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 	timer {
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 		compatible = "arm,armv8-timer";
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-		interrupts = <1 13 0xf08>,
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-			     <1 14 0xf08>,
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-			     <1 11 0xf08>,
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-			     <1 10 0xf08>;
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+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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 		clock-frequency = <100000000>;
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 	};
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 	pmu {
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 		compatible = "arm,armv8-pmuv3";
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-		interrupts = <0 60 4>,
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-			     <0 61 4>,
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-			     <0 62 4>,
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-			     <0 63 4>;
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+		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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 	};
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 	watchdog@2a440000 {
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 		compatible = "arm,sbsa-gwdt";
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 		reg = <0x0 0x2a440000 0 0x1000>,
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 			<0x0 0x2a450000 0 0x1000>;
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-		interrupts = <0 27 4>;
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+		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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 		timeout-sec = <30>;
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 	};
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-	smb@8000000 {
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+	v2m_clk24mhz: clk24mhz {
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+		compatible = "fixed-clock";
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+		#clock-cells = <0>;
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+		clock-frequency = <24000000>;
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+		clock-output-names = "v2m:clk24mhz";
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+	};
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+
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+	v2m_refclk1mhz: refclk1mhz {
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+		compatible = "fixed-clock";
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+		#clock-cells = <0>;
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+		clock-frequency = <1000000>;
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+		clock-output-names = "v2m:refclk1mhz";
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+	};
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+
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+	v2m_refclk32khz: refclk32khz {
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+		compatible = "fixed-clock";
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+		#clock-cells = <0>;
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+		clock-frequency = <32768>;
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+		clock-output-names = "v2m:refclk32khz";
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+	};
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+
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+	bus@8000000 {
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 		compatible = "arm,vexpress,v2m-p1", "simple-bus";
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 		arm,v2m-memory-map = "rs1";
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 		#address-cells = <2>; /* SMB chipselect number and offset */
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@@ -105,78 +128,57 @@
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 		#interrupt-cells = <1>;
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 		interrupt-map-mask = <0 0 63>;
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-		interrupt-map = <0 0  0 &gic 0 0 0  0 4>,
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-				<0 0  1 &gic 0 0 0  1 4>,
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-				<0 0  2 &gic 0 0 0  2 4>,
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-				<0 0  3 &gic 0 0 0  3 4>,
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-				<0 0  4 &gic 0 0 0  4 4>,
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-				<0 0  5 &gic 0 0 0  5 4>,
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-				<0 0  6 &gic 0 0 0  6 4>,
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-				<0 0  7 &gic 0 0 0  7 4>,
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-				<0 0  8 &gic 0 0 0  8 4>,
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-				<0 0  9 &gic 0 0 0  9 4>,
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-				<0 0 10 &gic 0 0 0 10 4>,
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-				<0 0 11 &gic 0 0 0 11 4>,
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-				<0 0 12 &gic 0 0 0 12 4>,
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-				<0 0 13 &gic 0 0 0 13 4>,
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-				<0 0 14 &gic 0 0 0 14 4>,
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-				<0 0 15 &gic 0 0 0 15 4>,
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-				<0 0 16 &gic 0 0 0 16 4>,
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-				<0 0 17 &gic 0 0 0 17 4>,
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-				<0 0 18 &gic 0 0 0 18 4>,
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-				<0 0 19 &gic 0 0 0 19 4>,
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-				<0 0 20 &gic 0 0 0 20 4>,
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-				<0 0 21 &gic 0 0 0 21 4>,
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-				<0 0 22 &gic 0 0 0 22 4>,
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-				<0 0 23 &gic 0 0 0 23 4>,
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-				<0 0 24 &gic 0 0 0 24 4>,
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-				<0 0 25 &gic 0 0 0 25 4>,
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-				<0 0 26 &gic 0 0 0 26 4>,
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-				<0 0 27 &gic 0 0 0 27 4>,
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-				<0 0 28 &gic 0 0 0 28 4>,
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-				<0 0 29 &gic 0 0 0 29 4>,
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-				<0 0 30 &gic 0 0 0 30 4>,
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-				<0 0 31 &gic 0 0 0 31 4>,
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-				<0 0 32 &gic 0 0 0 32 4>,
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-				<0 0 33 &gic 0 0 0 33 4>,
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-				<0 0 34 &gic 0 0 0 34 4>,
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-				<0 0 35 &gic 0 0 0 35 4>,
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-				<0 0 36 &gic 0 0 0 36 4>,
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-				<0 0 37 &gic 0 0 0 37 4>,
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-				<0 0 38 &gic 0 0 0 38 4>,
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-				<0 0 39 &gic 0 0 0 39 4>,
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-				<0 0 40 &gic 0 0 0 40 4>,
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-				<0 0 41 &gic 0 0 0 41 4>,
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-				<0 0 42 &gic 0 0 0 42 4>;
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+		interrupt-map = <0 0  0 &gic 0 GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0  1 &gic 0 GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0  2 &gic 0 GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0  3 &gic 0 GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0  4 &gic 0 GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0  5 &gic 0 GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0  6 &gic 0 GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0  7 &gic 0 GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0  8 &gic 0 GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0  9 &gic 0 GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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+				<0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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-		ethernet@2,02000000 {
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+		ethernet@202000000 {
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 			compatible = "smsc,lan91c111";
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 			reg = <2 0x02000000 0x10000>;
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 			interrupts = <15>;
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 		};
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-		v2m_clk24mhz: clk24mhz {
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-			compatible = "fixed-clock";
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-			#clock-cells = <0>;
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-			clock-frequency = <24000000>;
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-			clock-output-names = "v2m:clk24mhz";
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-		};
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-
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-		v2m_refclk1mhz: refclk1mhz {
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-			compatible = "fixed-clock";
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-			#clock-cells = <0>;
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-			clock-frequency = <1000000>;
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-			clock-output-names = "v2m:refclk1mhz";
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-		};
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-
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-		v2m_refclk32khz: refclk32khz {
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-			compatible = "fixed-clock";
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-			#clock-cells = <0>;
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-			clock-frequency = <32768>;
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-			clock-output-names = "v2m:refclk32khz";
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-		};
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-
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-		iofpga@3,00000000 {
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+		iofpga-bus@300000000 {
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 			compatible = "simple-bus";
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 			#address-cells = <1>;
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 			#size-cells = <1>;
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@@ -187,7 +189,7 @@
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 				reg = <0x010000 0x1000>;
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 			};
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-			v2m_serial0: uart@90000 {
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+			v2m_serial0: serial@90000 {
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 				compatible = "arm,pl011", "arm,primecell";
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 				reg = <0x090000 0x1000>;
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 				interrupts = <5>;
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@@ -195,7 +197,7 @@
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 				clock-names = "uartclk", "apb_pclk";
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 			};
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-			v2m_serial1: uart@a0000 {
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+			v2m_serial1: serial@a0000 {
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 				compatible = "arm,pl011", "arm,primecell";
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 				reg = <0x0a0000 0x1000>;
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 				interrupts = <6>;
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@@ -203,7 +205,7 @@
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 				clock-names = "uartclk", "apb_pclk";
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 			};
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-			v2m_serial2: uart@b0000 {
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+			v2m_serial2: serial@b0000 {
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 				compatible = "arm,pl011", "arm,primecell";
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 				reg = <0x0b0000 0x1000>;
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 				interrupts = <7>;
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@@ -211,7 +213,7 @@
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 				clock-names = "uartclk", "apb_pclk";
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 			};
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-			v2m_serial3: uart@c0000 {
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+			v2m_serial3: serial@c0000 {
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 				compatible = "arm,pl011", "arm,primecell";
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 				reg = <0x0c0000 0x1000>;
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 				interrupts = <8>;