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2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
....@@ -1,3 +1,4 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
34  *
....@@ -8,11 +9,6 @@
89  *
910  * Copyright (C) 2002 Intel Corporation.
1011  * Copyright (C) 2003-2004 MontaVista Software, Inc.
11
- *
12
- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
1612  */
1713 
1814 #ifndef _ASM_ARM_IXP4XX_H_
....@@ -43,8 +39,6 @@
4339  * Queue Manager
4440  */
4541 #define IXP4XX_QMGR_BASE_PHYS		0x60000000
46
-#define IXP4XX_QMGR_BASE_VIRT		IOMEM(0xFEF15000)
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-#define IXP4XX_QMGR_REGION_SIZE		0x00004000
4842 
4943 /*
5044  * Peripheral space, including debug UART. Must be section-aligned so that
....@@ -132,9 +126,6 @@
132126 #define IXP4XX_INTC_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
133127 #define IXP4XX_GPIO_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
134128 #define IXP4XX_TIMER_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
135
-#define IXP4XX_NPEA_BASE_VIRT   	(IXP4XX_PERIPHERAL_BASE_VIRT + 0x6000)
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-#define IXP4XX_NPEB_BASE_VIRT   	(IXP4XX_PERIPHERAL_BASE_VIRT + 0x7000)
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-#define IXP4XX_NPEC_BASE_VIRT   	(IXP4XX_PERIPHERAL_BASE_VIRT + 0x8000)
138129 #define IXP4XX_EthB_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
139130 #define IXP4XX_EthC_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
140131 #define IXP4XX_USB_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
....@@ -146,95 +137,6 @@
146137 #define IXP4XX_TIMESYNC_BASE_VIRT	(IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
147138 #define IXP4XX_I2C_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
148139 #define IXP4XX_SSP_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
149
-
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-/*
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- * Constants to make it easy to access  Interrupt Controller registers
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- */
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-#define IXP4XX_ICPR_OFFSET	0x00 /* Interrupt Status */
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-#define IXP4XX_ICMR_OFFSET	0x04 /* Interrupt Enable */
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-#define IXP4XX_ICLR_OFFSET	0x08 /* Interrupt IRQ/FIQ Select */
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-#define IXP4XX_ICIP_OFFSET      0x0C /* IRQ Status */
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-#define IXP4XX_ICFP_OFFSET	0x10 /* FIQ Status */
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-#define IXP4XX_ICHR_OFFSET	0x14 /* Interrupt Priority */
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-#define IXP4XX_ICIH_OFFSET	0x18 /* IRQ Highest Pri Int */
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-#define IXP4XX_ICFH_OFFSET	0x1C /* FIQ Highest Pri Int */
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-
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-/*
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- * IXP465-only
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- */
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-#define	IXP4XX_ICPR2_OFFSET	0x20 /* Interrupt Status 2 */
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-#define	IXP4XX_ICMR2_OFFSET	0x24 /* Interrupt Enable 2 */
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-#define	IXP4XX_ICLR2_OFFSET	0x28 /* Interrupt IRQ/FIQ Select 2 */
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-#define IXP4XX_ICIP2_OFFSET     0x2C /* IRQ Status */
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-#define IXP4XX_ICFP2_OFFSET	0x30 /* FIQ Status */
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-#define IXP4XX_ICEEN_OFFSET	0x34 /* Error High Pri Enable */
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-
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-
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-/*
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- * Interrupt Controller Register Definitions.
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- */
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-
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-#define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x)))
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-
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-#define IXP4XX_ICPR	IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)
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-#define IXP4XX_ICMR     IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)
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-#define IXP4XX_ICLR     IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)
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-#define IXP4XX_ICIP     IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)
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-#define IXP4XX_ICFP     IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)
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-#define IXP4XX_ICHR     IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
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-#define IXP4XX_ICIH     IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET) 
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-#define IXP4XX_ICFH     IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
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-#define IXP4XX_ICPR2	IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)
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-#define IXP4XX_ICMR2    IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)
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-#define IXP4XX_ICLR2    IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)
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-#define IXP4XX_ICIP2    IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)
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-#define IXP4XX_ICFP2    IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)
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-#define IXP4XX_ICEEN    IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)
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-                                                                                
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-/*
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- * Constants to make it easy to access GPIO registers
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- */
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-#define IXP4XX_GPIO_GPOUTR_OFFSET       0x00
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-#define IXP4XX_GPIO_GPOER_OFFSET        0x04
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-#define IXP4XX_GPIO_GPINR_OFFSET        0x08
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-#define IXP4XX_GPIO_GPISR_OFFSET        0x0C
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-#define IXP4XX_GPIO_GPIT1R_OFFSET	0x10
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-#define IXP4XX_GPIO_GPIT2R_OFFSET	0x14
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-#define IXP4XX_GPIO_GPCLKR_OFFSET	0x18
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-#define IXP4XX_GPIO_GPDBSELR_OFFSET	0x1C
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-
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-/* 
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- * GPIO Register Definitions.
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- * [Only perform 32bit reads/writes]
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- */
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-#define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x)))
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-
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-#define IXP4XX_GPIO_GPOUTR	IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)
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-#define IXP4XX_GPIO_GPOER       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)
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-#define IXP4XX_GPIO_GPINR       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)
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-#define IXP4XX_GPIO_GPISR       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)
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-#define IXP4XX_GPIO_GPIT1R      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)
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-#define IXP4XX_GPIO_GPIT2R      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)
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-#define IXP4XX_GPIO_GPCLKR      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)
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-#define IXP4XX_GPIO_GPDBSELR    IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)
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-
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-/*
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- * GPIO register bit definitions
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- */
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-
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-/* Interrupt styles
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- */
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-#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH	0x0
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-#define IXP4XX_GPIO_STYLE_ACTIVE_LOW	0x1
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-#define IXP4XX_GPIO_STYLE_RISING_EDGE	0x2
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-#define IXP4XX_GPIO_STYLE_FALLING_EDGE	0x3
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-#define IXP4XX_GPIO_STYLE_TRANSITIONAL	0x4
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-
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-/* 
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- * Mask used to clear interrupt styles 
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- */
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-#define IXP4XX_GPIO_STYLE_CLEAR		0x7
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-#define IXP4XX_GPIO_STYLE_SIZE		3
238140 
239141 /*
240142  * Constants to make it easy to access Timer Control/Status registers