update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/arm/boot/dts/qcom-mdm9615.dtsi
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@@ -45,8 +45,6 @@
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 /dts-v1/;
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-/include/ "skeleton.dtsi"
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-
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 #include <dt-bindings/interrupt-controller/arm-gic.h>
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 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
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 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
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@@ -54,6 +52,8 @@
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 #include <dt-bindings/soc/qcom,gsbi.h>
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 / {
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+	#address-cells = <1>;
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+	#size-cells = <1>;
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 	model = "Qualcomm MDM9615";
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 	compatible = "qcom,mdm9615";
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 	interrupt-parent = <&intc>;
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@@ -98,7 +98,7 @@
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 		ranges;
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 		compatible = "simple-bus";
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-		L2: l2-cache@2040000 {
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+		L2: cache-controller@2040000 {
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 			compatible = "arm,pl310-cache";
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 			reg = <0x02040000 0x1000>;
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 			arm,data-latency = <2 2 0>;
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@@ -128,6 +128,7 @@
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 		msmgpio: pinctrl@800000 {
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 			compatible = "qcom,mdm9615-pinctrl";
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 			gpio-controller;
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+			gpio-ranges = <&msmgpio 0 0 88>;
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 			#gpio-cells = <2>;
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 			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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 			interrupt-controller;
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@@ -323,14 +324,11 @@
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 				pmicgpio: gpio@150 {
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 					compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
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-					interrupt-parent = <&pmicintc>;
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-					interrupts = <24 IRQ_TYPE_NONE>,
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-						     <25 IRQ_TYPE_NONE>,
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-						     <26 IRQ_TYPE_NONE>,
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-						     <27 IRQ_TYPE_NONE>,
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-						     <28 IRQ_TYPE_NONE>,
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-						     <29 IRQ_TYPE_NONE>;
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+					reg = <0x150>;
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+					interrupt-controller;
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+					#interrupt-cells = <2>;
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 					gpio-controller;
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+					gpio-ranges = <&pmicgpio 0 0 6>;
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 					#gpio-cells = <2>;
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 				};
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 			};