~hc/RK356X_SDK_RELEASE.git

..	..	@@ -8,6 +8,7 @@
8	8	#include <dt-bindings/gpio/gpio.h>
9	9	#include <dt-bindings/input/input.h>
10	10	#include <dt-bindings/interrupt-controller/arm-gic.h>
	11	+#include <dt-bindings/reset/imx7-reset.h>
11	12	#include "imx7d-pinfunc.h"
12	13
13	14	/ {
..	..	@@ -46,11 +47,26 @@
46	47	spi1 = &ecspi2;
47	48	spi2 = &ecspi3;
48	49	spi3 = &ecspi4;
	50	+ usb0 = &usbotg1;
	51	+ usb1 = &usbh;
49	52	};
50	53
51	54	cpus {
52	55	#address-cells = <1>;
53	56	#size-cells = <0>;
	57	+
	58	+ idle-states {
	59	+ entry-method = "psci";
	60	+
	61	+ cpu_sleep_wait: cpu-sleep-wait {
	62	+ compatible = "arm,idle-state";
	63	+ arm,psci-suspend-param = <0x0010000>;
	64	+ local-timer-stop;
	65	+ entry-latency-us = <100>;
	66	+ exit-latency-us = <50>;
	67	+ min-residency-us = <1000>;
	68	+ };
	69	+ };
54	70
55	71	cpu0: cpu@0 {
56	72	compatible = "arm,cortex-a7";
..	..	@@ -59,6 +75,7 @@
59	75	clock-frequency = <792000000>;
60	76	clock-latency = <61036>; /* two CLK32 periods */
61	77	clocks = <&clks IMX7D_CLK_ARM>;
	78	+ cpu-idle-states = <&cpu_sleep_wait>;
62	79	};
63	80	};
64	81
..	..	@@ -87,6 +104,7 @@
87	104	compatible = "usb-nop-xceiv";
88	105	clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
89	106	clock-names = "main_clk";
	107	+ power-domains = <&pgc_hsic_phy>;
90	108	#phy-cells = <0>;
91	109	};
92	110
..	..	@@ -102,9 +120,9 @@
102	120	* non-configurable replicators don't show up on the
103	121	* AMBA bus. As such no need to add "arm,primecell"
104	122	*/
105		- compatible = "arm,coresight-replicator";
	123	+ compatible = "arm,coresight-static-replicator";
106	124
107		- ports {
	125	+ out-ports {
108	126	#address-cells = <1>;
109	127	#size-cells = <0>;
110	128	/* replicator output ports */
..	..	@@ -121,36 +139,24 @@
121	139	remote-endpoint = <&etr_in_port>;
122	140	};
123	141	};
	142	+ };
124	143
125		- /* replicator input port */
126		- port@2 {
127		- reg = <0>;
	144	+ in-ports {
	145	+ port {
128	146	replicator_in_port0: endpoint {
129		- slave-mode;
130	147	remote-endpoint = <&etf_out_port>;
131	148	};
132	149	};
133	150	};
134	151	};
135	152
136		- tempmon: tempmon {
137		- compatible = "fsl,imx7d-tempmon";
138		- interrupt-parent = <&gpc>;
139		- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
140		- fsl,tempmon =<&anatop>;
141		- nvmem-cells = <&tempmon_calib>,
142		- <&tempmon_temp_grade>;
143		- nvmem-cell-names = "calib", "temp_grade";
144		- clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
145		- };
146		-
147	153	timer {
148	154	compatible = "arm,armv7-timer";
149	155	interrupt-parent = <&intc>;
150		- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
151		- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
152		- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
153		- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	156	+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	157	+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	158	+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	159	+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>;
154	160	};
155	161
156	162	soc {
..	..	@@ -161,33 +167,28 @@
161	167	ranges;
162	168
163	169	funnel@30041000 {
164		- compatible = "arm,coresight-funnel", "arm,primecell";
	170	+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
165	171	reg = <0x30041000 0x1000>;
166	172	clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
167	173	clock-names = "apb_pclk";
168	174
169		- ca_funnel_ports: ports {
170		- #address-cells = <1>;
171		- #size-cells = <0>;
172		-
173		- /* funnel input ports */
174		- port@0 {
175		- reg = <0>;
	175	+ ca_funnel_in_ports: in-ports {
	176	+ port {
176	177	ca_funnel_in_port0: endpoint {
177		- slave-mode;
178	178	remote-endpoint = <&etm0_out_port>;
179	179	};
180	180	};
181	181
182		- /* funnel output port */
183		- port@2 {
184		- reg = <0>;
	182	+ /* the other input ports are not connect to anything */
	183	+ };
	184	+
	185	+ out-ports {
	186	+ port {
185	187	ca_funnel_out_port0: endpoint {
186	188	remote-endpoint = <&hugo_funnel_in_port0>;
187	189	};
188	190	};
189	191
190		- /* the other input ports are not connect to anything */
191	192	};
192	193	};
193	194
..	..	@@ -198,28 +199,28 @@
198	199	clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
199	200	clock-names = "apb_pclk";
200	201
201		- port {
202		- etm0_out_port: endpoint {
203		- remote-endpoint = <&ca_funnel_in_port0>;
	202	+ out-ports {
	203	+ port {
	204	+ etm0_out_port: endpoint {
	205	+ remote-endpoint = <&ca_funnel_in_port0>;
	206	+ };
204	207	};
205	208	};
206	209	};
207	210
208	211	funnel@30083000 {
209		- compatible = "arm,coresight-funnel", "arm,primecell";
	212	+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
210	213	reg = <0x30083000 0x1000>;
211	214	clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
212	215	clock-names = "apb_pclk";
213	216
214		- ports {
	217	+ in-ports {
215	218	#address-cells = <1>;
216	219	#size-cells = <0>;
217	220
218		- /* funnel input ports */
219	221	port@0 {
220	222	reg = <0>;
221	223	hugo_funnel_in_port0: endpoint {
222		- slave-mode;
223	224	remote-endpoint = <&ca_funnel_out_port0>;
224	225	};
225	226	};
..	..	@@ -227,18 +228,18 @@
227	228	port@1 {
228	229	reg = <1>;
229	230	hugo_funnel_in_port1: endpoint {
230		- slave-mode; /* M4 input */
	231	+ /* M4 input */
231	232	};
232	233	};
	234	+ /* the other input ports are not connect to anything */
	235	+ };
233	236
234		- port@2 {
235		- reg = <0>;
	237	+ out-ports {
	238	+ port {
236	239	hugo_funnel_out_port0: endpoint {
237	240	remote-endpoint = <&etf_in_port>;
238	241	};
239	242	};
240		-
241		- /* the other input ports are not connect to anything */
242	243	};
243	244	};
244	245
..	..	@@ -248,20 +249,16 @@
248	249	clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
249	250	clock-names = "apb_pclk";
250	251
251		- ports {
252		- #address-cells = <1>;
253		- #size-cells = <0>;
254		-
255		- port@0 {
256		- reg = <0>;
	252	+ in-ports {
	253	+ port {
257	254	etf_in_port: endpoint {
258		- slave-mode;
259	255	remote-endpoint = <&hugo_funnel_out_port0>;
260	256	};
261	257	};
	258	+ };
262	259
263		- port@1 {
264		- reg = <0>;
	260	+ out-ports {
	261	+ port {
265	262	etf_out_port: endpoint {
266	263	remote-endpoint = <&replicator_in_port0>;
267	264	};
..	..	@@ -275,10 +272,11 @@
275	272	clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
276	273	clock-names = "apb_pclk";
277	274
278		- port {
279		- etr_in_port: endpoint {
280		- slave-mode;
281		- remote-endpoint = <&replicator_out_port1>;
	275	+ in-ports {
	276	+ port {
	277	+ etr_in_port: endpoint {
	278	+ remote-endpoint = <&replicator_out_port1>;
	279	+ };
282	280	};
283	281	};
284	282	};
..	..	@@ -289,17 +287,18 @@
289	287	clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
290	288	clock-names = "apb_pclk";
291	289
292		- port {
293		- tpiu_in_port: endpoint {
294		- slave-mode;
295		- remote-endpoint = <&replicator_out_port0>;
	290	+ in-ports {
	291	+ port {
	292	+ tpiu_in_port: endpoint {
	293	+ remote-endpoint = <&replicator_out_port0>;
	294	+ };
296	295	};
297	296	};
298	297	};
299	298
300	299	intc: interrupt-controller@31001000 {
301	300	compatible = "arm,cortex-a7-gic";
302		- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	301	+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_HIGH)>;
303	302	#interrupt-cells = <3>;
304	303	interrupt-controller;
305	304	interrupt-parent = <&intc>;
..	..	@@ -309,7 +308,7 @@
309	308	<0x31006000 0x2000>;
310	309	};
311	310
312		- aips1: aips-bus@30000000 {
	311	+ aips1: bus@30000000 {
313	312	compatible = "fsl,aips-bus", "simple-bus";
314	313	#address-cells = <1>;
315	314	#size-cells = <1>;
..	..	@@ -400,14 +399,14 @@
400	399	gpio-ranges = <&iomuxc 0 139 16>;
401	400	};
402	401
403		- wdog1: wdog@30280000 {
	402	+ wdog1: watchdog@30280000 {
404	403	compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
405	404	reg = <0x30280000 0x10000>;
406	405	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
407	406	clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
408	407	};
409	408
410		- wdog2: wdog@30290000 {
	409	+ wdog2: watchdog@30290000 {
411	410	compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
412	411	reg = <0x30290000 0x10000>;
413	412	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -415,7 +414,7 @@
415	414	status = "disabled";
416	415	};
417	416
418		- wdog3: wdog@302a0000 {
	417	+ wdog3: watchdog@302a0000 {
419	418	compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
420	419	reg = <0x302a0000 0x10000>;
421	420	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -423,7 +422,7 @@
423	422	status = "disabled";
424	423	};
425	424
426		- wdog4: wdog@302b0000 {
	425	+ wdog4: watchdog@302b0000 {
427	426	compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
428	427	reg = <0x302b0000 0x10000>;
429	428	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -437,7 +436,7 @@
437	436	fsl,input-sel = <&iomuxc>;
438	437	};
439	438
440		- gpt1: gpt@302d0000 {
	439	+ gpt1: timer@302d0000 {
441	440	compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
442	441	reg = <0x302d0000 0x10000>;
443	442	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -446,7 +445,7 @@
446	445	clock-names = "ipg", "per";
447	446	};
448	447
449		- gpt2: gpt@302e0000 {
	448	+ gpt2: timer@302e0000 {
450	449	compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
451	450	reg = <0x302e0000 0x10000>;
452	451	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -456,7 +455,7 @@
456	455	status = "disabled";
457	456	};
458	457
459		- gpt3: gpt@302f0000 {
	458	+ gpt3: timer@302f0000 {
460	459	compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
461	460	reg = <0x302f0000 0x10000>;
462	461	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -466,7 +465,7 @@
466	465	status = "disabled";
467	466	};
468	467
469		- gpt4: gpt@30300000 {
	468	+ gpt4: timer@30300000 {
470	469	compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
471	470	reg = <0x30300000 0x10000>;
472	471	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -476,7 +475,7 @@
476	475	status = "disabled";
477	476	};
478	477
479		- kpp: kpp@30320000 {
	478	+ kpp: keypad@30320000 {
480	479	compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
481	480	reg = <0x30320000 0x10000>;
482	481	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -484,18 +483,53 @@
484	483	status = "disabled";
485	484	};
486	485
487		- iomuxc: iomuxc@30330000 {
	486	+ iomuxc: pinctrl@30330000 {
488	487	compatible = "fsl,imx7d-iomuxc";
489	488	reg = <0x30330000 0x10000>;
490	489	};
491	490
492	491	gpr: iomuxc-gpr@30340000 {
493	492	compatible = "fsl,imx7d-iomuxc-gpr",
494		- "fsl,imx6q-iomuxc-gpr", "syscon";
	493	+ "fsl,imx6q-iomuxc-gpr", "syscon",
	494	+ "simple-mfd";
495	495	reg = <0x30340000 0x10000>;
	496	+
	497	+ mux: mux-controller {
	498	+ compatible = "mmio-mux";
	499	+ #mux-control-cells = <1>;
	500	+ mux-reg-masks = <0x14 0x00000010>;
	501	+ };
	502	+
	503	+ video_mux: csi-mux {
	504	+ compatible = "video-mux";
	505	+ mux-controls = <&mux 0>;
	506	+ #address-cells = <1>;
	507	+ #size-cells = <0>;
	508	+ status = "disabled";
	509	+
	510	+ port@0 {
	511	+ reg = <0>;
	512	+ };
	513	+
	514	+ port@1 {
	515	+ reg = <1>;
	516	+
	517	+ csi_mux_from_mipi_vc0: endpoint {
	518	+ remote-endpoint = <&mipi_vc0_to_csi_mux>;
	519	+ };
	520	+ };
	521	+
	522	+ port@2 {
	523	+ reg = <2>;
	524	+
	525	+ csi_mux_to_csi: endpoint {
	526	+ remote-endpoint = <&csi_from_csi_mux>;
	527	+ };
	528	+ };
	529	+ };
496	530	};
497	531
498		- ocotp: ocotp-ctrl@30350000 {
	532	+ ocotp: efuse@30350000 {
499	533	#address-cells = <1>;
500	534	#size-cells = <1>;
501	535	compatible = "fsl,imx7d-ocotp", "syscon";
..	..	@@ -506,14 +540,14 @@
506	540	reg = <0x3c 0x4>;
507	541	};
508	542
509		- tempmon_temp_grade: temp-grade@10 {
	543	+ fuse_grade: fuse-grade@10 {
510	544	reg = <0x10 0x4>;
511	545	};
512	546	};
513	547
514	548	anatop: anatop@30360000 {
515	549	compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
516		- "syscon", "simple-bus";
	550	+ "syscon", "simple-mfd";
517	551	reg = <0x30360000 0x10000>;
518	552	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
519	553	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -545,6 +579,16 @@
545	579	anatop-max-voltage = <1300000>;
546	580	anatop-enable-bit = <0>;
547	581	};
	582	+
	583	+ tempmon: tempmon {
	584	+ compatible = "fsl,imx7d-tempmon";
	585	+ interrupt-parent = <&gpc>;
	586	+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	587	+ fsl,tempmon = <&anatop>;
	588	+ nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
	589	+ nvmem-cell-names = "calib", "temp_grade";
	590	+ clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
	591	+ };
548	592	};
549	593
550	594	snvs: snvs@30370000 {
..	..	@@ -561,24 +605,19 @@
561	605	clock-names = "snvs-rtc";
562	606	};
563	607
564		- snvs_poweroff: snvs-poweroff {
565		- compatible = "syscon-poweroff";
566		- regmap = <&snvs>;
567		- offset = <0x38>;
568		- value = <0x60>;
569		- mask = <0x60>;
570		- };
571		-
572	608	snvs_pwrkey: snvs-powerkey {
573	609	compatible = "fsl,sec-v4.0-pwrkey";
574	610	regmap = <&snvs>;
575	611	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	612	+ clocks = <&clks IMX7D_SNVS_CLK>;
	613	+ clock-names = "snvs-pwrkey";
576	614	linux,keycode = <KEY_POWER>;
577	615	wakeup-source;
	616	+ status = "disabled";
578	617	};
579	618	};
580	619
581		- clks: ccm@30380000 {
	620	+ clks: clock-controller@30380000 {
582	621	compatible = "fsl,imx7d-ccm";
583	622	reg = <0x30380000 0x10000>;
584	623	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
..	..	@@ -588,7 +627,7 @@
588	627	clock-names = "ckil", "osc";
589	628	};
590	629
591		- src: src@30390000 {
	630	+ src: reset-controller@30390000 {
592	631	compatible = "fsl,imx7d-src", "syscon";
593	632	reg = <0x30390000 0x10000>;
594	633	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -608,16 +647,28 @@
608	647	#address-cells = <1>;
609	648	#size-cells = <0>;
610	649
611		- pgc_pcie_phy: pgc-power-domain@1 {
	650	+ pgc_mipi_phy: power-domain@0 {
	651	+ #power-domain-cells = <0>;
	652	+ reg = <0>;
	653	+ power-supply = <&reg_1p0d>;
	654	+ };
	655	+
	656	+ pgc_pcie_phy: power-domain@1 {
612	657	#power-domain-cells = <0>;
613	658	reg = <1>;
614	659	power-supply = <&reg_1p0d>;
	660	+ };
	661	+
	662	+ pgc_hsic_phy: power-domain@2 {
	663	+ #power-domain-cells = <0>;
	664	+ reg = <2>;
	665	+ power-supply = <&reg_1p2>;
615	666	};
616	667	};
617	668	};
618	669	};
619	670
620		- aips2: aips-bus@30400000 {
	671	+ aips2: bus@30400000 {
621	672	compatible = "fsl,aips-bus", "simple-bus";
622	673	#address-cells = <1>;
623	674	#size-cells = <1>;
..	..	@@ -630,6 +681,7 @@
630	681	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
631	682	clocks = <&clks IMX7D_ADC_ROOT_CLK>;
632	683	clock-names = "adc";
	684	+ #io-channel-cells = <1>;
633	685	status = "disabled";
634	686	};
635	687
..	..	@@ -639,10 +691,11 @@
639	691	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
640	692	clocks = <&clks IMX7D_ADC_ROOT_CLK>;
641	693	clock-names = "adc";
	694	+ #io-channel-cells = <1>;
642	695	status = "disabled";
643	696	};
644	697
645		- ecspi4: ecspi@30630000 {
	698	+ ecspi4: spi@30630000 {
646	699	#address-cells = <1>;
647	700	#size-cells = <0>;
648	701	compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
..	..	@@ -698,6 +751,23 @@
698	751	status = "disabled";
699	752	};
700	753
	754	+ csi: csi@30710000 {
	755	+ compatible = "fsl,imx7-csi";
	756	+ reg = <0x30710000 0x10000>;
	757	+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	758	+ clocks = <&clks IMX7D_CLK_DUMMY>,
	759	+ <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
	760	+ <&clks IMX7D_CLK_DUMMY>;
	761	+ clock-names = "axi", "mclk", "dcic";
	762	+ status = "disabled";
	763	+
	764	+ port {
	765	+ csi_from_csi_mux: endpoint {
	766	+ remote-endpoint = <&csi_mux_to_csi>;
	767	+ };
	768	+ };
	769	+ };
	770	+
701	771	lcdif: lcdif@30730000 {
702	772	compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
703	773	reg = <0x30730000 0x10000>;
..	..	@@ -707,9 +777,38 @@
707	777	clock-names = "pix", "axi";
708	778	status = "disabled";
709	779	};
	780	+
	781	+ mipi_csi: mipi-csi@30750000 {
	782	+ compatible = "fsl,imx7-mipi-csi2";
	783	+ reg = <0x30750000 0x10000>;
	784	+ #address-cells = <1>;
	785	+ #size-cells = <0>;
	786	+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	787	+ clocks = <&clks IMX7D_IPG_ROOT_CLK>,
	788	+ <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
	789	+ <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
	790	+ clock-names = "pclk", "wrap", "phy";
	791	+ power-domains = <&pgc_mipi_phy>;
	792	+ phy-supply = <&reg_1p0d>;
	793	+ resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
	794	+ reset-names = "mrst";
	795	+ status = "disabled";
	796	+
	797	+ port@0 {
	798	+ reg = <0>;
	799	+ };
	800	+
	801	+ port@1 {
	802	+ reg = <1>;
	803	+
	804	+ mipi_vc0_to_csi_mux: endpoint {
	805	+ remote-endpoint = <&csi_mux_from_mipi_vc0>;
	806	+ };
	807	+ };
	808	+ };
710	809	};
711	810
712		- aips3: aips-bus@30800000 {
	811	+ aips3: bus@30800000 {
713	812	compatible = "fsl,aips-bus", "simple-bus";
714	813	#address-cells = <1>;
715	814	#size-cells = <1>;
..	..	@@ -723,7 +822,7 @@
723	822	reg = <0x30800000 0x100000>;
724	823	ranges;
725	824
726		- ecspi1: ecspi@30820000 {
	825	+ ecspi1: spi@30820000 {
727	826	#address-cells = <1>;
728	827	#size-cells = <0>;
729	828	compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
..	..	@@ -735,7 +834,7 @@
735	834	status = "disabled";
736	835	};
737	836
738		- ecspi2: ecspi@30830000 {
	837	+ ecspi2: spi@30830000 {
739	838	#address-cells = <1>;
740	839	#size-cells = <0>;
741	840	compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
..	..	@@ -747,7 +846,7 @@
747	846	status = "disabled";
748	847	};
749	848
750		- ecspi3: ecspi@30840000 {
	849	+ ecspi3: spi@30840000 {
751	850	#address-cells = <1>;
752	851	#size-cells = <0>;
753	852	compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
..	..	@@ -838,7 +937,7 @@
838	937	};
839	938	};
840	939
841		- crypto: caam@30900000 {
	940	+ crypto: crypto@30900000 {
842	941	compatible = "fsl,sec-v4.0";
843	942	#address-cells = <1>;
844	943	#size-cells = <1>;
..	..	@@ -849,19 +948,19 @@
849	948	<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
850	949	clock-names = "ipg", "aclk";
851	950
852		- sec_jr0: jr0@1000 {
	951	+ sec_jr0: jr@1000 {
853	952	compatible = "fsl,sec-v4.0-job-ring";
854	953	reg = <0x1000 0x1000>;
855	954	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
856	955	};
857	956
858		- sec_jr1: jr1@2000 {
	957	+ sec_jr1: jr@2000 {
859	958	compatible = "fsl,sec-v4.0-job-ring";
860	959	reg = <0x2000 0x1000>;
861	960	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
862	961	};
863	962
864		- sec_jr2: jr1@3000 {
	963	+ sec_jr2: jr@3000 {
865	964	compatible = "fsl,sec-v4.0-job-ring";
866	965	reg = <0x3000 0x1000>;
867	966	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -875,6 +974,7 @@
875	974	clocks = <&clks IMX7D_CLK_DUMMY>,
876	975	<&clks IMX7D_CAN1_ROOT_CLK>;
877	976	clock-names = "ipg", "per";
	977	+ fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
878	978	status = "disabled";
879	979	};
880	980
..	..	@@ -885,6 +985,7 @@
885	985	clocks = <&clks IMX7D_CLK_DUMMY>,
886	986	<&clks IMX7D_CAN2_ROOT_CLK>;
887	987	clock-names = "ipg", "per";
	988	+ fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
888	989	status = "disabled";
889	990	};
890	991
..	..	@@ -972,6 +1073,25 @@
972	1073	status = "disabled";
973	1074	};
974	1075
	1076	+ mu0a: mailbox@30aa0000 {
	1077	+ compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
	1078	+ reg = <0x30aa0000 0x10000>;
	1079	+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	1080	+ clocks = <&clks IMX7D_MU_ROOT_CLK>;
	1081	+ #mbox-cells = <2>;
	1082	+ status = "disabled";
	1083	+ };
	1084	+
	1085	+ mu0b: mailbox@30ab0000 {
	1086	+ compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
	1087	+ reg = <0x30ab0000 0x10000>;
	1088	+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	1089	+ clocks = <&clks IMX7D_MU_ROOT_CLK>;
	1090	+ #mbox-cells = <2>;
	1091	+ fsl,mu-side-b;
	1092	+ status = "disabled";
	1093	+ };
	1094	+
975	1095	usbotg1: usb@30b10000 {
976	1096	compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
977	1097	reg = <0x30b10000 0x200>;
..	..	@@ -1008,7 +1128,7 @@
1008	1128	reg = <0x30b30200 0x200>;
1009	1129	};
1010	1130
1011		- usdhc1: usdhc@30b40000 {
	1131	+ usdhc1: mmc@30b40000 {
1012	1132	compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1013	1133	reg = <0x30b40000 0x10000>;
1014	1134	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1017,10 +1137,12 @@
1017	1137	<&clks IMX7D_USDHC1_ROOT_CLK>;
1018	1138	clock-names = "ipg", "ahb", "per";
1019	1139	bus-width = <4>;
	1140	+ fsl,tuning-step = <2>;
	1141	+ fsl,tuning-start-tap = <20>;
1020	1142	status = "disabled";
1021	1143	};
1022	1144
1023		- usdhc2: usdhc@30b50000 {
	1145	+ usdhc2: mmc@30b50000 {
1024	1146	compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1025	1147	reg = <0x30b50000 0x10000>;
1026	1148	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1029,10 +1151,12 @@
1029	1151	<&clks IMX7D_USDHC2_ROOT_CLK>;
1030	1152	clock-names = "ipg", "ahb", "per";
1031	1153	bus-width = <4>;
	1154	+ fsl,tuning-step = <2>;
	1155	+ fsl,tuning-start-tap = <20>;
1032	1156	status = "disabled";
1033	1157	};
1034	1158
1035		- usdhc3: usdhc@30b60000 {
	1159	+ usdhc3: mmc@30b60000 {
1036	1160	compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1037	1161	reg = <0x30b60000 0x10000>;
1038	1162	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1041,10 +1165,25 @@
1041	1165	<&clks IMX7D_USDHC3_ROOT_CLK>;
1042	1166	clock-names = "ipg", "ahb", "per";
1043	1167	bus-width = <4>;
	1168	+ fsl,tuning-step = <2>;
	1169	+ fsl,tuning-start-tap = <20>;
1044	1170	status = "disabled";
1045	1171	};
1046	1172
1047		- sdma: sdma@30bd0000 {
	1173	+ qspi: spi@30bb0000 {
	1174	+ compatible = "fsl,imx7d-qspi";
	1175	+ reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
	1176	+ reg-names = "QuadSPI", "QuadSPI-memory";
	1177	+ #address-cells = <1>;
	1178	+ #size-cells = <0>;
	1179	+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	1180	+ clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
	1181	+ <&clks IMX7D_QSPI_ROOT_CLK>;
	1182	+ clock-names = "qspi_en", "qspi";
	1183	+ status = "disabled";
	1184	+ };
	1185	+
	1186	+ sdma: dma-controller@30bd0000 {
1048	1187	compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1049	1188	reg = <0x30bd0000 0x10000>;
1050	1189	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -1070,26 +1209,26 @@
1070	1209	<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1071	1210	clock-names = "ipg", "ahb", "ptp",
1072	1211	"enet_clk_ref", "enet_out";
1073		- fsl,num-tx-queues=<3>;
1074		- fsl,num-rx-queues=<3>;
	1212	+ fsl,num-tx-queues = <3>;
	1213	+ fsl,num-rx-queues = <3>;
	1214	+ fsl,stop-mode = <&gpr 0x10 3>;
1075	1215	status = "disabled";
1076	1216	};
1077	1217	};
1078	1218
1079		- dma_apbh: dma-apbh@33000000 {
	1219	+ dma_apbh: dma-controller@33000000 {
1080	1220	compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1081	1221	reg = <0x33000000 0x2000>;
1082	1222	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1083	1223	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1084	1224	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1085	1225	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1086		- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1087	1226	#dma-cells = <1>;
1088	1227	dma-channels = <4>;
1089	1228	clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1090	1229	};
1091	1230
1092		- gpmi: gpmi-nand@33002000{
	1231	+ gpmi: nand-controller@33002000{
1093	1232	compatible = "fsl,imx7d-gpmi-nand";
1094	1233	#address-cells = <1>;
1095	1234	#size-cells = <1>;