update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/arch/arm/boot/dts/highbank.dts
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@@ -1,17 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright 2011-2012 Calxeda, Inc.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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- * You should have received a copy of the GNU General Public License along with
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- * this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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 /dts-v1/;
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@@ -24,7 +13,6 @@
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 	compatible = "calxeda,highbank";
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 	#address-cells = <1>;
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 	#size-cells = <1>;
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-	clock-ranges;
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 	cpus {
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 		#address-cells = <1>;
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@@ -107,7 +95,7 @@
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 		};
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 	};
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-	memory {
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+	memory@0 {
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 		name = "memory";
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 		device_type = "memory";
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 		reg = <0x00000000 0xff900000>;
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@@ -139,14 +127,12 @@
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 		intc: interrupt-controller@fff11000 {
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 			compatible = "arm,cortex-a9-gic";
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 			#interrupt-cells = <3>;
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-			#size-cells = <0>;
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-			#address-cells = <1>;
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 			interrupt-controller;
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 			reg = <0xfff11000 0x1000>,
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 			      <0xfff10100 0x100>;
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 		};
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-		L2: l2-cache {
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+		L2: cache-controller {
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 			compatible = "arm,pl310-cache";
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 			reg = <0xfff12000 0x1000>;
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 			interrupts = <0 70 4>;
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@@ -156,14 +142,14 @@
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 		pmu {
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 			compatible = "arm,cortex-a9-pmu";
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-			interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
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+			interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
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 		};
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 		sregs@fff3c200 {
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 			compatible = "calxeda,hb-sregs-l2-ecc";
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 			reg = <0xfff3c200 0x100>;
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-			interrupts = <0 71 4  0 72 4>;
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+			interrupts = <0 71 4>, <0 72 4>;
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 		};
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 	};