| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | | - * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ |
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| 3 | | - * |
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| 4 | | - * This program is free software; you can redistribute it and/or modify |
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| 5 | | - * it under the terms of the GNU General Public License version 2 as |
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| 6 | | - * published by the Free Software Foundation. |
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| 3 | + * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/ |
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| 7 | 4 | */ |
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| 8 | 5 | /dts-v1/; |
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| 9 | 6 | |
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| 10 | 7 | #include "dra72x.dtsi" |
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| 8 | +#include "dra7-ipu-dsp-common.dtsi" |
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| 11 | 9 | #include <dt-bindings/gpio/gpio.h> |
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| 12 | | -#include <dt-bindings/clk/ti-dra7-atl.h> |
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| 10 | +#include <dt-bindings/clock/ti-dra7-atl.h> |
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| 13 | 11 | |
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| 14 | 12 | / { |
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| 15 | 13 | compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; |
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| .. | .. |
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| 190 | 188 | gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; |
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| 191 | 189 | enable-active-high; |
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| 192 | 190 | }; |
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| 191 | + |
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| 192 | + clk_ov5640_fixed: clock { |
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| 193 | + compatible = "fixed-clock"; |
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| 194 | + #clock-cells = <0>; |
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| 195 | + clock-frequency = <24000000>; |
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| 196 | + }; |
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| 193 | 197 | }; |
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| 194 | 198 | |
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| 195 | 199 | &dra7_pmx_core { |
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| .. | .. |
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| 272 | 276 | line-name = "vin6_sel_s0"; |
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| 273 | 277 | }; |
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| 274 | 278 | }; |
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| 279 | + |
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| 280 | + ov5640@3c { |
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| 281 | + compatible = "ovti,ov5640"; |
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| 282 | + reg = <0x3c>; |
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| 283 | + |
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| 284 | + clocks = <&clk_ov5640_fixed>; |
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| 285 | + clock-names = "xclk"; |
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| 286 | + |
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| 287 | + port { |
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| 288 | + csi2_cam0: endpoint { |
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| 289 | + remote-endpoint = <&csi2_phy0>; |
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| 290 | + clock-lanes = <0>; |
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| 291 | + data-lanes = <1 2>; |
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| 292 | + }; |
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| 293 | + }; |
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| 294 | + }; |
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| 295 | + |
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| 275 | 296 | }; |
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| 276 | 297 | |
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| 277 | 298 | &uart1 { |
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| .. | .. |
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| 441 | 462 | }; |
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| 442 | 463 | }; |
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| 443 | 464 | |
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| 444 | | -&mac { |
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| 445 | | - status = "okay"; |
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| 446 | | -}; |
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| 447 | | - |
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| 448 | 465 | &dcan1 { |
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| 449 | | - status = "ok"; |
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| 466 | + status = "okay"; |
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| 450 | 467 | pinctrl-names = "default", "sleep", "active"; |
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| 451 | 468 | pinctrl-0 = <&dcan1_pins_sleep>; |
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| 452 | 469 | pinctrl-1 = <&dcan1_pins_sleep>; |
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| .. | .. |
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| 515 | 532 | }; |
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| 516 | 533 | |
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| 517 | 534 | &dss { |
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| 518 | | - status = "ok"; |
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| 535 | + status = "okay"; |
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| 519 | 536 | }; |
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| 520 | 537 | |
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| 521 | 538 | &hdmi { |
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| 522 | | - status = "ok"; |
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| 539 | + status = "okay"; |
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| 523 | 540 | |
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| 524 | 541 | port { |
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| 525 | 542 | hdmi_out: endpoint { |
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| .. | .. |
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| 530 | 547 | |
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| 531 | 548 | &atl { |
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| 532 | 549 | assigned-clocks = <&abe_dpll_sys_clk_mux>, |
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| 533 | | - <&atl_clkctrl DRA7_ATL_CLKCTRL 26>, |
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| 550 | + <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>, |
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| 534 | 551 | <&dpll_abe_ck>, |
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| 535 | 552 | <&dpll_abe_m2x2_ck>, |
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| 536 | 553 | <&atl_clkin2_ck>; |
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| .. | .. |
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| 548 | 565 | &mcasp3 { |
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| 549 | 566 | #sound-dai-cells = <0>; |
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| 550 | 567 | |
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| 551 | | - assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>; |
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| 568 | + assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; |
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| 552 | 569 | assigned-clock-parents = <&atl_clkin2_ck>; |
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| 553 | 570 | |
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| 554 | 571 | status = "okay"; |
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| .. | .. |
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| 563 | 580 | rx-num-evt = <32>; |
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| 564 | 581 | }; |
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| 565 | 582 | |
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| 566 | | -&mailbox5 { |
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| 567 | | - status = "okay"; |
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| 568 | | - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { |
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| 569 | | - status = "okay"; |
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| 570 | | - }; |
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| 571 | | - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { |
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| 572 | | - status = "okay"; |
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| 573 | | - }; |
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| 574 | | -}; |
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| 575 | | - |
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| 576 | | -&mailbox6 { |
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| 577 | | - status = "okay"; |
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| 578 | | - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { |
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| 579 | | - status = "okay"; |
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| 580 | | - }; |
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| 581 | | -}; |
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| 582 | | - |
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| 583 | 583 | &pcie1_rc { |
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| 584 | 584 | status = "okay"; |
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| 585 | 585 | }; |
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| 586 | + |
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| 587 | +&csi2_0 { |
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| 588 | + csi2_phy0: endpoint { |
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| 589 | + remote-endpoint = <&csi2_cam0>; |
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| 590 | + clock-lanes = <0>; |
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| 591 | + data-lanes = <1 2>; |
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| 592 | + }; |
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| 593 | +}; |
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