.. | .. |
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4 | 4 | |
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5 | 5 | - compatible Should be "fsl,etsec-ptp" for eTSEC |
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6 | 6 | Should be "fsl,fman-ptp-timer" for DPAA FMan |
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| 7 | + Should be "fsl,dpaa2-ptp" for DPAA2 |
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| 8 | + Should be "fsl,enetc-ptp" for ENETC |
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7 | 9 | - reg Offset and length of the register set for the device |
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8 | 10 | - interrupts There should be at least two interrupts. Some devices |
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9 | 11 | have as many as four PTP related interrupts. |
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.. | .. |
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16 | 18 | - fsl,tmr-add Frequency compensation value. |
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17 | 19 | - fsl,tmr-fiper1 Fixed interval period pulse generator. |
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18 | 20 | - fsl,tmr-fiper2 Fixed interval period pulse generator. |
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| 21 | + - fsl,tmr-fiper3 Fixed interval period pulse generator. |
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| 22 | + Supported only on DPAA2 and ENETC hardware. |
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19 | 23 | - fsl,max-adj Maximum frequency adjustment in parts per billion. |
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| 24 | + - fsl,extts-fifo The presence of this property indicates hardware |
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| 25 | + support for the external trigger stamp FIFO. |
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| 26 | + - little-endian The presence of this property indicates the 1588 timer |
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| 27 | + IP block is little-endian mode. The default endian mode |
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| 28 | + is big-endian. |
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20 | 29 | |
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21 | 30 | These properties set the operational parameters for the PTP |
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22 | 31 | clock. You must choose these carefully for the clock to work right. |
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