update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/Documentation/devicetree/bindings/pci/pci-keystone.txt
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@@ -11,13 +11,24 @@
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 Required Properties:-
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-compatibility: "ti,keystone-pcie"
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-reg:	index 1 is the base address and length of DW application registers.
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-	index 2 is the base address and length of PCI device ID register.
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+compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
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+	       Should be "ti,am654-pcie-rc" for RC on AM654x SoC
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+reg: Three register ranges as listed in the reg-names property
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+reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
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+	   TI specific application registers, "config" for the
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+	   configuration space address
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 pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
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 	interrupt-cells: should be set to 1
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 	interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
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+	(required if the compatible is "ti,keystone-pcie")
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+msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt
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+	 (required if the compatible is "ti,am654-pcie-rc".
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+
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+ti,syscon-pcie-id : phandle to the device control module required to set device
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+		    id and vendor id.
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+ti,syscon-pcie-mode : phandle to the device control module required to configure
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+		      PCI in either RC mode or EP mode.
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  Example:
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 	pcie_msi_intc: msi-interrupt-controller {
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@@ -58,3 +69,47 @@
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 DesignWare DT Properties not applicable for Keystone PCI
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 1. pcie_bus clock-names not used.  Instead, a phandle to phys is used.
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+
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+AM654 PCIe Endpoint
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+===================
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+
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+Required Properties:-
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+
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+compatibility: Should be "ti,am654-pcie-ep" for EP on AM654x SoC
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+reg: Four register ranges as listed in the reg-names property
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+reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
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+	   TI specific application registers, "atu" for the
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+	   Address Translation Unit configuration registers and
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+	   "addr_space" used to map remote RC address space
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+num-ib-windows: As specified in
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+		Documentation/devicetree/bindings/pci/designware-pcie.txt
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+num-ob-windows: As specified in
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+		Documentation/devicetree/bindings/pci/designware-pcie.txt
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+num-lanes: As specified in
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+	   Documentation/devicetree/bindings/pci/designware-pcie.txt
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+power-domains: As documented by the generic PM domain bindings in
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+	       Documentation/devicetree/bindings/power/power_domain.txt.
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+ti,syscon-pcie-mode: phandle to the device control module required to configure
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+		      PCI in either RC mode or EP mode.
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+
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+Optional properties:-
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+
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+phys: list of PHY specifiers (used by generic PHY framework)
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+phy-names: must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
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+               number of lanes as specified in *num-lanes* property.
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+("phys" and "phy-names" DT bindings are specified in
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+Documentation/devicetree/bindings/phy/phy-bindings.txt)
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+interrupts: platform interrupt for error interrupts.
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+
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+pcie-ep {
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+	compatible = "ti,am654-pcie-ep";
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+	reg =  <0x5500000 0x1000>, <0x5501000 0x1000>,
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+	       <0x10000000 0x8000000>, <0x5506000 0x1000>;
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+	reg-names = "app", "dbics", "addr_space", "atu";
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+	power-domains = <&k3_pds 120>;
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+	ti,syscon-pcie-mode = <&pcie0_mode>;
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+	num-lanes = <1>;
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+	num-ib-windows = <16>;
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+	num-ob-windows = <16>;
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+	interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
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+};