update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
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-OMAP2+ Mailbox Driver
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+OMAP2+ and K3 Mailbox
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 =====================
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 The OMAP mailbox hardware facilitates communication between different processors
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 communication is achieved through a set of registers for message storage and
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 interrupt configuration registers.
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-Each mailbox IP block has a certain number of h/w fifo queues and output
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+Each mailbox IP block/cluster has a certain number of h/w fifo queues and output
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 interrupt lines. An output interrupt line is routed to an interrupt controller
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 within a processor subsystem, and there can be more than one line going to a
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 specific processor's interrupt controller. The interrupt line connections are
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 instance. DRA7xx has multiple instances with different number of h/w fifo queues
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 and interrupt lines between different instances. The interrupt lines can also be
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 routed to different processor sub-systems on DRA7xx as they are routed through
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-the Crossbar, a kind of interrupt router/multiplexer.
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+the Crossbar, a kind of interrupt router/multiplexer. The K3 AM65x and J721E
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+SoCs has each of these instances form a cluster and combine multiple clusters
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+into a single IP block present within the Main NavSS. The interrupt lines from
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+all these clusters are multiplexed and routed to different processor subsystems
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+over a limited number of common interrupt output lines of an Interrupt Router.
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 Mailbox Device Node:
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 ====================
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-A Mailbox device node is used to represent a Mailbox IP instance within a SoC.
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-The sub-mailboxes are represented as child nodes of this parent node.
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+A Mailbox device node is used to represent a Mailbox IP instance/cluster within
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+a SoC. The sub-mailboxes are represented as child nodes of this parent node.
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 Required properties:
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 --------------------
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 			    "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
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 			    "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
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 						   AM43xx and DRA7xx SoCs
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+			    "ti,am654-mailbox" for K3 AM65x and J721E SoCs
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 - reg:			Contains the mailbox register address range (base
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 			address and length)
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 - interrupts:		Contains the interrupt information for the mailbox
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 			device. The format is dependent on which interrupt
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-			controller the OMAP device uses
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-- ti,hwmods:		Name of the hwmod associated with the mailbox
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+			controller the Mailbox device uses
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 - #mbox-cells:		Common mailbox binding property to identify the number
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 			of cells required for the mailbox specifier. Should be
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 			1
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 - ti,mbox-num-users:	Number of targets (processor devices) that the mailbox
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 			device can interrupt
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 - ti,mbox-num-fifos:	Number of h/w fifo queues within the mailbox IP block
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+
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+SoC-specific Required properties:
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+---------------------------------
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+The following are mandatory properties for the OMAP architecture based SoCs
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+only:
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+- ti,hwmods:		Name of the hwmod associated with the mailbox. This
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+			should be defined in the mailbox node only if the node
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+			is not defined as a child node of a corresponding sysc
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+			interconnect node.
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+
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+The following are mandatory properties for the K3 AM65x and J721E SoCs only:
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+- interrupt-parent:	Should contain a phandle to the TI-SCI interrupt
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+			controller node that is used to dynamically program
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+			the interrupt routes between the IP and the main GIC
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+			controllers. See the following binding for additional
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+			details,
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+			Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
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 Child Nodes:
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 ============
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 Example:
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 --------
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-/* OMAP4 */
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+1. /* OMAP4 */
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 mailbox: mailbox@4a0f4000 {
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 	compatible = "ti,omap4-mailbox";
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 	reg = <0x4a0f4000 0x200>;
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 	...
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 };
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-/* AM33xx */
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+2. /* AM33xx */
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 mailbox: mailbox@480c8000 {
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 	compatible = "ti,omap4-mailbox";
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 	reg = <0x480C8000 0x200>;
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 		ti,mbox-rx = <0 0 3>;
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 	};
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 };
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+
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+3. /* AM65x */
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+&cbass_main {
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+	cbass_main_navss: interconnect0 {
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+		mailbox0_cluster0: mailbox@31f80000 {
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+			compatible = "ti,am654-mailbox";
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+			reg = <0x00 0x31f80000 0x00 0x200>;
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+			#mbox-cells = <1>;
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+			ti,mbox-num-users = <4>;
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+			ti,mbox-num-fifos = <16>;
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+			interrupt-parent = <&intr_main_navss>;
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+			interrupts = <164 0>;
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+
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+			mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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+				ti,mbox-tx = <1 0 0>;
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+				ti,mbox-rx = <0 0 0>;
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+			};
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+		};
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+	};
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+};