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2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/Documentation/devicetree/bindings/arm/coresight.txt
....@@ -8,7 +8,8 @@
88 sink. Each CoreSight component device should use these properties to describe
99 its hardware characteristcs.
1010 
11
-* Required properties for all components *except* non-configurable replicators:
11
+* Required properties for all components *except* non-configurable replicators
12
+  and non-configurable funnels:
1213 
1314 	* compatible: These have to be supplemented with "arm,primecell" as
1415 	  drivers are using the AMBA bus interface.  Possible values include:
....@@ -24,15 +25,20 @@
2425 		  discovered at boot time when the device is probed.
2526 			"arm,coresight-tmc", "arm,primecell";
2627 
27
-		- Trace Funnel:
28
-			"arm,coresight-funnel", "arm,primecell";
28
+		- Trace Programmable Funnel:
29
+			"arm,coresight-dynamic-funnel", "arm,primecell";
30
+			"arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For
31
+				backward compatibility and will be removed)
2932 
3033 		- Embedded Trace Macrocell (version 3.x) and
3134 					Program Flow Trace Macrocell:
3235 			"arm,coresight-etm3x", "arm,primecell";
3336 
34
-		- Embedded Trace Macrocell (version 4.x):
37
+		- Embedded Trace Macrocell (version 4.x), with memory mapped access.
3538 			"arm,coresight-etm4x", "arm,primecell";
39
+
40
+		- Embedded Trace Macrocell (version 4.x), with system register access only.
41
+			"arm,coresight-etm4x-sysreg";
3642 
3743 		- Coresight programmable Replicator :
3844 			"arm,coresight-dynamic-replicator", "arm,primecell";
....@@ -41,6 +47,10 @@
4147 			"arm,coresight-stm", "arm,primecell"; [1]
4248 		- Coresight Address Translation Unit (CATU)
4349 			"arm,coresight-catu", "arm,primecell";
50
+
51
+		- Coresight Cross Trigger Interface (CTI):
52
+			"arm,coresight-cti", "arm,primecell";
53
+			See coresight-cti.yaml for full CTI definitions.
4454 
4555 	* reg: physical base address and length of the register
4656 	  set(s) of the component.
....@@ -54,9 +64,12 @@
5464 	  clocks the core of that coresight component. The latter clock
5565 	  is optional.
5666 
57
-	* port or ports: The representation of the component's port
58
-	  layout using the generic DT graph presentation found in
59
-	  "bindings/graph.txt".
67
+	* port or ports: see "Graph bindings for Coresight" below.
68
+
69
+* Additional required property for Embedded Trace Macrocell (version 3.x and
70
+  version 4.x):
71
+	* cpu: the cpu phandle this ETM/PTM is affined to. Do not
72
+	  assume it to default to CPU0 if omitted.
6073 
6174 * Additional required properties for System Trace Macrocells (STM):
6275 	* reg: along with the physical base address and length of the register
....@@ -66,14 +79,23 @@
6679 	* reg-names: the only acceptable values are "stm-base" and
6780 	  "stm-stimulus-base", each corresponding to the areas defined in "reg".
6881 
82
+* Required properties for Coresight Cross Trigger Interface (CTI)
83
+	See coresight-cti.yaml for full CTI definitions.
84
+
6985 * Required properties for devices that don't show up on the AMBA bus, such as
70
-  non-configurable replicators:
86
+  non-configurable replicators and non-configurable funnels:
7187 
7288 	* compatible: Currently supported value is (note the absence of the
7389 	  AMBA markee):
74
-		- "arm,coresight-replicator"
90
+		- Coresight Non-configurable Replicator:
91
+			"arm,coresight-static-replicator";
92
+			"arm,coresight-replicator"; (OBSOLETE. For backward
93
+				compatibility and will be removed)
7594 
76
-	* port or ports: same as above.
95
+		- Coresight Non-configurable Funnel:
96
+			"arm,coresight-static-funnel";
97
+
98
+	* port or ports: see "Graph bindings for Coresight" below.
7799 
78100 * Optional properties for all components:
79101 
....@@ -89,8 +111,12 @@
89111 	* arm,cp14: must be present if the system accesses ETM/PTM management
90112 	  registers via co-processor 14.
91113 
92
-	* cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
93
-	  source is considered to belong to CPU0.
114
+	* qcom,skip-power-up: boolean. Indicates that an implementation can
115
+	  skip powering up the trace unit. TRCPDCR.PU does not have to be set
116
+	  on Qualcomm Technologies Inc. systems since ETMs are in the same power
117
+	  domain as their CPU cores. This property is required to identify such
118
+	  systems with hardware errata where the CPU watchdog counter is stopped
119
+	  when TRCPDCR.PU is set.
94120 
95121 * Optional property for TMC:
96122 
....@@ -105,6 +131,26 @@
105131 	* interrupts : Exactly one SPI may be listed for reporting the address
106132 	  error
107133 
134
+* Optional property for configurable replicators:
135
+
136
+	* qcom,replicator-loses-context: boolean. Indicates that the replicator
137
+	  will lose register context when AMBA clock is removed which is observed
138
+	  in some replicator designs.
139
+
140
+Graph bindings for Coresight
141
+-------------------------------
142
+
143
+Coresight components are interconnected to create a data path for the flow of
144
+trace data generated from the "sources" to their collection points "sink".
145
+Each coresight component must describe the "input" and "output" connections.
146
+The connections must be described via generic DT graph bindings as described
147
+by the "bindings/graph.txt", where each "port" along with an "endpoint"
148
+component represents a hardware port and the connection.
149
+
150
+ * All output ports must be listed inside a child node named "out-ports"
151
+ * All input ports must be listed inside a child node named "in-ports".
152
+ * Port address must match the hardware port number.
153
+
108154 Example:
109155 
110156 1. Sinks
....@@ -114,10 +160,11 @@
114160 
115161 		clocks = <&oscclk6a>;
116162 		clock-names = "apb_pclk";
117
-		port {
118
-			etb_in_port: endpoint@0 {
119
-				slave-mode;
120
-				remote-endpoint = <&replicator_out_port0>;
163
+		in-ports {
164
+			port {
165
+				etb_in_port: endpoint@0 {
166
+					remote-endpoint = <&replicator_out_port0>;
167
+				};
121168 			};
122169 		};
123170 	};
....@@ -128,10 +175,11 @@
128175 
129176 		clocks = <&oscclk6a>;
130177 		clock-names = "apb_pclk";
131
-		port {
132
-			tpiu_in_port: endpoint@0 {
133
-				slave-mode;
134
-				remote-endpoint = <&replicator_out_port1>;
178
+		in-ports {
179
+			port {
180
+				tpiu_in_port: endpoint@0 {
181
+					remote-endpoint = <&replicator_out_port1>;
182
+				};
135183 			};
136184 		};
137185 	};
....@@ -142,22 +190,16 @@
142190 
143191 		clocks = <&oscclk6a>;
144192 		clock-names = "apb_pclk";
145
-		ports {
146
-			#address-cells = <1>;
147
-			#size-cells = <0>;
148
-
149
-			/* input port */
150
-			port@0 {
151
-				reg =  <0>;
193
+		in-ports {
194
+			port {
152195 				etr_in_port: endpoint {
153
-					slave-mode;
154196 					remote-endpoint = <&replicator2_out_port0>;
155197 				};
156198 			};
199
+		};
157200 
158
-			/* CATU link represented by output port */
159
-			port@1 {
160
-				reg = <1>;
201
+		out-ports {
202
+			port {
161203 				etr_out_port: endpoint {
162204 					remote-endpoint = <&catu_in_port>;
163205 				};
....@@ -170,9 +212,9 @@
170212 		/* non-configurable replicators don't show up on the
171213 		 * AMBA bus.  As such no need to add "arm,primecell".
172214 		 */
173
-		compatible = "arm,coresight-replicator";
215
+		compatible = "arm,coresight-static-replicator";
174216 
175
-		ports {
217
+		out-ports {
176218 			#address-cells = <1>;
177219 			#size-cells = <0>;
178220 
....@@ -190,58 +232,90 @@
190232 					remote-endpoint = <&tpiu_in_port>;
191233 				};
192234 			};
235
+		};
193236 
194
-			/* replicator input port */
195
-			port@2 {
196
-				reg = <0>;
237
+		in-ports {
238
+			port {
197239 				replicator_in_port0: endpoint {
198
-					slave-mode;
199240 					remote-endpoint = <&funnel_out_port0>;
200241 				};
201242 			};
202243 		};
203244 	};
204245 
246
+	funnel {
247
+		/*
248
+		 * non-configurable funnel don't show up on the AMBA
249
+		 * bus.  As such no need to add "arm,primecell".
250
+		 */
251
+		compatible = "arm,coresight-static-funnel";
252
+		clocks = <&crg_ctrl HI3660_PCLK>;
253
+		clock-names = "apb_pclk";
254
+
255
+		out-ports {
256
+			port {
257
+				combo_funnel_out: endpoint {
258
+					remote-endpoint = <&top_funnel_in>;
259
+				};
260
+			};
261
+		};
262
+
263
+		in-ports {
264
+			#address-cells = <1>;
265
+			#size-cells = <0>;
266
+
267
+			port@0 {
268
+				reg = <0>;
269
+				combo_funnel_in0: endpoint {
270
+					remote-endpoint = <&cluster0_etf_out>;
271
+				};
272
+			};
273
+
274
+			port@1 {
275
+				reg = <1>;
276
+				combo_funnel_in1: endpoint {
277
+					remote-endpoint = <&cluster1_etf_out>;
278
+				};
279
+			};
280
+		};
281
+	};
282
+
205283 	funnel@20040000 {
206
-		compatible = "arm,coresight-funnel", "arm,primecell";
284
+		compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
207285 		reg = <0 0x20040000 0 0x1000>;
208286 
209287 		clocks = <&oscclk6a>;
210288 		clock-names = "apb_pclk";
211
-		ports {
212
-			#address-cells = <1>;
213
-			#size-cells = <0>;
214
-
215
-			/* funnel output port */
216
-			port@0 {
217
-				reg = <0>;
289
+		out-ports {
290
+			port {
218291 				funnel_out_port0: endpoint {
219292 					remote-endpoint =
220293 							<&replicator_in_port0>;
221294 				};
222295 			};
296
+		};
223297 
224
-			/* funnel input ports */
225
-			port@1 {
298
+		in-ports {
299
+			#address-cells = <1>;
300
+			#size-cells = <0>;
301
+
302
+			port@0 {
226303 				reg = <0>;
227304 				funnel_in_port0: endpoint {
228
-					slave-mode;
229305 					remote-endpoint = <&ptm0_out_port>;
230306 				};
231307 			};
232308 
233
-			port@2 {
309
+			port@1 {
234310 				reg = <1>;
235311 				funnel_in_port1: endpoint {
236
-					slave-mode;
237312 					remote-endpoint = <&ptm1_out_port>;
238313 				};
239314 			};
240315 
241
-			port@3 {
316
+			port@2 {
242317 				reg = <2>;
243318 				funnel_in_port2: endpoint {
244
-					slave-mode;
245319 					remote-endpoint = <&etm0_out_port>;
246320 				};
247321 			};
....@@ -257,9 +331,11 @@
257331 		cpu = <&cpu0>;
258332 		clocks = <&oscclk6a>;
259333 		clock-names = "apb_pclk";
260
-		port {
261
-			ptm0_out_port: endpoint {
262
-				remote-endpoint = <&funnel_in_port0>;
334
+		out-ports {
335
+			port {
336
+				ptm0_out_port: endpoint {
337
+					remote-endpoint = <&funnel_in_port0>;
338
+				};
263339 			};
264340 		};
265341 	};
....@@ -271,9 +347,11 @@
271347 		cpu = <&cpu1>;
272348 		clocks = <&oscclk6a>;
273349 		clock-names = "apb_pclk";
274
-		port {
275
-			ptm1_out_port: endpoint {
276
-				remote-endpoint = <&funnel_in_port1>;
350
+		out-ports {
351
+			port {
352
+				ptm1_out_port: endpoint {
353
+					remote-endpoint = <&funnel_in_port1>;
354
+				};
277355 			};
278356 		};
279357 	};
....@@ -287,9 +365,11 @@
287365 
288366 		clocks = <&soc_smc50mhz>;
289367 		clock-names = "apb_pclk";
290
-		port {
291
-			stm_out_port: endpoint {
292
-				remote-endpoint = <&main_funnel_in_port2>;
368
+		out-ports {
369
+			port {
370
+				stm_out_port: endpoint {
371
+					remote-endpoint = <&main_funnel_in_port2>;
372
+				};
293373 			};
294374 		};
295375 	};
....@@ -304,10 +384,11 @@
304384 		clock-names = "apb_pclk";
305385 
306386 		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
307
-		port {
308
-			catu_in_port: endpoint {
309
-				slave-mode;
310
-				remote-endpoint = <&etr_out_port>;
387
+		in-ports {
388
+			port {
389
+				catu_in_port: endpoint {
390
+					remote-endpoint = <&etr_out_port>;
391
+				};
311392 			};
312393 		};
313394 	};