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2023-11-20 2e7bd41e4e8ab3d1efdabd9e263a2f7fe79bff8c

 kernel/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
..
..
@@ -228,7 +228,7 @@
228
228
 			priv->clk_csr = STMMAC_CSR_100_150M;
229
229
 		else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
230
230
 			priv->clk_csr = STMMAC_CSR_150_250M;
231
-		else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
231
+		else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
232
232
 			priv->clk_csr = STMMAC_CSR_250_300M;
233
233
 	}
234
234
 
..
..
@@ -508,6 +508,7 @@
508
508
 	}
509
509
 }
510
510
 
511
+#ifdef CONFIG_STMMAC_PTP
511
512
 /**
512
513
  *  stmmac_hwtstamp_set - control hardware timestamping.
513
514
  *  @dev: device pointer.
..
..
@@ -760,6 +761,7 @@
760
761
 	return copy_to_user(ifr->ifr_data, config,
761
762
 			    sizeof(*config)) ? -EFAULT : 0;
762
763
 }
764
+#endif /* CONFIG_STMMAC_PTP */
763
765
 
764
766
 /**
765
767
  * stmmac_init_ptp - init PTP
..
..
@@ -800,7 +802,7 @@
800
802
 
801
803
 static void stmmac_release_ptp(struct stmmac_priv *priv)
802
804
 {
803
-	if (priv->plat->clk_ptp_ref)
805
+	if (priv->plat->clk_ptp_ref && IS_ENABLED(CONFIG_STMMAC_PTP))
804
806
 		clk_disable_unprepare(priv->plat->clk_ptp_ref);
805
807
 	stmmac_ptp_unregister(priv);
806
808
 }
..
..
@@ -934,23 +936,6 @@
934
936
 	}
935
937
 }
936
938
 
937
-static void rtl8211F_led_control(struct phy_device *phydev)
938
-{
939
-	printk("ben debug:rtl8211F_led_control...1 \n");
940
-
941
-       	if(!phydev) return;
942
-       	if(phydev->phy_id!=0x001cc916) return; /* only for 8211E*/
943
-
944
-       	/*switch to extension page44*/
945
-	phy_write(phydev, 31, 0x0d04);
946
-//add hc 1000M --> orange   
947
-//	 100M  --> green
948
-	phy_write(phydev, 16, 0x6D02);  
949
-//add hc 1000M&100M  --> green
950
-//     	phy_write(phydev, 16, 0x6C0A); 
951
-	printk("ben debug:rtl8211F_led_control...2 \n");
952
-}
953
-
954
939
 /**
955
940
  * stmmac_init_phy - PHY initialization
956
941
  * @dev: net device structure
..
..
@@ -971,6 +956,9 @@
971
956
 	priv->oldlink = false;
972
957
 	priv->speed = SPEED_UNKNOWN;
973
958
 	priv->oldduplex = DUPLEX_UNKNOWN;
959
+
960
+	if (priv->plat->integrated_phy_power)
961
+		priv->plat->integrated_phy_power(priv->plat->bsp_priv, true);
974
962
 
975
963
 	if (priv->plat->phy_node) {
976
964
 		phydev = of_phy_connect(dev, priv->plat->phy_node,
..
..
@@ -1032,9 +1020,6 @@
1032
1020
 		phydev->irq = PHY_POLL;
1033
1021
 
1034
1022
 	phy_attached_info(phydev);
1035
-
1036
-	//add ben
1037
-	rtl8211F_led_control(phydev);
1038
1023
 	return 0;
1039
1024
 }
1040
1025
 
..
..
@@ -2174,8 +2159,8 @@
2174
2159
  */
2175
2160
 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2176
2161
 {
2177
-	//if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2178
-	if (1) {
2162
+//	if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2163
+	if(1) {
2179
2164
 		stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2180
2165
 		if (likely(priv->plat->get_eth_addr))
2181
2166
 			priv->plat->get_eth_addr(priv->plat->bsp_priv,
..
..
@@ -2568,7 +2553,7 @@
2568
2553
 
2569
2554
 	stmmac_mmc_setup(priv);
2570
2555
 
2571
-	if (init_ptp) {
2556
+	if (IS_ENABLED(CONFIG_STMMAC_PTP) && init_ptp) {
2572
2557
 		ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2573
2558
 		if (ret < 0)
2574
2559
 			netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
..
..
@@ -2610,7 +2595,8 @@
2610
2595
 {
2611
2596
 	struct stmmac_priv *priv = netdev_priv(dev);
2612
2597
 
2613
-	clk_disable_unprepare(priv->plat->clk_ptp_ref);
2598
+	if (IS_ENABLED(CONFIG_STMMAC_PTP))
2599
+		clk_disable_unprepare(priv->plat->clk_ptp_ref);
2614
2600
 }
2615
2601
 
2616
2602
 /**
..
..
@@ -2748,6 +2734,9 @@
2748
2734
 	if (dev->phydev) {
2749
2735
 		phy_stop(dev->phydev);
2750
2736
 		phy_disconnect(dev->phydev);
2737
+		if (priv->plat->integrated_phy_power)
2738
+			priv->plat->integrated_phy_power(priv->plat->bsp_priv,
2739
+							 false);
2751
2740
 	}
2752
2741
 
2753
2742
 	stmmac_disable_all_queues(priv);
..
..
@@ -2778,7 +2767,8 @@
2778
2767
 
2779
2768
 	netif_carrier_off(dev);
2780
2769
 
2781
-	stmmac_release_ptp(priv);
2770
+	if (IS_ENABLED(CONFIG_STMMAC_PTP))
2771
+		stmmac_release_ptp(priv);
2782
2772
 
2783
2773
 	return 0;
2784
2774
 }
..
..
@@ -3757,7 +3747,6 @@
3757
3747
 	/* To handle GMAC own interrupts */
3758
3748
 	if ((priv->plat->has_gmac) || xmac) {
3759
3749
 		int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3760
-		int mtl_status;
3761
3750
 
3762
3751
 		if (unlikely(status)) {
3763
3752
 			/* For LPI we need to save the tx status */
..
..
@@ -3768,17 +3757,8 @@
3768
3757
 		}
3769
3758
 
3770
3759
 		for (queue = 0; queue < queues_count; queue++) {
3771
-			struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3772
-
3773
-			mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3774
-								queue);
3775
-			if (mtl_status != -EINVAL)
3776
-				status |= mtl_status;
3777
-
3778
-			if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3779
-				stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3780
-						       rx_q->rx_tail_addr,
3781
-						       queue);
3760
+			status = stmmac_host_mtl_irq_status(priv, priv->hw,
3761
+							    queue);
3782
3762
 		}
3783
3763
 
3784
3764
 		/* PCS link status */
..
..
@@ -3832,12 +3812,14 @@
3832
3812
 			return -EINVAL;
3833
3813
 		ret = phy_mii_ioctl(dev->phydev, rq, cmd);
3834
3814
 		break;
3815
+#ifdef CONFIG_STMMAC_PTP
3835
3816
 	case SIOCSHWTSTAMP:
3836
3817
 		ret = stmmac_hwtstamp_set(dev, rq);
3837
3818
 		break;
3838
3819
 	case SIOCGHWTSTAMP:
3839
3820
 		ret = stmmac_hwtstamp_get(dev, rq);
3840
3821
 		break;
3822
+#endif
3841
3823
 	default:
3842
3824
 		break;
3843
3825
 	}
..
..
@@ -4584,10 +4566,13 @@
4584
4566
 		stmmac_pmt(priv, priv->hw, priv->wolopts);
4585
4567
 		priv->irq_wake = 1;
4586
4568
 	} else {
4569
+		if (priv->plat->integrated_phy_power)
4570
+			priv->plat->integrated_phy_power(priv->plat->bsp_priv,
4571
+							 false);
4587
4572
 		stmmac_mac_set(priv, priv->ioaddr, false);
4588
4573
 		pinctrl_pm_select_sleep_state(priv->device);
4589
4574
 		/* Disable clock in case of PWM is off */
4590
-		if (priv->plat->clk_ptp_ref)
4575
+		if (priv->plat->clk_ptp_ref && IS_ENABLED(CONFIG_STMMAC_PTP))
4591
4576
 			clk_disable_unprepare(priv->plat->clk_ptp_ref);
4592
4577
 		clk_disable_unprepare(priv->plat->pclk);
4593
4578
 		clk_disable_unprepare(priv->plat->stmmac_clk);
..
..
@@ -4624,6 +4609,8 @@
4624
4609
 		tx_q->cur_tx = 0;
4625
4610
 		tx_q->dirty_tx = 0;
4626
4611
 		tx_q->mss = 0;
4612
+
4613
+		netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
4627
4614
 	}
4628
4615
 }
4629
4616
 
..
..
@@ -4641,7 +4628,6 @@
4641
4628
 	if (!netif_running(ndev))
4642
4629
 		return 0;
4643
4630
 
4644
-	printk("troy test %s start .... \n",__func__);
4645
4631
 	/* Power Down bit, into the PM register, is cleared
4646
4632
 	 * automatically as soon as a magic packet or a Wake-up frame
4647
4633
 	 * is received. Anyway, it's better to manually clear
..
..
@@ -4658,11 +4644,14 @@
4658
4644
 		/* enable the clk previously disabled */
4659
4645
 		clk_prepare_enable(priv->plat->stmmac_clk);
4660
4646
 		clk_prepare_enable(priv->plat->pclk);
4661
-		if (priv->plat->clk_ptp_ref)
4647
+		if (priv->plat->clk_ptp_ref && IS_ENABLED(CONFIG_STMMAC_PTP))
4662
4648
 			clk_prepare_enable(priv->plat->clk_ptp_ref);
4663
4649
 		/* reset the phy so that it's ready */
4664
4650
 		if (priv->mii)
4665
4651
 			stmmac_mdio_reset(priv->mii);
4652
+		if (priv->plat->integrated_phy_power)
4653
+			priv->plat->integrated_phy_power(priv->plat->bsp_priv,
4654
+							 true);
4666
4655
 	}
4667
4656
 
4668
4657
 	mutex_lock(&priv->lock);
..
..
@@ -4684,8 +4673,6 @@
4684
4673
 
4685
4674
 	if (ndev->phydev)
4686
4675
 		phy_start(ndev->phydev);
4687
-	printk("troy test %s end .... \n",__func__);
4688
-	rtl8211F_led_control(ndev->phydev);
4689
4676
 
4690
4677
 	return 0;
4691
4678
 }