.. | .. |
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45 | 45 | #define ALIGN_SIZE 64 /* Should be enough for most CPUs */ |
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46 | 46 | #define TCMU_MAILBOX_FLAG_CAP_OOOC (1 << 0) /* Out-of-order completions */ |
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47 | 47 | #define TCMU_MAILBOX_FLAG_CAP_READ_LEN (1 << 1) /* Read data length */ |
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| 48 | +#define TCMU_MAILBOX_FLAG_CAP_TMR (1 << 2) /* TMR notifications */ |
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48 | 49 | |
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49 | 50 | struct tcmu_mailbox { |
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50 | 51 | __u16 version; |
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.. | .. |
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62 | 63 | enum tcmu_opcode { |
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63 | 64 | TCMU_OP_PAD = 0, |
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64 | 65 | TCMU_OP_CMD, |
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| 66 | + TCMU_OP_TMR, |
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65 | 67 | }; |
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66 | 68 | |
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67 | 69 | /* |
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.. | .. |
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128 | 130 | |
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129 | 131 | } __packed; |
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130 | 132 | |
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| 133 | +struct tcmu_tmr_entry { |
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| 134 | + struct tcmu_cmd_entry_hdr hdr; |
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| 135 | + |
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| 136 | +#define TCMU_TMR_UNKNOWN 0 |
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| 137 | +#define TCMU_TMR_ABORT_TASK 1 |
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| 138 | +#define TCMU_TMR_ABORT_TASK_SET 2 |
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| 139 | +#define TCMU_TMR_CLEAR_ACA 3 |
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| 140 | +#define TCMU_TMR_CLEAR_TASK_SET 4 |
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| 141 | +#define TCMU_TMR_LUN_RESET 5 |
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| 142 | +#define TCMU_TMR_TARGET_WARM_RESET 6 |
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| 143 | +#define TCMU_TMR_TARGET_COLD_RESET 7 |
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| 144 | +/* Pseudo reset due to received PR OUT */ |
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| 145 | +#define TCMU_TMR_LUN_RESET_PRO 128 |
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| 146 | + __u8 tmr_type; |
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| 147 | + |
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| 148 | + __u8 __pad1; |
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| 149 | + __u16 __pad2; |
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| 150 | + __u32 cmd_cnt; |
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| 151 | + __u64 __pad3; |
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| 152 | + __u64 __pad4; |
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| 153 | + __u16 cmd_ids[0]; |
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| 154 | +} __packed; |
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| 155 | + |
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131 | 156 | #define TCMU_OP_ALIGN_SIZE sizeof(__u64) |
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132 | 157 | |
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133 | 158 | enum tcmu_genl_cmd { |
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