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2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc 
 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/sbutils.c
....@@ -1,16 +1,17 @@
1
-/* SPDX-License-Identifier: GPL-2.0 */
21 /*
32  * Misc utility routines for accessing chip-specific features
43  * of the SiliconBackplane-based Broadcom chips.
54  *
6
- * Copyright (C) 1999-2019, Broadcom Corporation
7
- * 
5
+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
6
+ *
7
+ * Copyright (C) 1999-2017, Broadcom Corporation
8
+ *
89  *      Unless you and Broadcom execute a separate written software license
910  * agreement governing use of this software, this software is licensed to you
1011  * under the terms of the GNU General Public License version 2 (the "GPL"),
1112  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
1213  * following added to such license:
13
- * 
14
+ *
1415  *      As a special exception, the copyright holders of this software give you
1516  * permission to link this software with independent modules, and to copy and
1617  * distribute the resulting executable under terms of your choice, provided that
....@@ -18,7 +19,7 @@
1819  * the license of that module.  An independent module is a module which is not
1920  * derived from this software.  The special exception does not apply to any
2021  * modifications of the software.
21
- * 
22
+ *
2223  *      Notwithstanding the above, under no circumstances may you combine this
2324  * software in any way with any other Broadcom software provided under a license
2425  * other than the GPL, without Broadcom's express prior written consent.
....@@ -26,7 +27,7 @@
2627  *
2728  * <<Broadcom-WL-IPTag/Open:>>
2829  *
29
- * $Id: sbutils.c 514727 2014-11-12 03:02:48Z $
30
+ * $Id: sbutils.c 700323 2017-05-18 16:12:11Z $
3031  */
3132 
3233 #include <bcm_cfg.h>
....@@ -43,16 +44,15 @@
4344 
4445 #include "siutils_priv.h"
4546 
46
-
4747 /* local prototypes */
4848 static uint _sb_coreidx(si_info_t *sii, uint32 sba);
49
-static uint _sb_scan(si_info_t *sii, uint32 sba, void *regs, uint bus, uint32 sbba,
50
-                     uint ncores);
49
+static uint _sb_scan(si_info_t *sii, uint32 sba, volatile void *regs, uint bus, uint32 sbba,
50
+                     uint ncores, uint devid);
5151 static uint32 _sb_coresba(si_info_t *sii);
52
-static void *_sb_setcoreidx(si_info_t *sii, uint coreidx);
52
+static volatile void *_sb_setcoreidx(si_info_t *sii, uint coreidx);
5353 #define	SET_SBREG(sii, r, mask, val)	\
5454 		W_SBREG((sii), (r), ((R_SBREG((sii), (r)) & ~(mask)) | (val)))
55
-#define	REGS2SB(va)	(sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
55
+#define	REGS2SB(va)	(sbconfig_t*) ((volatile int8*)(va) + SBCONFIGOFF)
5656 
5757 /* sonicsrev */
5858 #define	SONICS_2_2	(SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
....@@ -66,10 +66,8 @@
6666 static uint32
6767 sb_read_sbreg(si_info_t *sii, volatile uint32 *sbr)
6868 {
69
-	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
7069 	uint8 tmp;
7170 	uint32 val, intr_val = 0;
72
-
7371 
7472 	/*
7573 	 * compact flash only has 11 bits address, while we needs 12 bits address.
....@@ -98,11 +96,9 @@
9896 static void
9997 sb_write_sbreg(si_info_t *sii, volatile uint32 *sbr, uint32 v)
10098 {
101
-	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
10299 	uint8 tmp;
103100 	volatile uint32 dummy;
104101 	uint32 intr_val = 0;
105
-
106102 
107103 	/*
108104 	 * compact flash only has 11 bits address, while we needs 12 bits address.
....@@ -150,8 +146,7 @@
150146 sb_intflag(si_t *sih)
151147 {
152148 	si_info_t *sii = SI_INFO(sih);
153
-	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
154
-	void *corereg;
149
+	volatile void *corereg;
155150 	sbconfig_t *sb;
156151 	uint origidx, intflag, intr_val = 0;
157152 
....@@ -215,7 +210,6 @@
215210 {
216211 	uint32 sbaddr;
217212 
218
-
219213 	switch (BUSTYPE(sii->pub.bustype)) {
220214 	case SI_BUS: {
221215 		sbconfig_t *sb = REGS2SB(sii->curmap);
....@@ -243,8 +237,7 @@
243237 	case SDIO_BUS:
244238 		sbaddr = (uint32)(uintptr)sii->curmap;
245239 		break;
246
-#endif
247
-
240
+#endif // endif
248241 
249242 	default:
250243 		sbaddr = BADCOREADDR;
....@@ -377,7 +370,7 @@
377370 sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
378371 {
379372 	uint origidx = 0;
380
-	uint32 *r = NULL;
373
+	volatile uint32 *r = NULL;
381374 	uint w;
382375 	uint intr_val = 0;
383376 	bool fast = FALSE;
....@@ -400,7 +393,7 @@
400393 			                            SI_CORE_SIZE);
401394 			ASSERT(GOODREGS(cores_info->regs[coreidx]));
402395 		}
403
-		r = (uint32 *)((uchar *)cores_info->regs[coreidx] + regoff);
396
+		r = (volatile uint32 *)((volatile uchar *)cores_info->regs[coreidx] + regoff);
404397 	} else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
405398 		/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
406399 
....@@ -408,17 +401,18 @@
408401 			/* Chipc registers are mapped at 12KB */
409402 
410403 			fast = TRUE;
411
-			r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
404
+			r = (volatile uint32 *)((volatile char *)sii->curmap +
405
+			               PCI_16KB0_CCREGS_OFFSET + regoff);
412406 		} else if (sii->pub.buscoreidx == coreidx) {
413407 			/* pci registers are at either in the last 2KB of an 8KB window
414408 			 * or, in pcie and pci rev 13 at 8KB
415409 			 */
416410 			fast = TRUE;
417411 			if (SI_FAST(sii))
418
-				r = (uint32 *)((char *)sii->curmap +
412
+				r = (volatile uint32 *)((volatile char *)sii->curmap +
419413 				               PCI_16KB0_PCIREGS_OFFSET + regoff);
420414 			else
421
-				r = (uint32 *)((char *)sii->curmap +
415
+				r = (volatile uint32 *)((volatile char *)sii->curmap +
422416 				               ((regoff >= SBCONFIGOFF) ?
423417 				                PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
424418 				               regoff);
....@@ -432,7 +426,8 @@
432426 		origidx = si_coreidx(&sii->pub);
433427 
434428 		/* switch core */
435
-		r = (uint32*) ((uchar*)sb_setcoreidx(&sii->pub, coreidx) + regoff);
429
+		r = (volatile uint32*) ((volatile uchar*)sb_setcoreidx(&sii->pub, coreidx) +
430
+		               regoff);
436431 	}
437432 	ASSERT(r != NULL);
438433 
....@@ -451,12 +446,7 @@
451446 	if (regoff >= SBCONFIGOFF)
452447 		w = R_SBREG(sii, r);
453448 	else {
454
-		if ((CHIPID(sii->pub.chip) == BCM5354_CHIP_ID) &&
455
-		    (coreidx == SI_CC_IDX) &&
456
-		    (regoff == OFFSETOF(chipcregs_t, watchdog))) {
457
-			w = val;
458
-		} else
459
-			w = R_REG(sii->osh, r);
449
+		w = R_REG(sii->osh, r);
460450 	}
461451 
462452 	if (!fast) {
....@@ -479,10 +469,10 @@
479469  * For accessing registers that would need a core switch, this function will return
480470  * NULL.
481471  */
482
-uint32 *
472
+volatile uint32 *
483473 sb_corereg_addr(si_t *sih, uint coreidx, uint regoff)
484474 {
485
-	uint32 *r = NULL;
475
+	volatile uint32 *r = NULL;
486476 	bool fast = FALSE;
487477 	si_info_t *sii = SI_INFO(sih);
488478 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
....@@ -502,7 +492,7 @@
502492 			                            SI_CORE_SIZE);
503493 			ASSERT(GOODREGS(cores_info->regs[coreidx]));
504494 		}
505
-		r = (uint32 *)((uchar *)cores_info->regs[coreidx] + regoff);
495
+		r = (volatile uint32 *)((volatile uchar *)cores_info->regs[coreidx] + regoff);
506496 	} else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
507497 		/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
508498 
....@@ -510,17 +500,18 @@
510500 			/* Chipc registers are mapped at 12KB */
511501 
512502 			fast = TRUE;
513
-			r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
503
+			r = (volatile uint32 *)((volatile char *)sii->curmap +
504
+			               PCI_16KB0_CCREGS_OFFSET + regoff);
514505 		} else if (sii->pub.buscoreidx == coreidx) {
515506 			/* pci registers are at either in the last 2KB of an 8KB window
516507 			 * or, in pcie and pci rev 13 at 8KB
517508 			 */
518509 			fast = TRUE;
519510 			if (SI_FAST(sii))
520
-				r = (uint32 *)((char *)sii->curmap +
511
+				r = (volatile uint32 *)((volatile char *)sii->curmap +
521512 				               PCI_16KB0_PCIREGS_OFFSET + regoff);
522513 			else
523
-				r = (uint32 *)((char *)sii->curmap +
514
+				r = (volatile uint32 *)((volatile char *)sii->curmap +
524515 				               ((regoff >= SBCONFIGOFF) ?
525516 				                PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
526517 				               regoff);
....@@ -542,7 +533,8 @@
542533  */
543534 #define SB_MAXBUSES	2
544535 static uint
545
-_sb_scan(si_info_t *sii, uint32 sba, void *regs, uint bus, uint32 sbba, uint numcores)
536
+_sb_scan(si_info_t *sii, uint32 sba, volatile void *regs, uint bus,
537
+	uint32 sbba, uint numcores, uint devid)
546538 {
547539 	uint next;
548540 	uint ncc = 0;
....@@ -588,9 +580,7 @@
588580 				/* Older chips */
589581 				uint chip = CHIPID(sii->pub.chip);
590582 
591
-				if (chip == BCM4306_CHIP_ID)	/* < 4306c0 */
592
-					numcores = 6;
593
-				else if (chip == BCM4704_CHIP_ID)
583
+				if (chip == BCM4704_CHIP_ID)
594584 					numcores = 9;
595585 				else if (chip == BCM5365_CHIP_ID)
596586 					numcores = 7;
....@@ -612,15 +602,15 @@
612602 
613603 			sii->numcores = next + 1;
614604 
615
-			if ((nsbba & 0xfff00000) != SI_ENUM_BASE)
605
+			if ((nsbba & 0xfff00000) != si_enum_base(devid))
616606 				continue;
617607 			nsbba &= 0xfffff000;
618608 			if (_sb_coreidx(sii, nsbba) != BADIDX)
619609 				continue;
620610 
621611 			nsbcc = (R_SBREG(sii, &sb->sbtmstatehigh) & 0x000f0000) >> 16;
622
-			nsbcc = _sb_scan(sii, sba, regs, bus + 1, nsbba, nsbcc);
623
-			if (sbba == SI_ENUM_BASE)
612
+			nsbcc = _sb_scan(sii, sba, regs, bus + 1, nsbba, nsbcc, devid);
613
+			if (sbba == si_enum_base(devid))
624614 				numcores -= nsbcc;
625615 			ncc += nsbcc;
626616 		}
....@@ -634,11 +624,12 @@
634624 
635625 /* scan the sb enumerated space to identify all cores */
636626 void
637
-sb_scan(si_t *sih, void *regs, uint devid)
627
+sb_scan(si_t *sih, volatile void *regs, uint devid)
638628 {
639629 	uint32 origsba;
640630 	sbconfig_t *sb;
641631 	si_info_t *sii = SI_INFO(sih);
632
+	BCM_REFERENCE(devid);
642633 
643634 	sb = REGS2SB(sii->curmap);
644635 
....@@ -649,8 +640,8 @@
649640 	 */
650641 	origsba = _sb_coresba(sii);
651642 
652
-	/* scan all SB(s) starting from SI_ENUM_BASE */
653
-	sii->numcores = _sb_scan(sii, origsba, regs, 0, SI_ENUM_BASE, 1);
643
+	/* scan all SB(s) starting from SI_ENUM_BASE_DEFAULT */
644
+	sii->numcores = _sb_scan(sii, origsba, regs, 0, si_enum_base(devid), 1, devid);
654645 }
655646 
656647 /*
....@@ -658,7 +649,7 @@
658649  * must be called with interrupts off.
659650  * Moreover, callers should keep interrupts off during switching out of and back to d11 core
660651  */
661
-void *
652
+volatile void *
662653 sb_setcoreidx(si_t *sih, uint coreidx)
663654 {
664655 	si_info_t *sii = SI_INFO(sih);
....@@ -681,12 +672,12 @@
681672 /* This function changes the logical "focus" to the indicated core.
682673  * Return the current core's virtual address.
683674  */
684
-static void *
675
+static volatile void *
685676 _sb_setcoreidx(si_info_t *sii, uint coreidx)
686677 {
687678 	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
688679 	uint32 sbaddr = cores_info->coresba[coreidx];
689
-	void *regs;
680
+	volatile void *regs;
690681 
691682 	switch (BUSTYPE(sii->pub.bustype)) {
692683 	case SI_BUS:
....@@ -725,7 +716,6 @@
725716 		regs = cores_info->regs[coreidx];
726717 		break;
727718 #endif	/* BCMSDIO */
728
-
729719 
730720 	default:
731721 		ASSERT(0);
....@@ -806,13 +796,11 @@
806796 	return (sb_size(R_SBREG(sii, sb_admatch(sii, asidx))));
807797 }
808798 
809
-
810799 /* do buffered registers update */
811800 void
812801 sb_commit(si_t *sih)
813802 {
814803 	si_info_t *sii = SI_INFO(sih);
815
-	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
816804 	uint origidx;
817805 	uint intr_val = 0;
818806 
....@@ -974,12 +962,10 @@
974962 sb_set_initiator_to(si_t *sih, uint32 to, uint idx)
975963 {
976964 	si_info_t *sii = SI_INFO(sih);
977
-	si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
978965 	uint origidx;
979966 	uint intr_val = 0;
980967 	uint32 tmp, ret = 0xffffffff;
981968 	sbconfig_t *sb;
982
-
983969 
984970 	if ((to & ~TO_MASK) != 0)
985971 		return ret;
....@@ -996,7 +982,7 @@
996982 		case PCMCIA_BUS:
997983 #ifdef BCMSDIO
998984 		case SDIO_BUS:
999
-#endif
985
+#endif // endif
1000986 			idx = si_findcoreidx(sih, PCMCIA_CORE_ID, 0);
1001987 			break;
1002988 		case SI_BUS:
....@@ -1106,4 +1092,4 @@
11061092 	sb_setcoreidx(sih, origidx);
11071093 	INTR_RESTORE(sii, intr_val);
11081094 }
1109
-#endif	
1095
+#endif // endif