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2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc 
 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/sdio.h
....@@ -1,16 +1,17 @@
1
-/* SPDX-License-Identifier: GPL-2.0 */
21 /*
32  * SDIO spec header file
43  * Protocol and standard (common) device definitions
54  *
6
- * Copyright (C) 1999-2019, Broadcom Corporation
7
- * 
5
+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
6
+ *
7
+ * Copyright (C) 1999-2017, Broadcom Corporation
8
+ *
89  *      Unless you and Broadcom execute a separate written software license
910  * agreement governing use of this software, this software is licensed to you
1011  * under the terms of the GNU General Public License version 2 (the "GPL"),
1112  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
1213  * following added to such license:
13
- * 
14
+ *
1415  *      As a special exception, the copyright holders of this software give you
1516  * permission to link this software with independent modules, and to copy and
1617  * distribute the resulting executable under terms of your choice, provided that
....@@ -18,7 +19,7 @@
1819  * the license of that module.  An independent module is a module which is not
1920  * derived from this software.  The special exception does not apply to any
2021  * modifications of the software.
21
- * 
22
+ *
2223  *      Notwithstanding the above, under no circumstances may you combine this
2324  * software in any way with any other Broadcom software provided under a license
2425  * other than the GPL, without Broadcom's express prior written consent.
....@@ -26,7 +27,7 @@
2627  *
2728  * <<Broadcom-WL-IPTag/Open:>>
2829  *
29
- * $Id: sdio.h 514727 2014-11-12 03:02:48Z $
30
+ * $Id: sdio.h 689948 2017-03-14 05:21:03Z $
3031  */
3132 
3233 #ifndef	_SDIO_H
....@@ -89,11 +90,18 @@
8990 #define SDIOD_CCCR_INTR_EXTN		0x16
9091 
9192 /* Broadcom extensions (corerev >= 1) */
92
-#define SDIOD_CCCR_BRCM_CARDCAP		0xf0
93
+#define SDIOD_CCCR_BRCM_CARDCAP					0xf0
9394 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_SUPPORT	0x02
94
-#define SDIOD_CCCR_BRCM_CARDCAP_CMD14_EXT	0x04
95
-#define SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC	0x08
96
-#define SDIOD_CCCR_BRCM_CARDCTL			0xf1
95
+#define SDIOD_CCCR_BRCM_CARDCAP_CMD14_EXT		0x04
96
+#define SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC		0x08
97
+#define SDIOD_CCCR_BRCM_CARDCAP_CHIPID_PRESENT	0x40
98
+#define	SDIOD_CCCR_BRCM_CARDCAP_SECURE_MODE		0x80
99
+
100
+#define SDIOD_CCCR_BRCM_CARDCTL				0xf1
101
+#define SDIOD_CCCR_BRCM_CISLOADED			0x1
102
+#define SDIOD_CCCR_BRCM_WLANRST_ONF0ABORT	0x2
103
+#define SDIOD_CCCR_BRCM_SDIORST_ONWLANRST	0x20
104
+
97105 #define SDIOD_CCCR_BRCM_SEPINT			0xf2
98106 
99107 /* cccr_sdio_rev */
....@@ -107,6 +115,10 @@
107115 /* io_en */
108116 #define SDIO_FUNC_ENABLE_1	0x02	/* function 1 I/O enable */
109117 #define SDIO_FUNC_ENABLE_2	0x04	/* function 2 I/O enable */
118
+#if defined(BT_OVER_SDIO)
119
+#define SDIO_FUNC_ENABLE_3	0x08	/* function 2 I/O enable */
120
+#define SDIO_FUNC_DISABLE_3	0xF0	/* function 2 I/O enable */
121
+#endif /* defined (BT_OVER_SDIO) */
110122 
111123 /* io_rdys */
112124 #define SDIO_FUNC_READY_1	0x02	/* function 1 I/O ready */
....@@ -116,7 +128,9 @@
116128 #define INTR_CTL_MASTER_EN	0x1	/* interrupt enable master */
117129 #define INTR_CTL_FUNC1_EN	0x2	/* interrupt enable for function 1 */
118130 #define INTR_CTL_FUNC2_EN	0x4	/* interrupt enable for function 2 */
119
-
131
+#if defined(BT_OVER_SDIO)
132
+#define INTR_CTL_FUNC3_EN	0x8	/* interrupt enable for function 3 */
133
+#endif /* defined (BT_OVER_SDIO) */
120134 /* intr_status */
121135 #define INTR_STATUS_FUNC1	0x2	/* interrupt pending for function 1 */
122136 #define INTR_STATUS_FUNC2	0x4	/* interrupt pending for function 2 */
....@@ -280,8 +294,6 @@
280294 #define CARDREG_STATUS_BIT_IOCURRENTSTATE0	9
281295 #define CARDREG_STATUS_BIT_FUN_NUM_ERROR	4
282296 
283
-
284
-
285297 #define SD_CMD_GO_IDLE_STATE		0	/* mandatory for SDIO */
286298 #define SD_CMD_SEND_OPCOND		1
287299 #define SD_CMD_MMC_SET_RCA		3
....@@ -374,7 +386,6 @@
374386 
375387 #define SD_RSP_R5_ERRBITS		0xCB
376388 
377
-
378389 /* ------------------------------------------------
379390  *  SDIO Commands and responses
380391  *
....@@ -445,7 +456,6 @@
445456 #define CMD52_FUNCTION_S	28
446457 #define CMD52_RW_FLAG_M		BITFIELD_MASK(1)  /* Bit  31       - R/W flag */
447458 #define CMD52_RW_FLAG_S		31
448
-
449459 
450460 #define CMD53_BYTE_BLK_CNT_M	BITFIELD_MASK(9) /* Bits [8:0]     - Byte/Block Count of CMD53 */
451461 #define CMD53_BYTE_BLK_CNT_S	0
....@@ -537,7 +547,6 @@
537547 #define RSP1_OUT_OF_RANGE_M	BITFIELD_MASK(1)  /* Bit 31   - Cmd arg was out of range */
538548 #define RSP1_OUT_OF_RANGE_S	31
539549 
540
-
541550 #define RSP5_DATA_M		BITFIELD_MASK(8)  /* Bits [0:7]   - data */
542551 #define RSP5_DATA_S		0
543552 #define RSP5_FLAGS_M		BITFIELD_MASK(8)  /* Bit  [15:8]  - Rsp flags */
....@@ -622,5 +631,55 @@
622631 #define CMD_OPTION_DEFAULT	0
623632 #define CMD_OPTION_TUNING	1
624633 
634
+/* SDIO message exchange registers */
635
+#define SDIO_FN1_MSG_H2D_REG0	0x10030
636
+#define SDIO_FN1_MSG_H2D_REG1	0x10034
637
+#define SDIO_FN1_MSG_D2H_REG0	0x10038
638
+#define SDIO_FN1_MSG_D2H_REG1	0x1003c
639
+
640
+#define CFG_WRITE_BYTE_MASK	0xff
641
+
642
+#define HS_POLL_PERIOD_MS 10
643
+#define D2H_READY_WD_RESET_MS 1		/* 1ms */
644
+#ifdef BCMQT
645
+#define D2H_READY_TIMEOUT_MS (1000 * 60 * 3) /* 3 Mins >~ FW download time */
646
+#define D2H_VALDN_DONE_TIMEOUT_MS (1000 * 60 * 5) /* 5 Mins >~ Validation time */
647
+#define D2H_TRX_HDR_PARSE_DONE_TIMEOUT_MS (1000 * 60 * 1) /* 1 Mins >~ TRX Parsing */
648
+#define D2H_READY_WD_RESET_COUNT (84 * 1000) /* ~84secs >~ BL ready time after wd rst */
649
+#define D2H_READY_WD_RESET_DBG_PRINT_MS (1000) /* 1000ms - DEBUG print at every 1000ms */
650
+#else
651
+#define D2H_READY_TIMEOUT_MS (100) /* 100ms >~ FW download time */
652
+#define D2H_VALDN_DONE_TIMEOUT_MS (250) /* 250ms >~ Validation time */
653
+#define D2H_TRX_HDR_PARSE_DONE_TIMEOUT_MS (50) /* 50ms >~ TRX Parsing */
654
+#define D2H_READY_WD_RESET_COUNT (200) /* ~200ms >~ BL ready time after wd rst */
655
+#define D2H_READY_WD_RESET_DBG_PRINT_MS (10) /* 10ms - DEBUG print at evry 10ms */
656
+#endif // endif
657
+
658
+typedef struct bl_hs_address {
659
+	volatile void *d2h;
660
+	volatile void *h2d;
661
+} hs_addrs_t;
662
+
663
+/* [D2H] Dongle to host handshake bits shift */
664
+enum {
665
+	D2H_START_SHIFT			= 0,
666
+	D2H_READY_SHIFT			= 1,
667
+	D2H_STEADY_SHIFT		= 2,
668
+	D2H_TRX_HDR_PARSE_DONE_SHIFT	= 3,
669
+	D2H_VALDN_START_SHIFT		= 4,
670
+	D2H_VALDN_RESULT_SHIFT		= 5,
671
+	D2H_VALDN_DONE_SHIFT		= 6
672
+	/* Bits 31:7 reserved for future */
673
+};
674
+
675
+/* [H2D] Host to dongle handshake bits shift */
676
+enum {
677
+	H2D_DL_START_SHIFT		= 0,
678
+	H2D_DL_DONE_SHIFT		= 1,
679
+	H2D_DL_NVRAM_DONE_SHIFT		= 2,
680
+	H2D_BL_RESET_ON_ERROR_SHIFT	= 3
681
+	/* Bits 31:4 reserved for future */
682
+};
683
+
625684 #endif /* def BCMSDIO */
626685 #endif /* _SDIO_H */