~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,15 +1,16 @@
1		-/* SPDX-License-Identifier: GPL-2.0 */
2	1	/*
3	2	* BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
4	3	*
5		- * Copyright (C) 1999-2019, Broadcom Corporation
6		- *
	4	+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
	5	+ *
	6	+ * Copyright (C) 1999-2017, Broadcom Corporation
	7	+ *
7	8	* Unless you and Broadcom execute a separate written software license
8	9	* agreement governing use of this software, this software is licensed to you
9	10	* under the terms of the GNU General Public License version 2 (the "GPL"),
10	11	* available at http://www.broadcom.com/licenses/GPLv2.php, with the
11	12	* following added to such license:
12		- *
	13	+ *
13	14	* As a special exception, the copyright holders of this software give you
14	15	* permission to link this software with independent modules, and to copy and
15	16	* distribute the resulting executable under terms of your choice, provided that
..	..	@@ -17,7 +18,7 @@
17	18	* the license of that module. An independent module is a module which is not
18	19	* derived from this software. The special exception does not apply to any
19	20	* modifications of the software.
20		- *
	21	+ *
21	22	* Notwithstanding the above, under no circumstances may you combine this
22	23	* software in any way with any other Broadcom software provided under a license
23	24	* other than the GPL, without Broadcom's express prior written consent.
..	..	@@ -25,7 +26,7 @@
25	26	*
26	27	* <<Broadcom-WL-IPTag/Open:>>
27	28	*
28		- * $Id: sbpcmcia.h 521344 2014-12-17 10:03:55Z $
	29	+ * $Id: sbpcmcia.h 647676 2016-07-07 02:59:05Z $
29	30	*/
30	31
31	32	#ifndef _SBPCMCIA_H
..	..	@@ -61,12 +62,10 @@
61	62	#define COR_BLREN 0x01
62	63	#define COR_FUNEN 0x01
63	64
64		-
65	65	#define PCICIA_FCSR (2 / 2)
66	66	#define PCICIA_PRR (4 / 2)
67	67	#define PCICIA_SCR (6 / 2)
68	68	#define PCICIA_ESR (8 / 2)
69		-
70	69
71	70	#define PCM_MEMOFF 0x0000
72	71	#define F0_MEMOFF 0x1000
..	..	@@ -106,6 +105,34 @@
106	105	#define SRI_BLANK 0x04
107	106	#define SRI_OTP 0x80
108	107
	108	+#define SROM16K_BANK_SEL_MASK (3 << 11)
	109	+#define SROM16K_BANK_SHFT_MASK 11
	110	+#define SROM16K_ADDR_SEL_MASK ((1 << SROM16K_BANK_SHFT_MASK) - 1)
	111	+#define SROM_PRSNT_MASK 0x1
	112	+#define SROM_SUPPORT_SHIFT_MASK 30
	113	+#define SROM_SUPPORTED (0x1 << SROM_SUPPORT_SHIFT_MASK)
	114	+#define SROM_SIZE_MASK 0x00000006
	115	+#define SROM_SIZE_2K 2
	116	+#define SROM_SIZE_512 1
	117	+#define SROM_SIZE_128 0
	118	+#define SROM_SIZE_SHFT_MASK 1
	119	+
	120	+/* Standard tuples we know about */
	121	+
	122	+#define CISTPL_NULL 0x00
	123	+#define CISTPL_END 0xff /* End of the CIS tuple chain */
	124	+#define CISTPL_OFFSET 0xC0
	125	+
	126	+#define CISTPL_BRCM_HNBU 0x80
	127	+
	128	+#define HNBU_BOARDREV 0x02 /* One byte board revision */
	129	+
	130	+#define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */
	131	+
	132	+#define HNBU_HNBUCIS 0x1d /* what follows is proprietary HNBU CIS format */
	133	+
	134	+#define HNBU_CUSTOM1 0x82 /* 4 byte; For non-BRCM post-mfg additions */
	135	+#define HNBU_CUSTOM2 0x83 /* Reserved; For non-BRCM post-mfg additions */
109	136
110	137	/* sbtmstatelow */
111	138	#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
..	..	@@ -113,5 +140,4 @@
113	140
114	141	/* sbtmstatehigh */
115	142	#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
116		-
117	143	#endif /* _SBPCMCIA_H */