rtl8211F_led_control

hc

2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc

 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/sbhnddma.h
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@@ -1,16 +1,17 @@
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-/* SPDX-License-Identifier: GPL-2.0 */
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 /*
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  * Generic Broadcom Home Networking Division (HND) DMA engine HW interface
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  * This supports the following chips: BCM42xx, 44xx, 47xx .
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  *
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- * Copyright (C) 1999-2019, Broadcom Corporation
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- * 
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+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
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+ *
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+ * Copyright (C) 1999-2017, Broadcom Corporation
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+ *
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  *      Unless you and Broadcom execute a separate written software license
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  * agreement governing use of this software, this software is licensed to you
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  * under the terms of the GNU General Public License version 2 (the "GPL"),
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  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
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  * following added to such license:
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- * 
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+ *
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  *      As a special exception, the copyright holders of this software give you
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  * permission to link this software with independent modules, and to copy and
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  * distribute the resulting executable under terms of your choice, provided that
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@@ -18,7 +19,7 @@
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  * the license of that module.  An independent module is a module which is not
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  * derived from this software.  The special exception does not apply to any
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  * modifications of the software.
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- * 
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+ *
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  *      Notwithstanding the above, under no circumstances may you combine this
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  * software in any way with any other Broadcom software provided under a license
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  * other than the GPL, without Broadcom's express prior written consent.
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@@ -26,7 +27,7 @@
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  *
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  * <<Broadcom-WL-IPTag/Open:>>
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  *
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- * $Id: sbhnddma.h 530150 2015-01-29 08:43:40Z $
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+ * $Id: sbhnddma.h 694506 2017-04-13 05:10:05Z $
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  */
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 #ifndef	_sbhnddma_h_
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@@ -37,7 +38,6 @@
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  *  basic DMA register set is per channel(transmit or receive)
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  *  a pair of channels is defined for convenience
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  */
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-
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 /* 32 bits addressing */
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@@ -118,6 +118,7 @@
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 #define DMA_PC_4	1
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 #define DMA_PC_8	2
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 #define DMA_PC_16	3
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+#define DMA_PC_32	4
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 /* others: reserved */
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 /** Prefetch threshold */
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@@ -125,6 +126,10 @@
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 #define DMA_PT_2	1
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 #define DMA_PT_4	2
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 #define DMA_PT_8	3
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+
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+/** Channel Switch */
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+#define DMA_CS_OFF	0
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+#define DMA_CS_ON	1
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 /* transmit descriptor table pointer */
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 #define	XP_LD_MASK	0xfff			/**< last valid descriptor */
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@@ -164,7 +169,8 @@
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 #define RC_PC_SHIFT	21
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 #define RC_PT_MASK	0x03000000		/**< Prefetch threshold */
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 #define RC_PT_SHIFT	24
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-
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+#define RC_WAITCMP_MASK 0x00001000
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+#define RC_WAITCMP_SHIFT 12
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 /* receive descriptor table pointer */
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 #define	RP_LD_MASK	0xfff			/**< last valid descriptor */
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@@ -274,13 +280,12 @@
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 #define D64_DEF_USBBURSTLEN     2
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 #define D64_DEF_SDIOBURSTLEN    1
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-
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 #ifndef D64_USBBURSTLEN
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 #define D64_USBBURSTLEN	DMA_BL_64
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-#endif
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+#endif // endif
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 #ifndef D64_SDIOBURSTLEN
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 #define D64_SDIOBURSTLEN	DMA_BL_32
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-#endif
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+#endif // endif
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 /* transmit channel control */
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 #define	D64_XC_XE		0x00000001	/**< transmit enable */
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@@ -289,6 +294,8 @@
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 #define	D64_XC_FL		0x00000010	/**< flush request */
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 #define D64_XC_MR_MASK		0x000001C0	/**< Multiple outstanding reads */
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 #define D64_XC_MR_SHIFT		6
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+#define D64_XC_CS_SHIFT		9		/**< channel switch enable */
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+#define D64_XC_CS_MASK		0x00000200      /**< channel switch enable */
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 #define	D64_XC_PD		0x00000800	/**< parity check disable */
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 #define	D64_XC_AE		0x00030000	/**< address extension bits */
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 #define	D64_XC_AE_SHIFT		16
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@@ -298,6 +305,8 @@
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 #define D64_XC_PC_SHIFT		21
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 #define D64_XC_PT_MASK		0x03000000		/**< Prefetch threshold */
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 #define D64_XC_PT_SHIFT		24
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+#define D64_XC_CO_MASK		0x04000000	/**< coherent transactions for descriptors */
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+#define D64_XC_CO_SHIFT		26
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 /* transmit descriptor table pointer */
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 #define	D64_XP_LD_MASK		0x00001fff	/**< last valid descriptor */
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@@ -331,6 +340,8 @@
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 #define	D64_RC_SHIFT		9	/**< separate rx header descriptor enable */
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 #define	D64_RC_OC		0x00000400	/**< overflow continue */
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 #define	D64_RC_PD		0x00000800	/**< parity check disable */
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+#define D64_RC_WAITCMP_MASK	0x00001000
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+#define D64_RC_WAITCMP_SHIFT	12
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 #define D64_RC_SA		0x00002000	/**< select active */
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 #define D64_RC_GE		0x00004000	/**< Glom enable */
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 #define	D64_RC_AE		0x00030000	/**< address extension bits */
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@@ -341,6 +352,10 @@
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 #define D64_RC_PC_SHIFT		21
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 #define D64_RC_PT_MASK		0x03000000	/**< Prefetch threshold */
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 #define D64_RC_PT_SHIFT		24
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+#define D64_RC_CO_MASK		0x04000000	/**< coherent transactions for descriptors */
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+#define D64_RC_CO_SHIFT		26
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+#define	D64_RC_ROEXT_MASK	0x08000000	/**< receive frame offset extension bit */
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+#define	D64_RC_ROEXT_SHIFT	27
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 /* flags for dma controller */
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 #define DMA_CTRL_PEN		(1 << 0)	/**< partity enable */
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@@ -351,6 +366,15 @@
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 #define DMA_CTRL_DMA_AVOIDANCE_WAR (1 << 5)	/**< DMA avoidance WAR for 4331 */
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 #define DMA_CTRL_RXSINGLE	(1 << 6)	/**< always single buffer */
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 #define DMA_CTRL_SDIO_RXGLOM	(1 << 7)	/**< DMA Rx glome is enabled */
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+#define DMA_CTRL_DESC_ONLY_FLAG (1 << 8)	/**< For DMA which posts only descriptors,
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+						 * no packets
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+						 */
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+#define DMA_CTRL_DESC_CD_WAR	(1 << 9)	/**< WAR for descriptor only DMA's CD not being
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+						 * updated correctly by HW in CT mode.
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+						 */
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+#define DMA_CTRL_CS		(1 << 10)	/* channel switch enable */
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+#define DMA_CTRL_ROEXT		(1 << 11)	/* receive frame offset extension support */
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+#define DMA_CTRL_RX_ALIGN_8BYTE	(1 << 12)	/* RXDMA address 8-byte aligned for 43684A0 */
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 /* receive descriptor table pointer */
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 #define	D64_RP_LD_MASK		0x00001fff	/**< last valid descriptor */
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@@ -365,8 +389,8 @@
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 #define	D64_RS0_RS_STOPPED	0x30000000	/**< stopped */
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 #define	D64_RS0_RS_SUSP		0x40000000	/**< suspend pending */
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-#define	D64_RS1_AD_MASK		0x0001ffff	/**< active descriptor */
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-#define	D64_RS1_RE_MASK		0xf0000000     	/**< receive errors */
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+#define	D64_RS1_AD_MASK		(di->d64_rs1_ad_mask)	/* active descriptor pointer */
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+#define	D64_RS1_RE_MASK		0xf0000000	/* receive errors */
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 #define	D64_RS1_RE_SHIFT		28
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 #define	D64_RS1_RE_NOERR	0x00000000	/**< no error */
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 #define	D64_RS1_RE_DPO		0x10000000	/**< descriptor protocol error */
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@@ -392,6 +416,7 @@
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 /* descriptor control flags 1 */
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 #define D64_CTRL_COREFLAGS	0x0ff00000		/**< core specific flags */
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+#define D64_CTRL1_COHERENT      ((uint32)1 << 17)       /* cache coherent per transaction */
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 #define	D64_CTRL1_NOTPCIE	((uint32)1 << 18)	/**< buirst size control */
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 #define	D64_CTRL1_EOT		((uint32)1 << 28)	/**< end of descriptor table */
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 #define	D64_CTRL1_IOC		((uint32)1 << 29)	/**< interrupt on completion */
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 #define	D64_CTRL1_SOF		((uint32)1 << 31)	/**< start of frame */
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 /* descriptor control flags 2 */
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-#define	D64_CTRL2_BC_MASK	0x00007fff /**< buffer byte count. real data len must <= 16KB */
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+#define	D64_CTRL2_MAX_LEN	0x0000fff7 /* Max transfer length (buffer byte count) <= 65527 */
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+#define	D64_CTRL2_BC_MASK	0x0000ffff /**< mask for buffer byte count */
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 #define	D64_CTRL2_AE		0x00030000 /**< address extension bits */
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 #define	D64_CTRL2_AE_SHIFT	16
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 #define D64_CTRL2_PARITY	0x00040000      /* parity bit */
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 #define D64_RX_FRM_STS_LEN	0x0000ffff	/**< frame length mask */
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 #define D64_RX_FRM_STS_OVFL	0x00800000	/**< RxOverFlow */
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 #define D64_RX_FRM_STS_DSCRCNT	0x0f000000 /**< no. of descriptors used - 1, d11corerev >= 22 */
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+#define D64_RX_FRM_STS_DSCRCNT_SHIFT   24      /* Shift for no .of dma descriptor field */
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 #define D64_RX_FRM_STS_DATATYPE	0xf0000000	/**< core-dependent data type */
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+#define BCM_D64_CTRL2_BOUND_DMA_LENGTH(len) \
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+(((len) > D64_CTRL2_MAX_LEN) ? D64_CTRL2_MAX_LEN : (len))
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+
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 /** receive frame status */
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 typedef volatile struct {
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 	uint16 len;