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2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc 
 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/hndsoc.h
....@@ -1,15 +1,16 @@
1
-/* SPDX-License-Identifier: GPL-2.0 */
21 /*
32  * Broadcom HND chip & on-chip-interconnect-related definitions.
43  *
5
- * Copyright (C) 1999-2019, Broadcom Corporation
6
- * 
4
+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
5
+ *
6
+ * Copyright (C) 1999-2017, Broadcom Corporation
7
+ *
78  *      Unless you and Broadcom execute a separate written software license
89  * agreement governing use of this software, this software is licensed to you
910  * under the terms of the GNU General Public License version 2 (the "GPL"),
1011  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
1112  * following added to such license:
12
- * 
13
+ *
1314  *      As a special exception, the copyright holders of this software give you
1415  * permission to link this software with independent modules, and to copy and
1516  * distribute the resulting executable under terms of your choice, provided that
....@@ -17,7 +18,7 @@
1718  * the license of that module.  An independent module is a module which is not
1819  * derived from this software.  The special exception does not apply to any
1920  * modifications of the software.
20
- * 
21
+ *
2122  *      Notwithstanding the above, under no circumstances may you combine this
2223  * software in any way with any other Broadcom software provided under a license
2324  * other than the GPL, without Broadcom's express prior written consent.
....@@ -25,7 +26,7 @@
2526  *
2627  * <<Broadcom-WL-IPTag/Open:>>
2728  *
28
- * $Id: hndsoc.h 517544 2014-11-26 00:40:42Z $
29
+ * $Id: hndsoc.h 672520 2016-11-28 23:30:55Z $
2930  */
3031 
3132 #ifndef	_HNDSOC_H
....@@ -46,10 +47,35 @@
4647 #define	SI_SDRAM_SWAPPED	0x10000000	/* Byteswapped Physical SDRAM */
4748 #define SI_SDRAM_R2		0x80000000	/* Region 2 for sdram (512 MB) */
4849 
49
-#define SI_ENUM_BASE    	0x18000000	/* Enumeration space base */
50
+#ifdef STB_SOC_WIFI
51
+#define SI_REG_BASE_SIZE	0xB000		/* size from 0xf1800000 to 0xf180AFFF (44KB) */
52
+#define SI_ENUM_BASE_DEFAULT		0xF1800000	/* Enumeration space base */
53
+#define SI_WRAP_BASE_DEFAULT		0xF1900000	/* Wrapper space base */
54
+#endif /* STB_SOC_WIFI */
5055 
51
-#define SI_WRAP_BASE    	0x18100000	/* Wrapper space base */
52
-#define SI_CORE_SIZE    	0x1000		/* each core gets 4Kbytes for registers */
56
+#ifndef SI_ENUM_BASE_DEFAULT
57
+#define SI_ENUM_BASE_DEFAULT		0x18000000	/* Enumeration space base */
58
+#endif // endif
59
+
60
+#ifndef SI_WRAP_BASE_DEFAULT
61
+#define SI_WRAP_BASE_DEFAULT		0x18100000	/* Wrapper space base */
62
+#endif // endif
63
+
64
+#ifndef SI_ENUM_PCIE2_BASE
65
+#define SI_ENUM_PCIE2_BASE		0x18003000	/* PCIE Enumeration space base */
66
+#endif // endif
67
+
68
+/** new(er) chips started locating their chipc core at a different BP address than 0x1800_0000 */
69
+// NIC and DHD driver binaries should support both old(er) and new(er) chips at the same time
70
+#define SI_ENUM_BASE(sih)	((sih)->enum_base)
71
+#define SI_WRAP_BASE(sih)	(SI_ENUM_BASE(sih) + 0x00100000)
72
+
73
+#define SI_CORE_SIZE		0x1000		/* each core gets 4Kbytes for registers */
74
+
75
+#define SI_NIC400_GPV_BASE	0x18200000	/* NIC-400 Global Programmers View (GPV) */
76
+#define SI_GPV_WR_CAP_ADDR	0x4008	/* WR-CAP offset */
77
+#define SI_GPV_RD_CAP_EN	0x1	/* issue read */
78
+#define SI_GPV_WR_CAP_EN	0x2	/* issue write */
5379 
5480 #ifndef SI_MAXCORES
5581 #define	SI_MAXCORES		32		/* NorthStar has more cores */
....@@ -80,7 +106,9 @@
80106 #define	SI_ARMCM3_SRAM2		0x60000000	/* ARM Cortex-M3 SRAM Region 2 */
81107 #define	SI_ARM7S_SRAM2		0x80000000	/* ARM7TDMI-S SRAM Region 2 */
82108 #define	SI_ARMCA7_ROM		0x00000000	/* ARM Cortex-A7 ROM */
109
+#ifndef SI_ARMCA7_RAM
83110 #define	SI_ARMCA7_RAM		0x00200000	/* ARM Cortex-A7 RAM */
111
+#endif // endif
84112 #define	SI_ARM_FLASH1		0xffff0000	/* ARM Flash Region 1 */
85113 #define	SI_ARM_FLASH1_SZ	0x00010000	/* ARM Size of Flash Region 1 */
86114 
....@@ -97,6 +125,7 @@
97125 
98126 #define SI_BCM53573_NANDFLASH	0x30000000	/* 53573 NAND flash base */
99127 #define SI_BCM53573_NORFLASH	0x1c000000	/* 53573 NOR flash base */
128
+#define SI_BCM53573_FLASH2_SZ	0x04000000	/* 53573 NOR flash2 size */
100129 
101130 #define	SI_BCM53573_NORFLASH_WINDOW	0x01000000	/* only support 16M direct access for
102131 							 * 3-byte address modes in spi flash
....@@ -104,8 +133,18 @@
104133 #define	SI_BCM53573_BOOTDEV_MASK	0x3
105134 #define	SI_BCM53573_BOOTDEV_NOR		0x0
106135 
136
+#define SI_BCM53573_NAND_PRE_MASK	0x100	/* 53573 NAND present mask */
137
+
107138 #define	SI_BCM53573_DDRTYPE_MASK	0x10
108139 #define	SI_BCM53573_DDRTYPE_DDR3	0x10
140
+
141
+#define	SI_BCM47189_RGMII_VDD_MASK	0x3
142
+#define	SI_BCM47189_RGMII_VDD_SHIFT	21
143
+#define	SI_BCM47189_RGMII_VDD_3_3V	0
144
+#define	SI_BCM47189_RGMII_VDD_2_5V	1
145
+#define	SI_BCM47189_RGMII_VDD_1_5V	1
146
+
147
+#define	SI_BCM53573_LOCKED_CPUPLL	0x1
109148 
110149 /* APB bridge code */
111150 #define	APB_BRIDGE_ID		0x135		/* APB Bridge 0, 1, etc. */
....@@ -173,10 +212,13 @@
173212 #define USB30D_CORE_ID		0x83d		/* usb 3.0 device core */
174213 #define ARMCR4_CORE_ID		0x83e		/* ARM CR4 CPU */
175214 #define GCI_CORE_ID		0x840		/* GCI Core */
215
+#define SR_CORE_ID		0x841		/* SR_CORE ID */
176216 #define M2MDMA_CORE_ID          0x844           /* memory to memory dma */
177217 #define CMEM_CORE_ID		0x846		/* CNDS DDR2/3 memory controller */
178218 #define ARMCA7_CORE_ID		0x847		/* ARM CA7 CPU */
179219 #define SYSMEM_CORE_ID		0x849		/* System memory core */
220
+#define HUB_CORE_ID		0x84b           /* Hub core ID */
221
+#define HND_OOBR_CORE_ID        0x85c           /* Hnd oob router core ID */
180222 #define APB_BRIDGE_CORE_ID	0x135		/* APB bridge core ID */
181223 #define AXI_CORE_ID		0x301		/* AXI/GPV core ID */
182224 #define EROM_CORE_ID		0x366		/* EROM core ID */
....@@ -185,7 +227,6 @@
185227 						 * unused address ranges
186228 						 */
187229 
188
-#define CC_4706_CORE_ID		0x500		/* chipcommon core */
189230 #define NS_PCIEG2_CORE_ID	0x501		/* PCIE Gen 2 core */
190231 #define NS_DMA_CORE_ID		0x502		/* DMA core */
191232 #define NS_SDIO3_CORE_ID	0x503		/* SDIO3 core */
....@@ -197,12 +238,9 @@
197238 #define NS_NAND_CORE_ID		0x509		/* NAND flash controller core */
198239 #define NS_QSPI_CORE_ID		0x50a		/* SPI flash controller core */
199240 #define NS_CCB_CORE_ID		0x50b		/* ChipcommonB core */
200
-#define SOCRAM_4706_CORE_ID	0x50e		/* internal memory core */
201
-#define NS_SOCRAM_CORE_ID	SOCRAM_4706_CORE_ID
241
+#define NS_SOCRAM_CORE_ID	0x50e		/* internal memory core */
202242 #define	ARMCA9_CORE_ID		0x510		/* ARM Cortex A9 core (ihost) */
203243 #define	NS_IHOST_CORE_ID	ARMCA9_CORE_ID	/* ARM Cortex A9 core (ihost) */
204
-#define GMAC_COMMON_4706_CORE_ID	0x5dc		/* Gigabit MAC core */
205
-#define GMAC_4706_CORE_ID	0x52d		/* Gigabit MAC core */
206244 #define AMEMC_CORE_ID		0x52e		/* DDR1/2 memory controller core */
207245 #define ALTA_CORE_ID		0x534		/* I2S core */
208246 #define DDR23_PHY_CORE_ID	0x5dd
....@@ -212,12 +250,9 @@
212250 #define SI_PCIE1_DMA_H32		0xc0000000	/* PCIE Client Mode sb2pcitranslation2
213251 						 * (2 ZettaBytes), high 32 bits
214252 						 */
215
-#define CC_4706B0_CORE_REV	0x8000001f		/* chipcommon core */
216
-#define SOCRAM_4706B0_CORE_REV	0x80000005		/* internal memory core */
217
-#define GMAC_4706B0_CORE_REV	0x80000000		/* Gigabit MAC core */
218253 #define NS_PCIEG2_CORE_REV_B0	0x7		/* NS-B0 PCIE Gen 2 core rev */
219254 
220
-/* There are TWO constants on all HND chips: SI_ENUM_BASE above,
255
+/* There are TWO constants on all HND chips: SI_ENUM_BASE_DEFAULT above,
221256  * and chipcommon being the first core:
222257  */
223258 #define	SI_CC_IDX		0
....@@ -226,6 +261,7 @@
226261 #define	SOCI_AI			1
227262 #define	SOCI_UBUS		2
228263 #define	SOCI_NAI		3
264
+#define SOCI_DVTBUS		4 /* BCM7XXX Digital Video Tech bus */
229265 
230266 /* Common core control flags */
231267 #define	SICF_BIST_EN		0x8000
....@@ -249,6 +285,10 @@
249285 #define SISF_NS_BOOTDEV_OFFLOAD	0x0003	/* ROM core */
250286 #define SISF_NS_SKUVEC_MASK	0x000c	/* ROM core */
251287 
288
+/* dot11 core-specific status flags */
289
+#define	SISF_MINORREV_D11_SHIFT	16
290
+#define	SISF_MINORREV_D11_MASK	0xF		/**< minor corerev (corerev == 61) */
291
+
252292 /* A register that is common to all cores to
253293  * communicate w/PMU regarding clock control.
254294  */
....@@ -266,6 +306,7 @@
266306 #define CCS_USBCLKREQ		0x00000100	/* USB Clock Req */
267307 #define CCS_SECICLKREQ		0x00000100	/* SECI Clock Req */
268308 #define CCS_ARMFASTCLOCKREQ	0x00000100	/* ARM CR4/CA7 fast clock request */
309
+#define CCS_SFLASH_CLKREQ	0x00000200	/* Sflash clk request */
269310 #define CCS_AVBCLKREQ		0x00000400	/* AVB Clock enable request */
270311 #define CCS_ERSRC_REQ_MASK	0x00000700	/* external resource requests */
271312 #define CCS_ERSRC_REQ_SHIFT	8
....@@ -276,9 +317,7 @@
276317 #define CCS_ARMFASTCLOCKSTATUS	0x01000000	/* Fast CPU clock is running */
277318 #define CCS_ERSRC_STS_MASK	0x07000000	/* external resource status */
278319 #define CCS_ERSRC_STS_SHIFT	24
279
-
280
-#define	CCS0_HTAVAIL		0x00010000	/* HT avail in chipc and pcmcia on 4328a0 */
281
-#define	CCS0_ALPAVAIL		0x00020000	/* ALP avail in chipc and pcmcia on 4328a0 */
320
+#define CCS_SECI_AVAIL		0x01000000	/* RO: SECI is available  */
282321 
283322 /* Not really related to SOC Interconnect, but a couple of software
284323  * conventions for the use the flash space:
....@@ -313,4 +352,5 @@
313352 int soc_knl_dev(void *sih);
314353 #endif	/* !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) */
315354 
355
+#define PMU_BASE_OFFSET	0x00012000	/* PMU offset is changed for ccrev >= 56 */
316356 #endif /* _HNDSOC_H */