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2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc 
 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/bcmsrom_tbl.h
....@@ -1,15 +1,16 @@
1
-/* SPDX-License-Identifier: GPL-2.0 */
21 /*
32  * Table that encodes the srom formats for PCI/PCIe NICs.
43  *
5
- * Copyright (C) 1999-2019, Broadcom Corporation
6
- * 
4
+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
5
+ *
6
+ * Copyright (C) 1999-2017, Broadcom Corporation
7
+ *
78  *      Unless you and Broadcom execute a separate written software license
89  * agreement governing use of this software, this software is licensed to you
910  * under the terms of the GNU General Public License version 2 (the "GPL"),
1011  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
1112  * following added to such license:
12
- * 
13
+ *
1314  *      As a special exception, the copyright holders of this software give you
1415  * permission to link this software with independent modules, and to copy and
1516  * distribute the resulting executable under terms of your choice, provided that
....@@ -17,7 +18,7 @@
1718  * the license of that module.  An independent module is a module which is not
1819  * derived from this software.  The special exception does not apply to any
1920  * modifications of the software.
20
- * 
21
+ *
2122  *      Notwithstanding the above, under no circumstances may you combine this
2223  * software in any way with any other Broadcom software provided under a license
2324  * other than the GPL, without Broadcom's express prior written consent.
....@@ -25,7 +26,7 @@
2526  *
2627  * <<Broadcom-WL-IPTag/Open:>>
2728  *
28
- * $Id: bcmsrom_tbl.h 553564 2015-04-30 06:19:30Z $
29
+ * $Id: bcmsrom_tbl.h 700323 2017-05-18 16:12:11Z $
2930  */
3031 
3132 #ifndef	_bcmsrom_tbl_h_
....@@ -54,7 +55,7 @@
5455 #define SRFL_ARRAY	0x100		/* value is in an array. All elements EXCEPT FOR THE LAST
5556 					 * ONE in the array should have this flag set.
5657 					 */
57
-
58
+#define PRHEX_N_MORE (SRFL_PRHEX | SRFL_MORE)
5859 
5960 #define SROM_DEVID_PCIE	48
6061 
....@@ -71,6 +72,7 @@
7172  * - The last entry's name field must be NULL to indicate the end of the table. Other
7273  *   entries must have non-NULL name.
7374  */
75
+#if !defined(SROM15_MEMOPT)
7476 static const sromvar_t pci_sromvars[] = {
7577 /*	name		revmask		flags		off			mask */
7678 #if defined(CABLECPE)
....@@ -79,7 +81,7 @@
7981 	{"devid",	0xffffff00,	SRFL_PRHEX, SROM_DEVID_PCIE,		0xffff},
8082 #else
8183 	{"devid",	0xffffff00,	SRFL_PRHEX|SRFL_NOVAR,	PCI_F0DEVID,	0xffff},
82
-#endif 
84
+#endif // endif
8385 	{"boardrev",	0x0000000e,	SRFL_PRHEX,	SROM_AABREV,		SROM_BR_MASK},
8486 	{"boardrev",	0x000000f0,	SRFL_PRHEX,	SROM4_BREV,		0xffff},
8587 	{"boardrev",	0xffffff00,	SRFL_PRHEX,	SROM8_BREV,		0xffff},
....@@ -109,9 +111,9 @@
109111 	{"boardnum",	0x00000700,	0,		SROM8_MACLO,		0xffff},
110112 	{"cc",		0x00000002,	0,		SROM_AABREV,		SROM_CC_MASK},
111113 	{"regrev",	0x00000008,	0,		SROM_OPO,		0xff00},
112
-	{"regrev",	0x00000010,	0,		SROM4_REGREV,		0x00ff},
113
-	{"regrev",	0x000000e0,	0,		SROM5_REGREV,		0x00ff},
114
-	{"regrev",	0x00000700,	0,		SROM8_REGREV,		0x00ff},
114
+	{"regrev",	0x00000010,	0,		SROM4_REGREV,		0xffff},
115
+	{"regrev",	0x000000e0,	0,		SROM5_REGREV,		0xffff},
116
+	{"regrev",	0x00000700,	0,		SROM8_REGREV,		0xffff},
115117 	{"ledbh0",	0x0000000e,	SRFL_NOFFS,	SROM_LEDBH10,		0x00ff},
116118 	{"ledbh1",	0x0000000e,	SRFL_NOFFS,	SROM_LEDBH10,		0xff00},
117119 	{"ledbh2",	0x0000000e,	SRFL_NOFFS,	SROM_LEDBH32,		0x00ff},
....@@ -474,7 +476,7 @@
474476 	{"boardnum",	0xfffff800,	0,			SROM11_MACLO,	0xffff},
475477 	{"macaddr",	0xfffff800,	SRFL_ETHADDR,		SROM11_MACHI,	0xffff},
476478 	{"ccode",	0xfffff800,	SRFL_CCODE,		SROM11_CCODE,	0xffff},
477
-	{"regrev",	0xfffff800,	0,			SROM11_REGREV,	0x00ff},
479
+	{"regrev",	0xfffff800,	0,			SROM11_REGREV,	0xffff},
478480 	{"ledbh0",	0xfffff800,	SRFL_NOFFS,		SROM11_LEDBH10,	0x00ff},
479481 	{"ledbh1",	0xfffff800,	SRFL_NOFFS,		SROM11_LEDBH10,	0xff00},
480482 	{"ledbh2",	0xfffff800,	SRFL_NOFFS,		SROM11_LEDBH32,	0x00ff},
....@@ -514,6 +516,7 @@
514516 	{"tempcorrx",		0xfffff800,	SRFL_PRHEX, 	SROM11_TS_SLP_OPT_CORRX, 0xfc00},
515517 	{"tempsense_option",	0xfffff800,	SRFL_PRHEX,	SROM11_TS_SLP_OPT_CORRX, 0x0300},
516518 	{"xtalfreq",		0xfffff800,	0,		SROM11_XTAL_FREQ, 	0xffff},
519
+	{"txpwrbckof",	0x00000800,	SRFL_PRHEX,	SROM11_PATH0 + SROM11_2G_MAXP,	0xff00},
517520 	/* Special PA Params for 4350 5G Band, 40/80 MHz BW Ant #1 */
518521 	{"pa5gbw4080a1", 0xfffff800,	SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_4080_W0_A1, 0xffff},
519522 	{"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_4080_W1_A1,                 0xffff},
....@@ -710,16 +713,6 @@
710713 	{"pdoffset20in80m5gb3", 0xfffff000,	0,      SROM12_PDOFF_20in80M_5G_B3,    0xffff},
711714 	{"pdoffset20in80m5gb4", 0xfffff000,	0,      SROM12_PDOFF_20in80M_5G_B4,    0xffff},
712715 
713
-	{"pdoffset20in40m5gcore3",   0xffffe000, 0,     SROM13_PDOFFSET20IN40M5GCORE3,   0xffff},
714
-	{"pdoffset20in40m5gcore3_1", 0xffffe000, 0,     SROM13_PDOFFSET20IN40M5GCORE3_1, 0xffff},
715
-	{"pdoffset20in80m5gcore3",   0xffffe000, 0,     SROM13_PDOFFSET20IN80M5GCORE3,   0xffff},
716
-	{"pdoffset20in80m5gcore3_1", 0xffffe000, 0,     SROM13_PDOFFSET20IN80M5GCORE3_1, 0xffff},
717
-	{"pdoffset40in80m5gcore3",   0xffffe000, 0,     SROM13_PDOFFSET40IN80M5GCORE3,   0xffff},
718
-	{"pdoffset40in80m5gcore3_1", 0xffffe000, 0,     SROM13_PDOFFSET40IN80M5GCORE3_1, 0xffff},
719
-
720
-	{"pdoffset20in40m2g",        0xffffe000, 0,     SROM13_PDOFFSET20IN40M2G,        0xffff},
721
-	{"pdoffset20in40m2gcore3",   0xffffe000, 0,     SROM13_PDOFFSET20IN40M2GCORE3,   0xffff},
722
-
723716 	/* power per rate */
724717 	{"mcsbw205gx1po",       0xfffff000,     SRFL_MORE,      SROM12_MCSBW205GX1PO,   0xffff},
725718 	{"",                    0xfffff000,     0,              SROM12_MCSBW205GX1PO_1, 0xffff},
....@@ -767,6 +760,15 @@
767760 	{"gpdn",		0xfffff000,	SRFL_PRHEX|SRFL_MORE,	SROM12_GPDN_L,	0xffff},
768761 	{"",			0,		0,			SROM12_GPDN_H,	0xffff},
769762 
763
+	{"rpcal2gcore3",        0xffffe000, 	0,	SROM13_RPCAL2GCORE3,            0x00ff},
764
+	{"rpcal5gb0core3",      0xffffe000, 	0,	SROM13_RPCAL5GB01CORE3,         0x00ff},
765
+	{"rpcal5gb1core3",      0xffffe000, 	0,	SROM13_RPCAL5GB01CORE3,         0xff00},
766
+	{"rpcal5gb2core3",      0xffffe000, 	0,	SROM13_RPCAL5GB23CORE3,         0x00ff},
767
+	{"rpcal5gb3core3",      0xffffe000, 	0,	SROM13_RPCAL5GB23CORE3,         0xff00},
768
+
769
+	{"sw_txchain_mask",	0xffffe000,	0,	SROM13_SW_TXRX_MASK,	0x000f},
770
+	{"sw_rxchain_mask",	0xffffe000,	0,	SROM13_SW_TXRX_MASK,	0x00f0},
771
+
770772 	{"eu_edthresh2g",       0x00002000,     0,       SROM13_EU_EDCRSTH,     0x00ff},
771773 	{"eu_edthresh5g",       0x00002000,     0,       SROM13_EU_EDCRSTH,     0xff00},
772774 
....@@ -788,6 +790,18 @@
788790 	{"rxgains5ghelnagaina3",        0xffffe000,     0,       SROM13_RXGAINS1CORE3,  0x0700},
789791 	{"rxgains5ghtrisoa3",   0xffffe000,     0,       SROM13_RXGAINS1CORE3,  0x7800},
790792 	{"rxgains5ghtrelnabypa3", 0xffffe000,   0,       SROM13_RXGAINS1CORE3,  0x8000},
793
+
794
+	/* pdoffset */
795
+	{"pdoffset20in40m5gcore3",   0xffffe000, 0,     SROM13_PDOFFSET20IN40M5GCORE3,   0xffff},
796
+	{"pdoffset20in40m5gcore3_1", 0xffffe000, 0,     SROM13_PDOFFSET20IN40M5GCORE3_1, 0xffff},
797
+	{"pdoffset20in80m5gcore3",   0xffffe000, 0,     SROM13_PDOFFSET20IN80M5GCORE3,   0xffff},
798
+	{"pdoffset20in80m5gcore3_1", 0xffffe000, 0,     SROM13_PDOFFSET20IN80M5GCORE3_1, 0xffff},
799
+	{"pdoffset40in80m5gcore3",   0xffffe000, 0,     SROM13_PDOFFSET40IN80M5GCORE3,   0xffff},
800
+	{"pdoffset40in80m5gcore3_1", 0xffffe000, 0,     SROM13_PDOFFSET40IN80M5GCORE3_1, 0xffff},
801
+
802
+	{"pdoffset20in40m2g",        0xffffe000, 0,     SROM13_PDOFFSET20IN40M2G,        0xffff},
803
+	{"pdoffset20in40m2gcore3",   0xffffe000, 0,     SROM13_PDOFFSET20IN40M2GCORE3,   0xffff},
804
+	{"pdoffsetcck20m",           0xffffe000, 0,     SROM13_PDOFF_2G_CCK_20M,         0xffff},
791805 
792806 	/* power per rate */
793807 	{"mcs1024qam2gpo",      0xffffe000,     0,           SROM13_MCS1024QAM2GPO,     0xffff},
....@@ -853,16 +867,6 @@
853867 
854868 	{"sb20in40hrlrpox",     0xffffe000,     0,       SROM13_SB20IN40HRLRPOX,        0xffff},
855869 
856
-	{"pdoffset20in40m2g",   0xffffe000,     0,      SROM13_PDOFFSET20IN40M2G,       0xffff},
857
-	{"pdoffset20in40m2gcore3", 0xffffe000,  0,      SROM13_PDOFFSET20IN40M2GCORE3,  0xffff},
858
-
859
-	{"pdoffset20in40m5gcore3", 0xffffe000, SRFL_MORE, SROM13_PDOFFSET20IN40M5GCORE3, 0xffff},
860
-	{"",                    0xffffe000,     0,  SROM13_PDOFFSET20IN40M5GCORE3_1,   0xffff},
861
-	{"pdoffset40in80m5gcore3", 0xffffe000, SRFL_MORE, SROM13_PDOFFSET40IN80M5GCORE3, 0xffff},
862
-	{"",                    0xffffe000,     0,  SROM13_PDOFFSET40IN80M5GCORE3_1,   0xffff},
863
-	{"pdoffset20in80m5gcore3", 0xffffe000, SRFL_MORE, SROM13_PDOFFSET20IN80M5GCORE3, 0xffff},
864
-	{"",                    0xffffe000,     0,  SROM13_PDOFFSET20IN80M5GCORE3_1,   0xffff},
865
-
866870 	{"swctrlmap4_cfg",      0xffffe000,     0,      SROM13_SWCTRLMAP4_CFG,          0xffff},
867871 	{"swctrlmap4_TX2g_fem3to0", 0xffffe000, 0,      SROM13_SWCTRLMAP4_TX2G_FEM3TO0, 0xffff},
868872 	{"swctrlmap4_RX2g_fem3to0", 0xffffe000, 0,      SROM13_SWCTRLMAP4_RX2G_FEM3TO0, 0xffff},
....@@ -881,6 +885,57 @@
881885 	{"swctrlmap4_RXByp5g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_RXBYP5G_FEM7TO4, 0xffff},
882886 	{"swctrlmap4_misc5g_fem7to4", 0xffffe000, 0,  SROM13_SWCTRLMAP4_MISC5G_FEM7TO4, 0xffff},
883887 	{NULL,		0,		0,		0,			0}
888
+};
889
+#endif /* !defined(SROM15_MEMOPT) */
890
+
891
+static const sromvar_t pci_srom15vars[] = {
892
+	{"macaddr",	0x00008000,	SRFL_ETHADDR,		SROM15_MACHI,	0xffff},
893
+	{"caldata_offset", 0x00008000, 0, SROM15_CAL_OFFSET_LOC, 0xffff},
894
+	{"boardrev", 0x00008000, SRFL_PRHEX, SROM15_BRDREV, 0xffff},
895
+	{"ccode", 0x00008000, SRFL_CCODE, SROM15_CCODE, 0xffff},
896
+	{"regrev", 0x00008000, 0, SROM15_REGREV, 0xffff},
897
+	{NULL,		0,		0,		0,			0}
898
+};
899
+
900
+static const sromvar_t pci_srom16vars[] = {
901
+	{"macaddr",		0x00010000,	SRFL_ETHADDR,	SROM16_MACHI,		0xffff},
902
+	{"caldata_offset",	0x00010000,	0,	SROM16_CALDATA_OFFSET_LOC,	0xffff},
903
+	{"boardrev",		0x00010000,	0,		SROM16_BOARDREV,	0xffff},
904
+	{"ccode",		0x00010000,	0,		SROM16_CCODE,		0xffff},
905
+	{"regrev",		0x00010000,	0,		SROM16_REGREV,		0xffff},
906
+	{NULL,			0,		0,		0,			0}
907
+};
908
+
909
+static const sromvar_t pci_srom17vars[] = {
910
+	{"boardrev",	0x00020000,	SRFL_PRHEX,	SROM17_BRDREV,		0xffff},
911
+	{"macaddr",	0x00020000,	SRFL_ETHADDR,	SROM17_MACADDR,		0xffff},
912
+	{"ccode",		0x00020000,	SRFL_CCODE,	SROM17_CCODE,		0xffff},
913
+	{"caldata_offset",	0x00020000,	0,		SROM17_CALDATA,		0xffff},
914
+	{"gain_cal_temp",	0x00020000,	SRFL_PRHEX,	SROM17_GCALTMP,		0xffff},
915
+	{"rssi_delta_2gb0_c0", 0x00020000,	PRHEX_N_MORE,	SROM17_C0SRD202G,	0xffff},
916
+	{"",		0x00020000,	0,		SROM17_C0SRD202G_1,	0xffff},
917
+	{"rssi_delta_5gl_c0", 0x00020000,	PRHEX_N_MORE,	SROM17_C0SRD205GL,	0xffff},
918
+	{"",		0x00020000,	0,		SROM17_C0SRD205GL_1,	0xffff},
919
+	{"rssi_delta_5gml_c0", 0x00020000,	PRHEX_N_MORE,	SROM17_C0SRD205GML,	0xffff},
920
+	{"",		0x00020000,	0,		SROM17_C0SRD205GML_1,	0xffff},
921
+	{"rssi_delta_5gmu_c0", 0x00020000,	PRHEX_N_MORE,	SROM17_C0SRD205GMU,	0xffff},
922
+	{"",		0x00020000,	0,		SROM17_C0SRD205GMU_1,	0xffff},
923
+	{"rssi_delta_5gh_c0", 0x00020000,	PRHEX_N_MORE,	SROM17_C0SRD205GH,	0xffff},
924
+	{"",		0x00020000,	0,		SROM17_C0SRD205GH_1,	0xffff},
925
+	{"rssi_delta_2gb0_c1", 0x00020000,	PRHEX_N_MORE,	SROM17_C1SRD202G,	0xffff},
926
+	{"",		0x00020000,	0,		SROM17_C1SRD202G_1,	0xffff},
927
+	{"rssi_delta_5gl_c1", 0x00020000,	PRHEX_N_MORE,	SROM17_C1SRD205GL,	0xffff},
928
+	{"",		0x00020000,	0,		SROM17_C1SRD205GL_1,	0xffff},
929
+	{"rssi_delta_5gml_c1", 0x00020000,	PRHEX_N_MORE,	SROM17_C1SRD205GML,	0xffff},
930
+	{"",		0x00020000,	0,		SROM17_C1SRD205GML_1,	0xffff},
931
+	{"rssi_delta_5gmu_c1", 0x00020000,	PRHEX_N_MORE,	SROM17_C1SRD205GMU,	0xffff},
932
+	{"",		0x00020000,	0,		SROM17_C1SRD205GMU_1,	0xffff},
933
+	{"rssi_delta_5gh_c1", 0x00020000,	PRHEX_N_MORE,	SROM17_C1SRD205GH,	0xffff},
934
+	{"",		0x00020000,	0,		SROM17_C1SRD205GH_1,	0xffff},
935
+	{"txpa_trim_magic",	0x00020000,	PRHEX_N_MORE,	SROM17_TRAMMAGIC,	0xffff},
936
+	{"",		0x00020000,	0,		SROM17_TRAMMAGIC_1,	0xffff},
937
+	{"txpa_trim_data",	0x00020000,	SRFL_PRHEX,	SROM17_TRAMDATA,	0xffff},
938
+	{NULL,		0,		0,		0,			0x00}
884939 };
885940 
886941 static const sromvar_t perpath_pci_sromvars[] = {
....@@ -1059,8 +1114,7 @@
10591114 	{NULL,		0,		0,		0, 			0}
10601115 };
10611116 
1062
-#if !(defined(PHY_TYPE_HT) && defined(PHY_TYPE_N))
1063
-#define	PHY_TYPE_HT		7	/* HT-Phy value */
1117
+#if !defined(PHY_TYPE_N)
10641118 #define	PHY_TYPE_N		4	/* N-Phy value */
10651119 #endif /* !(defined(PHY_TYPE_HT) && defined(PHY_TYPE_N)) */
10661120 #if !defined(PHY_TYPE_AC)
....@@ -1081,22 +1135,6 @@
10811135 } pavars_t;
10821136 
10831137 static const pavars_t pavars[] = {
1084
-	/* HTPHY */
1085
-	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_2G,  0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"},
1086
-	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_2G,  1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"},
1087
-	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_2G,  2, "pa2gw0a2 pa2gw1a2 pa2gw2a2"},
1088
-	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND0, 0, "pa5glw0a0 pa5glw1a0 pa5glw2a0"},
1089
-	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND0, 1, "pa5glw0a1 pa5glw1a1 pa5glw2a1"},
1090
-	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND0, 2, "pa5glw0a2 pa5glw1a2 pa5glw2a2"},
1091
-	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND1, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"},
1092
-	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND1, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"},
1093
-	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND1, 2, "pa5gw0a2 pa5gw1a2 pa5gw2a2"},
1094
-	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND2, 0, "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"},
1095
-	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND2, 1, "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"},
1096
-	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND2, 2, "pa5ghw0a2 pa5ghw1a2 pa5ghw2a2"},
1097
-	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND3, 0, "pa5gw0a3 pa5gw1a3 pa5gw2a3"},
1098
-	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND3, 1,  "pa5glw0a3 pa5glw1a3 pa5glw2a3"},
1099
-	{PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5G_BAND3, 2, "pa5ghw0a3 pa5ghw1a3 pa5ghw2a3"},
11001138 	/* NPHY */
11011139 	{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G,  0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"},
11021140 	{PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G,  1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"},
....@@ -1117,7 +1155,6 @@
11171155 	{PHY_TYPE_LCN20, WL_CHAN_FREQ_RANGE_2G,  0, "pa2ga0"},
11181156 	{PHY_TYPE_NULL, 0, 0, ""}
11191157 };
1120
-
11211158 
11221159 static const pavars_t pavars_SROM12[] = {
11231160 	/* ACPHY */
....@@ -1285,7 +1322,7 @@
12851322 	{HNBU_LEDDC,		0xffffffff, 3, "2leddc"},
12861323 	{HNBU_RDLRNDIS,		0xffffffff, 2, "1rdlndis"},
12871324 	{HNBU_CHAINSWITCH,	0xffffffff, 5, "1txchain 1rxchain 2antswitch"},
1288
-	{HNBU_REGREV,		0xffffffff, 2, "1regrev"},
1325
+	{HNBU_REGREV,		0xffffffff, 3, "2regrev"},
12891326 	{HNBU_FEM,		0x000007fe, 5, "0antswctl2g 0triso2g 0pdetrange2g 0extpagain2g "
12901327 	"0tssipos2g 0antswctl5g 0triso5g 0pdetrange5g 0extpagain5g 0tssipos5g"}, /* special case */
12911328 	{HNBU_PAPARMS_C0,	0x000007fe, 31, "1maxp2ga0 1itt2ga0 2pa2gw0a0 2pa2gw1a0 "
....@@ -1335,10 +1372,10 @@
13351372 	{HNBU_FEM_CFG,		0xfffff800, 5,	"0femctrl 0papdcap2g 0tworangetssi2g 0pdgain2g "
13361373 	"0epagain2g 0tssiposslope2g 0gainctrlsph 0papdcap5g 0tworangetssi5g 0pdgain5g 0epagain5g "
13371374 	"0tssiposslope5g"}, /* special case */
1338
-	{HNBU_ACPA_C0,		0xfffff800, 39,	"2subband5gver 2maxp2ga0 2*3pa2ga0 "
1375
+	{HNBU_ACPA_C0,		0x00001800, 39,	"2subband5gver 2maxp2ga0 2*3pa2ga0 "
13391376 	"1*4maxp5ga0 2*12pa5ga0"},
1340
-	{HNBU_ACPA_C1,		0xfffff800, 37,	"2maxp2ga1 2*3pa2ga1 1*4maxp5ga1 2*12pa5ga1"},
1341
-	{HNBU_ACPA_C2,		0xfffff800, 37,	"2maxp2ga2 2*3pa2ga2 1*4maxp5ga2 2*12pa5ga2"},
1377
+	{HNBU_ACPA_C1,		0x00001800, 37,	"2maxp2ga1 2*3pa2ga1 1*4maxp5ga1 2*12pa5ga1"},
1378
+	{HNBU_ACPA_C2,		0x00001800, 37,	"2maxp2ga2 2*3pa2ga2 1*4maxp5ga2 2*12pa5ga2"},
13421379 	{HNBU_MEAS_PWR,		0xfffff800, 5,	"1measpower 1measpower1 1measpower2 2rawtempsense"},
13431380 	{HNBU_PDOFF,		0xfffff800, 13,	"2pdoffset40ma0 2pdoffset40ma1 2pdoffset40ma2 "
13441381 	"2pdoffset80ma0 2pdoffset80ma1 2pdoffset80ma2"},
....@@ -1386,15 +1423,37 @@
13861423 	"2tx_duty_cycle_thresh_40_5g 2tx_duty_cycle_ofdm_80_5g 2tx_duty_cycle_thresh_80_5g"},
13871424 	{HNBU_PDOFF_2G,		0xfffff800, 3,	"0pdoffset2g40ma0 0pdoffset2g40ma1 "
13881425 	"0pdoffset2g40ma2 0pdoffset2g40mvalid"},
1389
-	{HNBU_ACPA_CCK,		0xfffff800, 7,	"2*3pa2gccka0"},
1426
+	{HNBU_ACPA_CCK_C0,	0xfffff800, 7,  "2*3pa2gccka0"},
1427
+	{HNBU_ACPA_CCK_C1,	0xfffff800, 7,  "2*3pa2gccka1"},
13901428 	{HNBU_ACPA_40,		0xfffff800, 25,	"2*12pa5gbw40a0"},
13911429 	{HNBU_ACPA_80,		0xfffff800, 25,	"2*12pa5gbw80a0"},
13921430 	{HNBU_ACPA_4080,	0xfffff800, 49,	"2*12pa5gbw4080a0 2*12pa5gbw4080a1"},
1431
+	{HNBU_ACPA_4X4C0,	0xffffe000, 23, "1maxp2ga0 2*4pa2ga0 2*4pa2g40a0 "
1432
+	"1maxp5gb0a0 1maxp5gb1a0 1maxp5gb2a0 1maxp5gb3a0 1maxp5gb4a0"},
1433
+	{HNBU_ACPA_4X4C1,	0xffffe000, 23, "1maxp2ga1 2*4pa2ga1 2*4pa2g40a1 "
1434
+	"1maxp5gb0a1 1maxp5gb1a1 1maxp5gb2a1 1maxp5gb3a1 1maxp5gb4a1"},
1435
+	{HNBU_ACPA_4X4C2,	0xffffe000, 23, "1maxp2ga2 2*4pa2ga2 2*4pa2g40a2 "
1436
+	"1maxp5gb0a2 1maxp5gb1a2 1maxp5gb2a2 1maxp5gb3a2 1maxp5gb4a2"},
1437
+	{HNBU_ACPA_4X4C3,	0xffffe000, 23, "1maxp2ga3 2*4pa2ga3 2*4pa2g40a3 "
1438
+	"1maxp5gb0a3 1maxp5gb1a3 1maxp5gb2a3 1maxp5gb3a3 1maxp5gb4a3"},
1439
+	{HNBU_ACPA_BW20_4X4C0,	0xffffe000, 41, "2*20pa5ga0"},
1440
+	{HNBU_ACPA_BW40_4X4C0,	0xffffe000, 41, "2*20pa5g40a0"},
1441
+	{HNBU_ACPA_BW80_4X4C0,	0xffffe000, 41, "2*20pa5g80a0"},
1442
+	{HNBU_ACPA_BW20_4X4C1,	0xffffe000, 41, "2*20pa5ga1"},
1443
+	{HNBU_ACPA_BW40_4X4C1,	0xffffe000, 41, "2*20pa5g40a1"},
1444
+	{HNBU_ACPA_BW80_4X4C1,	0xffffe000, 41, "2*20pa5g80a1"},
1445
+	{HNBU_ACPA_BW20_4X4C2,	0xffffe000, 41, "2*20pa5ga2"},
1446
+	{HNBU_ACPA_BW40_4X4C2,	0xffffe000, 41, "2*20pa5g40a2"},
1447
+	{HNBU_ACPA_BW80_4X4C2,	0xffffe000, 41, "2*20pa5g80a2"},
1448
+	{HNBU_ACPA_BW20_4X4C3,	0xffffe000, 41, "2*20pa5ga3"},
1449
+	{HNBU_ACPA_BW40_4X4C3,	0xffffe000, 41, "2*20pa5g40a3"},
1450
+	{HNBU_ACPA_BW80_4X4C3,	0xffffe000, 41, "2*20pa5g80a3"},
13931451 	{HNBU_SUBBAND5GVER,	0xfffff800, 3,	"2subband5gver"},
13941452 	{HNBU_PAPARAMBWVER,	0xfffff800, 2,	"1paparambwver"},
13951453 	{HNBU_TXBFRPCALS,  0xfffff800, 11,
13961454 	"2rpcal2g 2rpcal5gb0 2rpcal5gb1 2rpcal5gb2 2rpcal5gb3"}, /* txbf rpcalvars */
13971455 	{HNBU_GPIO_PULL_DOWN,	0xffffffff, 5, "4gpdn"},
1456
+	{HNBU_MACADDR2,		0xffffffff, 7, "6macaddr2"},	/* special case */
13981457 	{0xFF,			0xffffffff, 0, ""}
13991458 };
14001459