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| 1 | | -/* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | 1 | /* |
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| 3 | 2 | * 'Standard' SDIO HOST CONTROLLER driver |
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| 4 | 3 | * |
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| 5 | | - * Copyright (C) 1999-2019, Broadcom Corporation |
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| 6 | | - * |
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| 4 | + * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation |
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| 5 | + * |
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| 6 | + * Copyright (C) 1999-2017, Broadcom Corporation |
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| 7 | + * |
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| 7 | 8 | * Unless you and Broadcom execute a separate written software license |
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| 8 | 9 | * agreement governing use of this software, this software is licensed to you |
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| 9 | 10 | * under the terms of the GNU General Public License version 2 (the "GPL"), |
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| 10 | 11 | * available at http://www.broadcom.com/licenses/GPLv2.php, with the |
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| 11 | 12 | * following added to such license: |
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| 12 | | - * |
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| 13 | + * |
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| 13 | 14 | * As a special exception, the copyright holders of this software give you |
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| 14 | 15 | * permission to link this software with independent modules, and to copy and |
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| 15 | 16 | * distribute the resulting executable under terms of your choice, provided that |
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| .. | .. |
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| 17 | 18 | * the license of that module. An independent module is a module which is not |
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| 18 | 19 | * derived from this software. The special exception does not apply to any |
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| 19 | 20 | * modifications of the software. |
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| 20 | | - * |
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| 21 | + * |
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| 21 | 22 | * Notwithstanding the above, under no circumstances may you combine this |
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| 22 | 23 | * software in any way with any other Broadcom software provided under a license |
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| 23 | 24 | * other than the GPL, without Broadcom's express prior written consent. |
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| .. | .. |
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| 25 | 26 | * |
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| 26 | 27 | * <<Broadcom-WL-IPTag/Open:>> |
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| 27 | 28 | * |
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| 28 | | - * $Id: bcmsdstd.h 514727 2014-11-12 03:02:48Z $ |
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| 29 | + * $Id: bcmsdstd.h 663318 2016-10-04 19:02:16Z $ |
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| 29 | 30 | */ |
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| 30 | 31 | #ifndef _BCM_SD_STD_H |
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| 31 | 32 | #define _BCM_SD_STD_H |
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| .. | .. |
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| 82 | 83 | #define SDIOH_CMD7_EXP_STATUS 0x00001E00 |
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| 83 | 84 | |
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| 84 | 85 | #define RETRIES_LARGE 100000 |
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| 86 | +#ifdef BCMQT |
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| 87 | +extern void sdstd_os_yield(sdioh_info_t *sd); |
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| 88 | +#define RETRIES_SMALL 10000 |
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| 89 | +#else |
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| 85 | 90 | #define sdstd_os_yield(sd) do {} while (0) |
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| 86 | 91 | #define RETRIES_SMALL 100 |
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| 87 | | - |
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| 92 | +#endif // endif |
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| 88 | 93 | |
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| 89 | 94 | #define USE_BLOCKMODE 0x2 /* Block mode can be single block or multi */ |
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| 90 | 95 | #define USE_MULTIBLOCK 0x4 |
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| .. | .. |
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| 94 | 99 | #define CLIENT_INTR 0x100 /* Get rid of this! */ |
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| 95 | 100 | |
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| 96 | 101 | #define HC_INTR_RETUNING 0x1000 |
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| 97 | | - |
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| 98 | 102 | |
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| 99 | 103 | #ifdef BCMSDIOH_TXGLOM |
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| 100 | 104 | /* Total glom pkt can not exceed 64K |
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| .. | .. |
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| 108 | 112 | ulong dma_phys_arr[SDIOH_MAXGLOM_SIZE]; /* DMA_MAPed address of frames */ |
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| 109 | 113 | uint16 nbytes[SDIOH_MAXGLOM_SIZE]; /* Size of each frame */ |
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| 110 | 114 | } glom_buf_t; |
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| 111 | | -#endif |
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| 115 | +#endif // endif |
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| 112 | 116 | |
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| 113 | 117 | struct sdioh_info { |
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| 114 | | - uint cfg_bar; /* pci cfg address for bar */ |
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| 115 | | - uint32 caps; /* cached value of capabilities reg */ |
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| 116 | | - uint32 curr_caps; /* max current capabilities reg */ |
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| 118 | + uint cfg_bar; /* pci cfg address for bar */ |
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| 119 | + uint32 caps; /* cached value of capabilities reg */ |
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| 120 | + uint32 curr_caps; /* max current capabilities reg */ |
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| 117 | 121 | |
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| 118 | | - osl_t *osh; /* osh handler */ |
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| 119 | | - volatile char *mem_space; /* pci device memory va */ |
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| 120 | | - uint lockcount; /* nest count of sdstd_lock() calls */ |
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| 122 | + osl_t *osh; /* osh handler */ |
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| 123 | + volatile char *mem_space; /* pci device memory va */ |
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| 124 | + uint lockcount; /* nest count of sdstd_lock() calls */ |
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| 121 | 125 | bool client_intr_enabled; /* interrupt connnected flag */ |
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| 122 | 126 | bool intr_handler_valid; /* client driver interrupt handler valid */ |
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| 123 | 127 | sdioh_cb_fn_t intr_handler; /* registered interrupt handler */ |
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| .. | .. |
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| 163 | 167 | ulong adma2_dscr_start_phys; |
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| 164 | 168 | uint alloced_adma2_dscr_size; |
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| 165 | 169 | |
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| 166 | | - int r_cnt; /* rx count */ |
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| 167 | | - int t_cnt; /* tx_count */ |
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| 170 | + int r_cnt; /* rx count */ |
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| 171 | + int t_cnt; /* tx_count */ |
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| 168 | 172 | bool got_hcint; /* local interrupt flag */ |
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| 169 | 173 | uint16 last_intrstatus; /* to cache intrstatus */ |
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| 170 | | - int host_UHSISupported; /* whether UHSI is supported for HC. */ |
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| 171 | | - int card_UHSI_voltage_Supported; /* whether UHSI is supported for |
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| 174 | + int host_UHSISupported; /* whether UHSI is supported for HC. */ |
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| 175 | + int card_UHSI_voltage_Supported; /* whether UHSI is supported for |
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| 172 | 176 | * Card in terms of Voltage [1.8 or 3.3]. |
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| 173 | 177 | */ |
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| 174 | 178 | int global_UHSI_Supp; /* type of UHSI support in both host and card. |
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| .. | .. |
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| 176 | 180 | * HOST_SDR_12_25: SDR12 and SDR25 supported |
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| 177 | 181 | * HOST_SDR_50_104_DDR: one of SDR50/SDR104 or DDR50 supptd |
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| 178 | 182 | */ |
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| 179 | | - volatile int sd3_dat_state; /* data transfer state used for retuning check */ |
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| 180 | | - volatile int sd3_tun_state; /* tuning state used for retuning check */ |
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| 181 | | - bool sd3_tuning_reqd; /* tuning requirement parameter */ |
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| 183 | + volatile int sd3_dat_state; /* data transfer state used for retuning check */ |
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| 184 | + volatile int sd3_tun_state; /* tuning state used for retuning check */ |
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| 185 | + bool sd3_tuning_reqd; /* tuning requirement parameter */ |
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| 186 | + bool sd3_tuning_disable; /* tuning disable due to bus sleeping */ |
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| 182 | 187 | uint32 caps3; /* cached value of 32 MSbits capabilities reg (SDIO 3.0) */ |
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| 183 | 188 | #ifdef BCMSDIOH_TXGLOM |
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| 184 | 189 | glom_buf_t glom_info; /* pkt information used for glomming */ |
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| 185 | 190 | uint txglom_mode; /* Txglom mode: 0 - copy, 1 - multi-descriptor */ |
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| 186 | | -#endif |
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| 191 | +#endif // endif |
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| 187 | 192 | }; |
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| 188 | 193 | |
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| 189 | 194 | #define DMA_MODE_NONE 0 |
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| .. | .. |
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| 207 | 212 | #define CHECK_TUNING_PRE_DATA 1 |
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| 208 | 213 | #define CHECK_TUNING_POST_DATA 2 |
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| 209 | 214 | |
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| 210 | | - |
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| 211 | 215 | #ifdef DHD_DEBUG |
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| 212 | 216 | #define SD_DHD_DISABLE_PERIODIC_TUNING 0x01 |
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| 213 | 217 | #define SD_DHD_ENABLE_PERIODIC_TUNING 0x00 |
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| 214 | | -#endif |
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| 215 | | - |
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| 218 | +#endif // endif |
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| 216 | 219 | |
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| 217 | 220 | /************************************************************ |
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| 218 | 221 | * Internal interfaces: per-port references into bcmsdstd.c |
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| .. | .. |
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| 234 | 237 | |
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| 235 | 238 | /* Wait for specified interrupt and error bits to be set */ |
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| 236 | 239 | extern void sdstd_spinbits(sdioh_info_t *sd, uint16 norm, uint16 err); |
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| 237 | | - |
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| 238 | 240 | |
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| 239 | 241 | /************************************************************** |
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| 240 | 242 | * Internal interfaces: bcmsdstd.c references to per-port code |
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