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2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc 
 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/bcmpcie.h
....@@ -1,17 +1,18 @@
1
-/* SPDX-License-Identifier: GPL-2.0 */
21 /*
32  * Broadcom PCIE
43  * Software-specific definitions shared between device and host side
54  * Explains the shared area between host and dongle
65  *
7
- * Copyright (C) 1999-2019, Broadcom Corporation
8
- * 
6
+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
7
+ *
8
+ * Copyright (C) 1999-2017, Broadcom Corporation
9
+ *
910  *      Unless you and Broadcom execute a separate written software license
1011  * agreement governing use of this software, this software is licensed to you
1112  * under the terms of the GNU General Public License version 2 (the "GPL"),
1213  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
1314  * following added to such license:
14
- * 
15
+ *
1516  *      As a special exception, the copyright holders of this software give you
1617  * permission to link this software with independent modules, and to copy and
1718  * distribute the resulting executable under terms of your choice, provided that
....@@ -19,7 +20,7 @@
1920  * the license of that module.  An independent module is a module which is not
2021  * derived from this software.  The special exception does not apply to any
2122  * modifications of the software.
22
- * 
23
+ *
2324  *      Notwithstanding the above, under no circumstances may you combine this
2425  * software in any way with any other Broadcom software provided under a license
2526  * other than the GPL, without Broadcom's express prior written consent.
....@@ -27,14 +28,13 @@
2728  *
2829  * <<Broadcom-WL-IPTag/Open:>>
2930  *
30
- * $Id: bcmpcie.h 542048 2015-03-18 15:37:26Z $
31
+ * $Id$
3132  */
32
-
3333 
3434 #ifndef	_bcmpcie_h_
3535 #define	_bcmpcie_h_
3636 
37
-#include <bcmutils.h>
37
+#include <typedefs.h>
3838 
3939 #define ADDR_64(x)			(x.addr)
4040 #define HIGH_ADDR_32(x)     ((uint32) (((sh_addr_t) x).high_addr))
....@@ -45,17 +45,18 @@
4545 	uint32 high_addr;
4646 } sh_addr_t;
4747 
48
-
4948 /* May be overridden by 43xxxxx-roml.mk */
5049 #if !defined(BCMPCIE_MAX_TX_FLOWS)
5150 #define BCMPCIE_MAX_TX_FLOWS	40
5251 #endif /* ! BCMPCIE_MAX_TX_FLOWS */
5352 
53
+#define PCIE_SHARED_VERSION_7		0x00007
54
+#define PCIE_SHARED_VERSION_6		0x00006 /* rev6 is compatible with rev 5 */
55
+#define PCIE_SHARED_VERSION_5		0x00005 /* rev6 is compatible with rev 5 */
5456 /**
5557  * Feature flags enabled in dongle. Advertised by dongle to DHD via the PCIe Shared structure that
5658  * is located in device memory.
5759  */
58
-#define PCIE_SHARED_VERSION		0x00005
5960 #define PCIE_SHARED_VERSION_MASK	0x000FF
6061 #define PCIE_SHARED_ASSERT_BUILT	0x00100
6162 #define PCIE_SHARED_ASSERT		0x00200
....@@ -63,7 +64,7 @@
6364 #define PCIE_SHARED_IN_BRPT		0x00800
6465 #define PCIE_SHARED_SET_BRPT		0x01000
6566 #define PCIE_SHARED_PENDING_BRPT	0x02000
66
-#define PCIE_SHARED_TXPUSH_SPRT		0x04000
67
+/* BCMPCIE_SUPPORT_TX_PUSH_RING		0x04000 obsolete */
6768 #define PCIE_SHARED_EVT_SEQNUM		0x08000
6869 #define PCIE_SHARED_DMA_INDEX		0x10000
6970 
....@@ -82,9 +83,95 @@
8283 #define PCIE_SHARED_IDLE_FLOW_RING		0x80000
8384 #define PCIE_SHARED_2BYTE_INDICES       0x100000
8485 
86
+#define PCIE_SHARED2_EXTENDED_TRAP_DATA	0x00000001	/* using flags2 in shared area */
87
+#define PCIE_SHARED2_TXSTATUS_METADATA	0x00000002
88
+#define PCIE_SHARED2_BT_LOGGING		0x00000004	/* BT logging support */
89
+#define PCIE_SHARED2_SNAPSHOT_UPLOAD	0x00000008	/* BT/WLAN snapshot upload support */
90
+#define PCIE_SHARED2_SUBMIT_COUNT_WAR	0x00000010	/* submission count WAR */
91
+#define PCIE_SHARED2_FW_SMALL_MEMDUMP	0x00000200      /* FW small memdump */
92
+#define PCIE_SHARED2_DEBUG_BUF_DEST	0x00002000	/* debug buf dest support */
93
+#define PCIE_SHARED_FAST_DELETE_RING	0x00000020      /* Fast Delete Ring */
94
+#define PCIE_SHARED_EVENT_BUF_POOL_MAX	0x000000c0      /* event buffer pool max bits */
95
+#define PCIE_SHARED_EVENT_BUF_POOL_MAX_POS     6       /* event buffer pool max bit position */
96
+
97
+/* dongle supports fatal buf log collection */
98
+#define PCIE_SHARED_FATAL_LOGBUG_VALID	0x200000
99
+
100
+/* Implicit DMA with corerev 19 and after */
101
+#define PCIE_SHARED_IDMA		0x400000
102
+
103
+/* MSI support */
104
+#define PCIE_SHARED_D2H_MSI_MULTI_MSG   0x800000
105
+
106
+/* IFRM with corerev 19 and after */
107
+#define PCIE_SHARED_IFRM		0x1000000
108
+
109
+/**
110
+ * From Rev6 and above, suspend/resume can be done using two handshake methods.
111
+ * 1. Using ctrl post/ctrl cmpl messages (Default rev6)
112
+ * 2. Using Mailbox data (old method as used in rev5)
113
+ * This shared flag indicates whether to overide rev6 default method and use mailbox for
114
+ * suspend/resume.
115
+ */
116
+#define PCIE_SHARED_USE_MAILBOX		0x2000000
117
+
118
+/* Firmware compiled for mfgbuild purposes */
119
+#define PCIE_SHARED_MFGBUILD_FW		0x4000000
120
+
121
+/* Firmware could use DB0 value as host timestamp */
122
+#define PCIE_SHARED_TIMESTAMP_DB0	0x8000000
123
+/* Firmware could use Hostready (IPC rev7) */
124
+#define PCIE_SHARED_HOSTRDY_SUPPORT	0x10000000
125
+
126
+/* When set, Firmwar does not support OOB Device Wake based DS protocol */
127
+#define PCIE_SHARED_NO_OOB_DW		0x20000000
128
+
129
+/* When set, Firmwar supports Inband DS protocol */
130
+#define PCIE_SHARED_INBAND_DS		0x40000000
131
+
132
+/* use DAR registers */
133
+#define PCIE_SHARED_DAR			0x80000000
134
+
135
+/**
136
+ * Following are the shared2 flags. All bits in flags have been used. A flags2
137
+ * field got added and the definition for these flags come here:
138
+ */
139
+/* WAR: D11 txstatus through unused status field of PCIe completion header */
140
+#define PCIE_SHARED2_D2H_D11_TX_STATUS	0x40000000
141
+#define PCIE_SHARED2_H2D_D11_TX_STATUS	0x80000000
142
+
143
+#define PCIE_SHARED2_EXTENDED_TRAP_DATA	0x00000001
144
+
145
+#define PCIE_SHARED2_TXSTATUS_METADATA	0x00000002
146
+
147
+/* BT logging support */
148
+#define PCIE_SHARED2_BT_LOGGING		0x00000004
149
+/* BT/WLAN snapshot upload support */
150
+#define PCIE_SHARED2_SNAPSHOT_UPLOAD	0x00000008
151
+/* submission count WAR */
152
+#define PCIE_SHARED2_SUBMIT_COUNT_WAR	0x00000010
153
+
154
+/* Fast Delete ring support */
155
+#define PCIE_SHARED2_FAST_DELETE_RING	0x00000020
156
+
157
+/* Host SCB support */
158
+#define PCIE_SHARED2_HSCB		0x00000800
85159 
86160 #define PCIE_SHARED_D2H_MAGIC		0xFEDCBA09
87161 #define PCIE_SHARED_H2D_MAGIC		0x12345678
162
+
163
+#define PCIE_SHARED2_PKT_TX_STATUS	0x00000100		/* using flags2 to indicate
164
+							   firmware support added to reuse
165
+							   timesync to update PKT txstatus
166
+							   */
167
+/* Support Enhanced Debug Lane */
168
+#define PCIE_SHARED2_EDL_RING		0x00001000
169
+
170
+/* Timestamp in packet */
171
+#define PCIE_SHARED2_PKT_TIMESTAMP	0x00008000
172
+
173
+/* HP2P feature */
174
+#define PCIE_SHARED2_HP2P		0x00010000u
88175 
89176 /**
90177  * Message rings convey messages between host and device. They are unidirectional, and are located
....@@ -105,6 +192,24 @@
105192 
106193 #define BCMPCIE_H2D_MSGRINGS(max_tx_flows) \
107194 	(BCMPCIE_H2D_COMMON_MSGRINGS + (max_tx_flows))
195
+
196
+/* different ring types */
197
+#define BCMPCIE_H2D_RING_TYPE_CTRL_SUBMIT		0x1
198
+#define BCMPCIE_H2D_RING_TYPE_TXFLOW_RING		0x2
199
+#define BCMPCIE_H2D_RING_TYPE_RXBUFPOST			0x3
200
+#define BCMPCIE_H2D_RING_TYPE_TXSUBMIT			0x4
201
+#define BCMPCIE_H2D_RING_TYPE_DBGBUF_SUBMIT		0x5
202
+#define BCMPCIE_H2D_RING_TYPE_BTLOG_SUBMIT		0x6
203
+
204
+#define BCMPCIE_D2H_RING_TYPE_CTRL_CPL			0x1
205
+#define BCMPCIE_D2H_RING_TYPE_TX_CPL			0x2
206
+#define BCMPCIE_D2H_RING_TYPE_RX_CPL			0x3
207
+#define BCMPCIE_D2H_RING_TYPE_DBGBUF_CPL		0x4
208
+#define BCMPCIE_D2H_RING_TYPE_AC_RX_COMPLETE		0x5
209
+#define BCMPCIE_D2H_RING_TYPE_BTLOG_CPL		0x6
210
+#define BCMPCIE_D2H_RING_TYPE_EDL                       0x7
211
+#define BCMPCIE_D2H_RING_TYPE_HPP_TX_CPL		0x8
212
+#define BCMPCIE_D2H_RING_TYPE_HPP_RX_CPL		0x9
108213 
109214 /**
110215  * H2D and D2H, WR and RD index, are maintained in the following arrays:
....@@ -187,9 +292,8 @@
187292 	sh_addr_t	base_addr; /* 64 bits address, either in host or device memory */
188293 } ring_mem_t;
189294 
190
-
191295 /**
192
- * Per flow ring, information is maintained in device memory, e.g. at what address the ringmem and
296
+ * Per flow ring, information is maintained in device memory, eg at what address the ringmem and
193297  * ringstate are located. The flow ring itself can be instantiated in either host or device memory.
194298  *
195299  * Perhaps this type should be renamed to make clear that it resides in device memory only.
....@@ -217,8 +321,12 @@
217321 	sh_addr_t	d2h_w_idx_hostaddr; /* Array of all D2H ring's WR indices */
218322 	sh_addr_t	d2h_r_idx_hostaddr; /* Array of all D2H ring's RD indices */
219323 
220
-	uint16		max_sub_queues; /* maximum number of H2D rings: common + flow */
221
-	uint16		rsvd;
324
+	uint16		max_tx_flowrings; /* maximum number of H2D rings: common + flow */
325
+	uint16		max_submission_queues; /* maximum number of H2D rings: common + flow */
326
+	uint16		max_completion_rings; /* maximum number of H2D rings: common + flow */
327
+	uint16		max_vdevs; /* max number of virtual interfaces supported */
328
+
329
+	sh_addr_t	ifrm_w_idx_hostaddr; /* Array of all H2D ring's WR indices for IFRM */
222330 } ring_info_t;
223331 
224332 /**
....@@ -257,15 +365,74 @@
257365 	uint32		host_dma_scratch_buffer_len;
258366 	sh_addr_t	host_dma_scratch_buffer;
259367 
260
-	/** block of host memory for the dongle to push the status into */
261
-	uint32		device_rings_stsblk_len;
262
-	sh_addr_t	device_rings_stsblk;
368
+	/* location in host memory for scb host offload structures */
369
+	sh_addr_t	host_scb_addr;
370
+	uint32		host_scb_size;
263371 
264
-	uint32	buzzz;	/* BUZZZ state format strings and trace buffer */
372
+	/* anonymous union for overloading fields in structure */
373
+	union {
374
+		uint32	buzz_dbg_ptr;	/* BUZZZ state format strings and trace buffer */
375
+		struct {
376
+			/* Host provided trap buffer length in words */
377
+			uint16	device_trap_debug_buffer_len;
378
+			uint16	rsvd2;
379
+		};
380
+	};
265381 
382
+	/* rev6 compatible changes */
383
+	uint32          flags2;
384
+	uint32          host_cap;
385
+
386
+	/* location in the host address space to write trap indication.
387
+	* At this point for the current rev of the spec, firmware will
388
+	* support only indications to 32 bit host addresses.
389
+	* This essentially is device_trap_debug_buffer_addr
390
+	*/
391
+	sh_addr_t       host_trap_addr;
392
+
393
+	/* location for host fatal error log buffer start address */
394
+	uint32		device_fatal_logbuf_start;
395
+
396
+	/* location in host memory for offloaded modules */
397
+	sh_addr_t	hoffload_addr;
398
+	uint32	debug_info_addr;	/* Address of debug_info area */
266399 } pciedev_shared_t;
267400 
268
-extern pciedev_shared_t pciedev_shared;
401
+/* Device F/W provides the following access function:
402
+ * pciedev_shared_t *hnd_get_pciedev_shared(void);
403
+ */
404
+
405
+/* host capabilities */
406
+#define HOSTCAP_PCIEAPI_VERSION_MASK		0x000000FF
407
+#define HOSTCAP_H2D_VALID_PHASE			0x00000100
408
+#define HOSTCAP_H2D_ENABLE_TRAP_ON_BADPHASE	0x00000200
409
+#define HOSTCAP_H2D_ENABLE_HOSTRDY		0x00000400
410
+#define HOSTCAP_DB0_TIMESTAMP			0x00000800
411
+#define HOSTCAP_DS_NO_OOB_DW			0x00001000
412
+#define HOSTCAP_DS_INBAND_DW			0x00002000
413
+#define HOSTCAP_H2D_IDMA			0x00004000
414
+#define HOSTCAP_H2D_IFRM			0x00008000
415
+#define HOSTCAP_H2D_DAR				0x00010000
416
+#define HOSTCAP_EXTENDED_TRAP_DATA		0x00020000
417
+#define HOSTCAP_TXSTATUS_METADATA		0x00040000
418
+#define HOSTCAP_BT_LOGGING			0x00080000
419
+#define HOSTCAP_SNAPSHOT_UPLOAD			0x00100000
420
+#define HOSTCAP_FAST_DELETE_RING		0x00200000
421
+#define HOSTCAP_PKT_TXSTATUS			0x00400000
422
+#define HOSTCAP_UR_FW_NO_TRAP			0x00800000 /* Don't trap on UR */
423
+#define HOSTCAP_HSCB				0x02000000
424
+/* Host support for extended device trap debug buffer */
425
+#define HOSTCAP_EXT_TRAP_DBGBUF			0x04000000
426
+/* Host support for enhanced debug lane */
427
+#define HOSTCAP_EDL_RING			0x10000000
428
+#define HOSTCAP_PKT_TIMESTAMP			0x20000000
429
+#define HOSTCAP_PKT_HP2P			0x40000000
430
+
431
+/* extended trap debug buffer allocation sizes. Note that this buffer can be used for
432
+ * other trap related purposes also.
433
+ */
434
+#define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN_MIN	(64u * 1024u)
435
+#define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN_MAX	(256u * 1024u)
269436 
270437 /**
271438  * Mailboxes notify a remote party that an event took place, using interrupts. They use hardware
....@@ -273,47 +440,96 @@
273440  */
274441 
275442 /* H2D mail box Data */
276
-#define H2D_HOST_D3_INFORM	0x00000001
443
+#define H2D_HOST_D3_INFORM		0x00000001
277444 #define H2D_HOST_DS_ACK		0x00000002
278445 #define H2D_HOST_DS_NAK		0x00000004
446
+#define H2D_HOST_D0_INFORM_IN_USE	0x00000008
447
+#define H2D_HOST_D0_INFORM		0x00000010
448
+#define H2DMB_DS_ACTIVE			0x00000020
449
+#define H2DMB_DS_DEVICE_WAKE	0x00000040
450
+#define H2D_HOST_IDMA_INITED	0x00000080
451
+#define H2D_HOST_ACK_NOINT		0x00010000 /* d2h_ack interrupt ignore */
279452 #define H2D_HOST_CONS_INT	0x80000000	/**< h2d int for console cmds  */
280453 #define H2D_FW_TRAP		0x20000000	/**< h2d force TRAP */
281
-#define H2D_HOST_D0_INFORM_IN_USE	0x00000008
282
-#define H2D_HOST_D0_INFORM	0x00000010
454
+#define H2DMB_DS_HOST_SLEEP_INFORM H2D_HOST_D3_INFORM
455
+#define H2DMB_DS_DEVICE_SLEEP_ACK  H2D_HOST_DS_ACK
456
+#define H2DMB_DS_DEVICE_SLEEP_NAK  H2D_HOST_DS_NAK
457
+#define H2DMB_D0_INFORM_IN_USE     H2D_HOST_D0_INFORM_IN_USE
458
+#define H2DMB_D0_INFORM            H2D_HOST_D0_INFORM
459
+#define H2DMB_FW_TRAP              H2D_FW_TRAP
460
+#define H2DMB_HOST_CONS_INT        H2D_HOST_CONS_INT
461
+#define H2DMB_DS_DEVICE_WAKE_ASSERT		H2DMB_DS_DEVICE_WAKE
462
+#define H2DMB_DS_DEVICE_WAKE_DEASSERT	H2DMB_DS_ACTIVE
283463 
284464 /* D2H mail box Data */
285
-#define D2H_DEV_D3_ACK		0x00000001
286
-#define D2H_DEV_DS_ENTER_REQ	0x00000002
287
-#define D2H_DEV_DS_EXIT_NOTE	0x00000004
288
-#define D2H_DEV_FWHALT		0x10000000
465
+#define D2H_DEV_D3_ACK					0x00000001
466
+#define D2H_DEV_DS_ENTER_REQ			0x00000002
467
+#define D2H_DEV_DS_EXIT_NOTE			0x00000004
468
+#define D2HMB_DS_HOST_SLEEP_EXIT_ACK	0x00000008
469
+#define D2H_DEV_IDMA_INITED				0x00000010
470
+#define D2H_DEV_FWHALT					0x10000000
471
+#define D2H_DEV_TRAP_PING_HOST_FAILURE  0x08000000
472
+#define D2H_DEV_EXT_TRAP_DATA			0x20000000
473
+#define D2H_DEV_TRAP_IN_TRAP			0x40000000
474
+#define D2H_DEV_TRAP_DUE_TO_BT			0x01000000
475
+/* Indicates trap due to HMAP violation */
476
+#define D2H_DEV_TRAP_DUE_TO_HMAP		0x02000000
477
+/* Indicates whether HMAP violation was Write */
478
+#define D2H_DEV_TRAP_HMAP_WRITE			0x04000000
479
+
480
+#define D2HMB_DS_HOST_SLEEP_ACK         D2H_DEV_D3_ACK
481
+#define D2HMB_DS_DEVICE_SLEEP_ENTER_REQ D2H_DEV_DS_ENTER_REQ
482
+#define D2HMB_DS_DEVICE_SLEEP_EXIT      D2H_DEV_DS_EXIT_NOTE
483
+#define D2HMB_FWHALT                    D2H_DEV_FWHALT
484
+#define D2HMB_TRAP_IN_TRAP              D2H_DEV_TRAP_IN_TRAP
485
+#define D2HMB_EXT_TRAP_DATA             D2H_DEV_EXT_TRAP_DATA
486
+#define D2H_FWTRAP_MASK		0x0000001F	/* Adding maskbits for TRAP information */
289487 #define D2H_DEV_MB_MASK		(D2H_DEV_D3_ACK | D2H_DEV_DS_ENTER_REQ | \
290
-				D2H_DEV_DS_EXIT_NOTE | D2H_DEV_FWHALT)
488
+				D2H_DEV_DS_EXIT_NOTE | D2H_DEV_IDMA_INITED | D2H_DEV_FWHALT | \
489
+				D2H_FWTRAP_MASK | D2H_DEV_EXT_TRAP_DATA | D2H_DEV_TRAP_IN_TRAP)
291490 #define D2H_DEV_MB_INVALIDATED(x)	((!x) || (x & ~D2H_DEV_MB_MASK))
292491 
492
+/* Size of Extended Trap data Buffer */
493
+#define BCMPCIE_EXT_TRAP_DATA_MAXLEN  4096
494
+
293495 /** These macro's operate on type 'inuse_lclbuf_pool_t' and are used by firmware only */
496
+#define PREVTXP(i, d)           (((i) == 0) ? ((d) - 1) : ((i) - 1))
294497 #define NEXTTXP(i, d)           ((((i)+1) >= (d)) ? 0 : ((i)+1))
498
+#define NEXTNTXP(i, n, d)       ((((i)+(n)) >= (d)) ? 0 : ((i)+(n)))
295499 #define NTXPACTIVE(r, w, d)     (((r) <= (w)) ? ((w)-(r)) : ((d)-(r)+(w)))
296500 #define NTXPAVAIL(r, w, d)      (((d) - NTXPACTIVE((r), (w), (d))) > 1)
297501 
298502 /* Function can be used to notify host of FW halt */
299
-#define READ_AVAIL_SPACE(w, r, d)		\
300
-			((w >= r) ? (w - r) : (d - r))
503
+#define READ_AVAIL_SPACE(w, r, d) ((w >= r) ? (uint32)(w - r) : (uint32)(d - r))
504
+#define WRITE_SPACE_AVAIL_CONTINUOUS(r, w, d) ((w >= r) ? (d - w) : (r - w))
505
+#define WRITE_SPACE_AVAIL(r, w, d) (d - (NTXPACTIVE(r, w, d)) - 1)
506
+#define CHECK_WRITE_SPACE(r, w, d) ((r) > (w)) ? \
507
+	(uint32)((r) - (w) - 1) : ((r) == 0 || (w) == 0) ? \
508
+	(uint32)((d) - (w) - 1) : (uint32)((d) - (w))
301509 
302
-#define WRITE_SPACE_AVAIL_CONTINUOUS(r, w, d)		((w >= r) ? (d - w) : (r - w))
303
-#define WRITE_SPACE_AVAIL(r, w, d)	(d - (NTXPACTIVE(r, w, d)) - 1)
304
-#define CHECK_WRITE_SPACE(r, w, d)	\
305
-		MIN(WRITE_SPACE_AVAIL(r, w, d), WRITE_SPACE_AVAIL_CONTINUOUS(r, w, d))
306
-
510
+#define CHECK_NOWRITE_SPACE(r, w, d) \
511
+	(((uint32)(r) == (uint32)((w) + 1)) || (((r) == 0) && ((w) == ((d) - 1))))
307512 
308513 #define WRT_PEND(x)	((x)->wr_pending)
309
-#define DNGL_RING_WPTR(msgbuf)		(*((msgbuf)->tcm_rs_w_ptr))
514
+#define DNGL_RING_WPTR(msgbuf)		(*((msgbuf)->tcm_rs_w_ptr)) /**< advanced by producer */
310515 #define BCMMSGBUF_RING_SET_W_PTR(msgbuf, a)	(DNGL_RING_WPTR(msgbuf) = (a))
311516 
312
-#define DNGL_RING_RPTR(msgbuf)		(*((msgbuf)->tcm_rs_r_ptr))
517
+#define DNGL_RING_RPTR(msgbuf)		(*((msgbuf)->tcm_rs_r_ptr)) /**< advanced by consumer */
313518 #define BCMMSGBUF_RING_SET_R_PTR(msgbuf, a)	(DNGL_RING_RPTR(msgbuf) = (a))
314519 
315
-#define RING_START_PTR(x)	((x)->ringmem->base_addr.low_addr)
316
-#define RING_MAX_ITEM(x)	((x)->ringmem->max_item)
317
-#define RING_LEN_ITEMS(x)	((x)->ringmem->len_items)
520
+#define MODULO_RING_IDX(x, y)	((x) % (y)->bitmap_size)
521
+
522
+#define  RING_READ_PTR(x)	((x)->ringstate->r_offset)
523
+#define  RING_WRITE_PTR(x)	((x)->ringstate->w_offset)
524
+#define  RING_START_PTR(x)	((x)->ringmem->base_addr.low_addr)
525
+#define  RING_MAX_ITEM(x)	((x)->ringmem->max_item)
526
+#define  RING_LEN_ITEMS(x)	((x)->ringmem->len_items)
527
+#define	 HOST_RING_BASE(x)	((x)->dma_buf.va)
528
+#define	 HOST_RING_END(x)	((uint8 *)HOST_RING_BASE((x)) + \
529
+					((RING_MAX_ITEM((x))-1)*RING_LEN_ITEMS((x))))
530
+
531
+/* Trap types copied in the pciedev_shared.trap_addr */
532
+#define	FW_INITIATED_TRAP_TYPE	(0x1 << 7)
533
+#define	HEALTHCHECK_NODS_TRAP_TYPE	(0x1 << 6)
318534 
319535 #endif	/* _bcmpcie_h_ */