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2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc 
 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/dhd_bus.h
....@@ -1,18 +1,19 @@
1
-/* SPDX-License-Identifier: GPL-2.0 */
21 /*
32  * Header file describing the internal (inter-module) DHD interfaces.
43  *
54  * Provides type definitions and function prototypes used to link the
65  * DHD OS, bus, and protocol modules.
76  *
8
- * Copyright (C) 1999-2019, Broadcom Corporation
9
- * 
7
+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
8
+ *
9
+ * Copyright (C) 1999-2017, Broadcom Corporation
10
+ *
1011  *      Unless you and Broadcom execute a separate written software license
1112  * agreement governing use of this software, this software is licensed to you
1213  * under the terms of the GNU General Public License version 2 (the "GPL"),
1314  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
1415  * following added to such license:
15
- * 
16
+ *
1617  *      As a special exception, the copyright holders of this software give you
1718  * permission to link this software with independent modules, and to copy and
1819  * distribute the resulting executable under terms of your choice, provided that
....@@ -20,7 +21,7 @@
2021  * the license of that module.  An independent module is a module which is not
2122  * derived from this software.  The special exception does not apply to any
2223  * modifications of the software.
23
- * 
24
+ *
2425  *      Notwithstanding the above, under no circumstances may you combine this
2526  * software in any way with any other Broadcom software provided under a license
2627  * other than the GPL, without Broadcom's express prior written consent.
....@@ -28,7 +29,7 @@
2829  *
2930  * <<Broadcom-WL-IPTag/Open:>>
3031  *
31
- * $Id: dhd_bus.h 603826 2015-12-03 08:57:00Z $
32
+ * $Id: dhd_bus.h 701741 2017-05-26 08:18:08Z $
3233  */
3334 
3435 #ifndef _dhd_bus_h_
....@@ -38,12 +39,18 @@
3839  * Exported from dhd bus module (dhd_usb, dhd_sdio)
3940  */
4041 
42
+/* global variable for the bus */
43
+extern struct dhd_bus *g_dhd_bus;
44
+
4145 /* Indicate (dis)interest in finding dongles. */
4246 extern int dhd_bus_register(void);
4347 extern void dhd_bus_unregister(void);
4448 
4549 /* Download firmware image and nvram image */
4650 extern int dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh, char *fw_path, char *nv_path);
51
+#if defined(BT_OVER_SDIO)
52
+extern int dhd_bus_download_btfw(struct dhd_bus *bus, osl_t *osh, char *btfw_path);
53
+#endif /* defined (BT_OVER_SDIO) */
4754 
4855 /* Stop bus module: clear pending frames, disable data flow */
4956 extern void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex);
....@@ -62,8 +69,11 @@
6269 extern int dhd_bus_txdata(struct dhd_bus *bus, void *txp, uint8 ifidx);
6370 #else
6471 extern int dhd_bus_txdata(struct dhd_bus *bus, void *txp);
65
-#endif
72
+#endif // endif
6673 
74
+#ifdef BCMPCIE
75
+extern void dhdpcie_cto_recovery_handler(dhd_pub_t *dhd);
76
+#endif /* BCMPCIE */
6777 
6878 /* Send/receive a control message to/from the dongle.
6979  * Expects caller to enforce a single outstanding transaction.
....@@ -81,15 +91,12 @@
8191 extern void dhd_bus_dev_pm_relax(dhd_pub_t *dhdpub);
8292 extern bool dhd_bus_dev_pm_enabled(dhd_pub_t *dhdpub);
8393 
84
-#if defined(DHD_DEBUG)
8594 /* Device console input function */
8695 extern int dhd_bus_console_in(dhd_pub_t *dhd, uchar *msg, uint msglen);
87
-#endif /* defined(DHD_DEBUG) */
8896 
8997 /* Deferred processing for the bus, return TRUE requests reschedule */
9098 extern bool dhd_bus_dpc(struct dhd_bus *bus);
9199 extern void dhd_bus_isr(bool * InterruptRecognized, bool * QueueMiniportHandleInterrupt, void *arg);
92
-
93100 
94101 /* Check for and handle local prot-specific iovar commands */
95102 extern int dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
....@@ -120,7 +127,7 @@
120127 extern uint8 dhd_bus_is_ioready(struct dhd_bus *bus);
121128 #else
122129 #define dhd_bus_set_dotxinrx(a, b) do {} while (0)
123
-#endif
130
+#endif // endif
124131 
125132 #define DHD_SET_BUS_STATE_DOWN(_bus)  do { \
126133 	(_bus)->dhd->busstate = DHD_BUS_DOWN; \
....@@ -132,6 +139,14 @@
132139 extern void dhd_txglom_enable(dhd_pub_t *dhdp, bool enable);
133140 extern int dhd_bus_get_ids(struct dhd_bus *bus, uint32 *bus_type, uint32 *bus_num,
134141 	uint32 *slot_num);
142
+
143
+#if defined(DHD_FW_COREDUMP) && (defined(BCMPCIE) || defined(BCMSDIO))
144
+extern int dhd_bus_mem_dump(dhd_pub_t *dhd);
145
+extern int dhd_bus_get_mem_dump(dhd_pub_t *dhdp);
146
+#else
147
+#define dhd_bus_mem_dump(x)
148
+#define dhd_bus_get_mem_dump(x)
149
+#endif /* DHD_FW_COREDUMP && (BCMPCIE || BCMSDIO) */
135150 
136151 #ifdef BCMPCIE
137152 enum {
....@@ -151,6 +166,10 @@
151166 	D2H_DMA_INDX_WR_UPD, /* update D2H WR index in D2H WR dma indices buf */
152167 	D2H_DMA_INDX_RD_UPD, /* update D2H RD index in D2H RD dma indices buf */
153168 
169
+	/* DHD Indices array buffers and update for: H2D flow ring WR */
170
+	H2D_IFRM_INDX_WR_BUF, /* update H2D WR dma indices buf base addr to dongle */
171
+	H2D_IFRM_INDX_WR_UPD, /* update H2D WR dma indices buf base addr to dongle */
172
+
154173 	/* H2D and D2H Mailbox data update */
155174 	H2D_MB_DATA,
156175 	D2H_MB_DATA,
....@@ -165,20 +184,25 @@
165184 	RING_WR_UPD,         /* update ring write index from/to dongle */
166185 
167186 	TOTAL_LFRAG_PACKET_CNT,
168
-	MAX_HOST_RXBUFS
187
+	MAX_HOST_RXBUFS,
188
+	HOST_API_VERSION,
189
+	DNGL_TO_HOST_TRAP_ADDR,
190
+	HOST_SCB_ADDR,		/* update host scb base address to dongle */
169191 };
170192 
171193 typedef void (*dhd_mb_ring_t) (struct dhd_bus *, uint32);
194
+typedef void (*dhd_mb_ring_2_t) (struct dhd_bus *, uint32, bool);
172195 extern void dhd_bus_cmn_writeshared(struct dhd_bus *bus, void * data, uint32 len, uint8 type,
173196 	uint16 ringid);
174197 extern void dhd_bus_ringbell(struct dhd_bus *bus, uint32 value);
198
+extern void dhd_bus_ringbell_2(struct dhd_bus *bus, uint32 value, bool devwake);
175199 extern void dhd_bus_cmn_readshared(struct dhd_bus *bus, void* data, uint8 type, uint16 ringid);
176200 extern uint32 dhd_bus_get_sharedflags(struct dhd_bus *bus);
177201 extern void dhd_bus_rx_frame(struct dhd_bus *bus, void* pkt, int ifidx, uint pkt_count);
178202 extern void dhd_bus_start_queue(struct dhd_bus *bus);
179203 extern void dhd_bus_stop_queue(struct dhd_bus *bus);
180
-
181204 extern dhd_mb_ring_t dhd_bus_get_mbintr_fn(struct dhd_bus *bus);
205
+extern dhd_mb_ring_2_t dhd_bus_get_mbintr_2_fn(struct dhd_bus *bus);
182206 extern void dhd_bus_write_flow_ring_states(struct dhd_bus *bus,
183207 	void * data, uint16 flowid);
184208 extern void dhd_bus_read_flow_ring_states(struct dhd_bus *bus,
....@@ -193,6 +217,9 @@
193217 extern uint32 dhd_bus_max_h2d_queues(struct dhd_bus *bus);
194218 extern int dhd_bus_schedule_queue(struct dhd_bus *bus, uint16 flow_id, bool txs);
195219 
220
+#ifdef IDLE_TX_FLOW_MGMT
221
+extern void dhd_bus_flow_ring_resume_response(struct dhd_bus *bus, uint16 flowid, int32 status);
222
+#endif /* IDLE_TX_FLOW_MGMT */
196223 
197224 extern int dhdpcie_bus_clock_start(struct dhd_bus *bus);
198225 extern int dhdpcie_bus_clock_stop(struct dhd_bus *bus);
....@@ -203,21 +230,128 @@
203230 extern bool dhdpcie_bus_dongle_attach(struct dhd_bus *bus);
204231 extern int dhd_bus_release_dongle(struct dhd_bus *bus);
205232 extern int dhd_bus_request_irq(struct dhd_bus *bus);
233
+extern int dhdpcie_get_pcieirq(struct dhd_bus *bus, unsigned int *irq);
234
+extern void dhd_bus_aer_config(struct dhd_bus *bus);
206235 
236
+extern struct device * dhd_bus_to_dev(struct dhd_bus *bus);
237
+
238
+extern int dhdpcie_cto_init(struct dhd_bus *bus, bool enable);
239
+extern int dhdpcie_cto_cfg_init(struct dhd_bus *bus, bool enable);
240
+
241
+extern void dhdpcie_ssreset_dis_enum_rst(struct dhd_bus *bus);
207242 
208243 #ifdef DHD_FW_COREDUMP
209
-extern int dhd_bus_mem_dump(dhd_pub_t *dhd);
244
+#ifdef BCMDHDX
245
+extern int dhdx_dongle_mem_dump(void);
246
+#else
247
+extern int dhd_dongle_mem_dump(void);
248
+#endif /* BCMDHDX */
210249 #endif /* DHD_FW_COREDUMP */
211250 
251
+#ifdef IDLE_TX_FLOW_MGMT
252
+extern void dhd_bus_idle_tx_ring_suspend(dhd_pub_t *dhd, uint16 flow_ring_id);
253
+#endif /* IDLE_TX_FLOW_MGMT */
254
+extern void dhd_bus_handle_mb_data(struct dhd_bus *bus, uint32 d2h_mb_data);
212255 #endif /* BCMPCIE */
213256 
214
-#ifdef DHD_ULP
215
-extern int dhd_bcmsdh_send_buffer(void *bus, uint8 *frame, uint16 len);
216
-extern void dhd_bus_ulp_bus_wake(void *bus);
217
-extern void dhd_bus_ulp_disable_console(dhd_pub_t *dhdp);
218
-extern int dhd_bus_read_sdh_config(void *bus);
219
-extern void dhd_bus_schedule_dpc(void *bus);
257
+/* dump the device trap informtation  */
258
+extern void dhd_bus_dump_trap_info(struct dhd_bus *bus, struct bcmstrbuf *b);
259
+extern void dhd_bus_copy_trap_sig(struct dhd_bus *bus,  trap_t *tr);
260
+#ifdef WL_CFGVENDOR_SEND_HANG_EVENT
261
+void copy_ext_trap_sig(dhd_pub_t *dhd, trap_t *tr);
262
+void copy_hang_info_trap(dhd_pub_t *dhd);
263
+#endif /* WL_CFGVENDOR_SEND_HANG_EVENT */
264
+/* Function to set default min res mask */
220265 extern bool dhd_bus_set_default_min_res_mask(struct dhd_bus *bus);
266
+
267
+/* Function to reset PMU registers */
221268 extern void dhd_bus_pmu_reg_reset(dhd_pub_t *dhdp);
269
+
270
+extern void dhd_bus_ucode_download(struct dhd_bus *bus);
271
+
272
+#ifdef DHD_ULP
273
+extern void dhd_bus_ulp_disable_console(dhd_pub_t *dhdp);
222274 #endif /* DHD_ULP */
275
+extern int dhd_bus_readwrite_bp_addr(dhd_pub_t *dhdp, uint addr, uint size, uint* data, bool read);
276
+extern int dhd_get_idletime(dhd_pub_t *dhd);
277
+#ifdef BCMPCIE
278
+extern void dhd_bus_dump_console_buffer(struct dhd_bus *bus);
279
+extern void dhd_bus_intr_count_dump(dhd_pub_t *dhdp);
280
+extern void dhd_bus_set_dpc_sched_time(dhd_pub_t *dhdp);
281
+extern bool dhd_bus_query_dpc_sched_errors(dhd_pub_t *dhdp);
282
+extern int dhd_bus_dmaxfer_lpbk(dhd_pub_t *dhdp, uint32 type);
283
+#ifndef BCMDHDX
284
+extern bool dhd_bus_check_driver_up(void);
285
+#else
286
+extern bool dhdx_bus_check_driver_up(void);
287
+#endif /* BCMDHDX */
288
+extern int dhd_bus_get_cto(dhd_pub_t *dhdp);
289
+extern void dhd_bus_set_linkdown(dhd_pub_t *dhdp, bool val);
290
+extern int dhd_bus_get_linkdown(dhd_pub_t *dhdp);
291
+#else
292
+#define dhd_bus_dump_console_buffer(x)
293
+static INLINE void dhd_bus_intr_count_dump(dhd_pub_t *dhdp) { UNUSED_PARAMETER(dhdp); }
294
+static INLINE void dhd_bus_set_dpc_sched_time(dhd_pub_t *dhdp) { }
295
+static INLINE bool dhd_bus_query_dpc_sched_errors(dhd_pub_t *dhdp) { return 0; }
296
+static INLINE int dhd_bus_dmaxfer_lpbk(dhd_pub_t *dhdp, uint32 type) { return 0; }
297
+static INLINE bool dhd_bus_check_driver_up(void) { return FALSE; }
298
+extern INLINE void dhd_bus_set_linkdown(dhd_pub_t *dhdp, bool val) { }
299
+extern INLINE int dhd_bus_get_linkdown(dhd_pub_t *dhdp) { return 0; }
300
+static INLINE int dhd_bus_get_cto(dhd_pub_t *dhdp) { return 0; }
301
+#endif /* BCMPCIE */
302
+
303
+#if defined(BCMPCIE) && defined(EWP_ETD_PRSRV_LOGS)
304
+void dhdpcie_get_etd_preserve_logs(dhd_pub_t *dhd, uint8 *ext_trap_data,
305
+		void *event_decode_data);
306
+#endif // endif
307
+
308
+extern uint16 dhd_get_chipid(dhd_pub_t *dhd);
309
+
310
+#ifdef DHD_WAKE_STATUS
311
+extern wake_counts_t* dhd_bus_get_wakecount(dhd_pub_t *dhd);
312
+extern int dhd_bus_get_bus_wake(dhd_pub_t * dhd);
313
+#endif /* DHD_WAKE_STATUS */
314
+
315
+#ifdef BT_OVER_SDIO
316
+/*
317
+ * SDIO layer clock control functions exposed to be called from other layers.
318
+ * This is required especially in the case where the BUS is shared between
319
+ * BT and SDIO and we have to control the clock. The callers of this function
320
+ * are expected to hold the sdlock
321
+ */
322
+int __dhdsdio_clk_enable(struct dhd_bus *bus, bus_owner_t owner, int can_wait);
323
+int __dhdsdio_clk_disable(struct dhd_bus *bus, bus_owner_t owner, int can_wait);
324
+void dhdsdio_reset_bt_use_count(struct dhd_bus *bus);
325
+#endif /* BT_OVER_SDIO */
326
+
327
+int dhd_bus_perform_flr(struct dhd_bus *bus, bool force_fail);
328
+extern bool dhd_bus_get_flr_force_fail(struct dhd_bus *bus);
329
+
330
+extern bool dhd_bus_aspm_enable_rc_ep(struct dhd_bus *bus, bool enable);
331
+extern void dhd_bus_l1ss_enable_rc_ep(struct dhd_bus *bus, bool enable);
332
+
333
+bool dhd_bus_is_multibp_capable(struct dhd_bus *bus);
334
+
335
+#ifdef BCMPCIE
336
+extern void dhdpcie_advertise_bus_cleanup(dhd_pub_t  *dhdp);
337
+extern void dhd_msgbuf_iovar_timeout_dump(dhd_pub_t *dhd);
338
+#endif /* BCMPCIE */
339
+
340
+extern bool dhd_bus_force_bt_quiesce_enabled(struct dhd_bus *bus);
341
+
342
+#ifdef DHD_SSSR_DUMP
343
+extern int dhd_bus_fis_trigger(dhd_pub_t *dhd);
344
+extern int dhd_bus_fis_dump(dhd_pub_t *dhd);
345
+#endif /* DHD_SSSR_DUMP */
346
+
347
+#ifdef PCIE_FULL_DONGLE
348
+extern int dhdpcie_set_dma_ring_indices(dhd_pub_t *dhd, int32 int_val);
349
+#endif /* PCIE_FULL_DONGLE */
350
+
351
+#ifdef DHD_USE_BP_RESET
352
+extern int dhd_bus_perform_bp_reset(struct dhd_bus *bus);
353
+#endif /* DHD_USE_BP_RESET */
354
+
355
+extern void dhd_bwm_bt_quiesce(struct dhd_bus *bus);
356
+extern void dhd_bwm_bt_resume(struct dhd_bus *bus);
223357 #endif /* _dhd_bus_h_ */