forked from ~ljy/RK356X_SDK_RELEASE
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2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc 
 kernel/drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c
....@@ -1,27 +1,5 @@
1
-/******************************************************************************
2
- *
3
- * Copyright(c) 2009-2014  Realtek Corporation.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of version 2 of the GNU General Public License as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
14
- * The full GNU General Public License is included in this distribution in the
15
- * file called LICENSE.
16
- *
17
- * Contact Information:
18
- * wlanfae <wlanfae@realtek.com>
19
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20
- * Hsinchu 300, Taiwan.
21
- *
22
- * Larry Finger <Larry.Finger@lwfinger.net>
23
- *
24
- *****************************************************************************/
1
+// SPDX-License-Identifier: GPL-2.0
2
+/* Copyright(c) 2009-2014  Realtek Corporation.*/
253 
264 #include "../wifi.h"
275 #include "../pci.h"
....@@ -55,23 +33,22 @@
5533 {
5634 	struct rtl_priv *rtlpriv = rtl_priv(hw);
5735 	u32 original_value, readback_value, bitshift;
58
-	unsigned long flags;
5936 
60
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
61
-		 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
62
-		  regaddr, rfpath, bitmask);
37
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
38
+		"regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
39
+		regaddr, rfpath, bitmask);
6340 
64
-	spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
41
+	spin_lock(&rtlpriv->locks.rf_lock);
6542 
6643 	original_value = rtl8723_phy_rf_serial_read(hw, rfpath, regaddr);
6744 	bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
6845 	readback_value = (original_value & bitmask) >> bitshift;
6946 
70
-	spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
47
+	spin_unlock(&rtlpriv->locks.rf_lock);
7148 
72
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
73
-		 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
74
-		 regaddr, rfpath, bitmask, original_value);
49
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
50
+		"regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
51
+		regaddr, rfpath, bitmask, original_value);
7552 
7653 	return readback_value;
7754 }
....@@ -81,13 +58,12 @@
8158 {
8259 	struct rtl_priv *rtlpriv = rtl_priv(hw);
8360 	u32 original_value, bitshift;
84
-	unsigned long flags;
8561 
86
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
87
-		 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
88
-		  regaddr, bitmask, data, path);
62
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
63
+		"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
64
+		regaddr, bitmask, data, path);
8965 
90
-	spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
66
+	spin_lock(&rtlpriv->locks.rf_lock);
9167 
9268 	if (bitmask != RFREG_OFFSET_MASK) {
9369 			original_value = rtl8723_phy_rf_serial_read(hw, path,
....@@ -99,11 +75,11 @@
9975 
10076 	rtl8723_phy_rf_serial_write(hw, path, regaddr, data);
10177 
102
-	spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
78
+	spin_unlock(&rtlpriv->locks.rf_lock);
10379 
104
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
105
-		 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
106
-		  regaddr, bitmask, data, path);
80
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
81
+		"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
82
+		regaddr, bitmask, data, path);
10783 
10884 }
10985 
....@@ -182,18 +158,18 @@
182158 		      rtlhal->type_alna << 16 |
183159 		      rtlhal->type_apa  << 24;
184160 
185
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
186
-		 "===> [8812A] CheckPositive (cond1, cond2) = (0x%X 0x%X)\n",
187
-		 cond1, cond2);
188
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
189
-		 "===> [8812A] CheckPositive (driver1, driver2) = (0x%X 0x%X)\n",
190
-		 driver1, driver2);
161
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
162
+		"===> [8812A] CheckPositive (cond1, cond2) = (0x%X 0x%X)\n",
163
+		cond1, cond2);
164
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
165
+		"===> [8812A] CheckPositive (driver1, driver2) = (0x%X 0x%X)\n",
166
+		driver1, driver2);
191167 
192
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
193
-		 "	(Platform, Interface) = (0x%X, 0x%X)\n", 0x04, intf);
194
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
195
-		 "	(Board, Package) = (0x%X, 0x%X)\n",
196
-		 rtlhal->board_type, rtlhal->package_type);
168
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
169
+		"(Platform, Interface) = (0x%X, 0x%X)\n", 0x04, intf);
170
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
171
+		"(Board, Package) = (0x%X, 0x%X)\n",
172
+		rtlhal->board_type, rtlhal->package_type);
197173 
198174 	/*============== Value Defined Check ===============*/
199175 	/*QFN Type [15:12] and Cut Version [27:24] need to do value check*/
....@@ -307,9 +283,9 @@
307283 	struct rtl_phy *rtlphy = &rtlpriv->phy;
308284 
309285 	if (path > RF90_PATH_D) {
310
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
311
-			 "Invalid Rf Path %d in phy_SetTxPowerByRatBase()\n",
312
-			  path);
286
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
287
+			"Invalid Rf Path %d in phy_SetTxPowerByRatBase()\n",
288
+			path);
313289 		return;
314290 	}
315291 
....@@ -328,15 +304,15 @@
328304 			rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value;
329305 			break;
330306 		default:
331
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
332
-				 "Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n",
333
-				 rate_section, path, txnum);
307
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
308
+				"Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_SetTxPowerByRateBase()\n",
309
+				rate_section, path, txnum);
334310 			break;
335
-		};
311
+		}
336312 	} else {
337
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
338
-			 "Invalid Band %d in PHY_SetTxPowerByRateBase()\n",
339
-			 band);
313
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
314
+			"Invalid Band %d in PHY_SetTxPowerByRateBase()\n",
315
+			band);
340316 	}
341317 
342318 }
....@@ -349,9 +325,9 @@
349325 	struct rtl_phy *rtlphy = &rtlpriv->phy;
350326 	u8 value = 0;
351327 	if (path > RF90_PATH_D) {
352
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
353
-			 "Invalid Rf Path %d in PHY_GetTxPowerByRateBase()\n",
354
-			  path);
328
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
329
+			"Invalid Rf Path %d in PHY_GetTxPowerByRateBase()\n",
330
+			path);
355331 		return 0;
356332 	}
357333 
....@@ -370,15 +346,15 @@
370346 			value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3];
371347 			break;
372348 		default:
373
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
374
-				 "Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n",
375
-				 rate_section, path, txnum);
349
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
350
+				"Invalid RateSection %d in Band 2.4G, Rf Path %d, %dTx in PHY_GetTxPowerByRateBase()\n",
351
+				rate_section, path, txnum);
376352 			break;
377
-		};
353
+		}
378354 	} else {
379
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
380
-			 "Invalid Band %d in PHY_GetTxPowerByRateBase()\n",
381
-			 band);
355
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
356
+			"Invalid Band %d in PHY_GetTxPowerByRateBase()\n",
357
+			band);
382358 	}
383359 
384360 	return value;
....@@ -501,8 +477,8 @@
501477 	    &rtlphy->tx_power_by_rate_offset[BAND_ON_2_4G][rfpath][RF_2TX][7],
502478 	    0, 3, base);
503479 
504
-	RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
505
-	    "<===_rtl8723be_phy_convert_txpower_dbm_to_relative_value()\n");
480
+	rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
481
+		"<===%s\n", __func__);
506482 }
507483 
508484 static void phy_txpower_by_rate_config(struct ieee80211_hw *hw)
....@@ -612,7 +588,7 @@
612588 {
613589 	struct rtl_priv *rtlpriv = rtl_priv(hw);
614590 
615
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read rtl8723beMACPHY_Array\n");
591
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read rtl8723beMACPHY_Array\n");
616592 
617593 	return rtl8723be_phy_config_with_headerfile(hw,
618594 			RTL8723BEMAC_1T_ARRAY, RTL8723BEMAC_1T_ARRAYLEN,
....@@ -694,7 +670,7 @@
694670 		else if (regaddr >= 0xE20 && regaddr <= 0xE4C)
695671 			index = (u8)((regaddr - 0xE20) / 4);
696672 		break;
697
-	};
673
+	}
698674 	return index;
699675 }
700676 
....@@ -708,16 +684,16 @@
708684 	u8 rate_section = _rtl8723be_get_rate_section_index(regaddr);
709685 
710686 	if (band != BAND_ON_2_4G && band != BAND_ON_5G) {
711
-		RT_TRACE(rtlpriv, FPHY, PHY_TXPWR, "Invalid Band %d\n", band);
687
+		rtl_dbg(rtlpriv, FPHY, PHY_TXPWR, "Invalid Band %d\n", band);
712688 		return;
713689 	}
714690 	if (rfpath > MAX_RF_PATH - 1) {
715
-		RT_TRACE(rtlpriv, FPHY, PHY_TXPWR,
716
-			 "Invalid RfPath %d\n", rfpath);
691
+		rtl_dbg(rtlpriv, FPHY, PHY_TXPWR,
692
+			"Invalid RfPath %d\n", rfpath);
717693 		return;
718694 	}
719695 	if (txnum > MAX_RF_PATH - 1) {
720
-		RT_TRACE(rtlpriv, FPHY, PHY_TXPWR, "Invalid TxNum %d\n", txnum);
696
+		rtl_dbg(rtlpriv, FPHY, PHY_TXPWR, "Invalid TxNum %d\n", txnum);
721697 		return;
722698 	}
723699 
....@@ -758,8 +734,8 @@
758734 			}
759735 		}
760736 	} else {
761
-		RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
762
-			 "configtype != BaseBand_Config_PHY_REG\n");
737
+		rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,
738
+			"configtype != BaseBand_Config_PHY_REG\n");
763739 	}
764740 	return true;
765741 }
....@@ -771,7 +747,7 @@
771747 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
772748 	bool ret = true;
773749 
774
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
750
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
775751 	switch (rfpath) {
776752 	case RF90_PATH_A:
777753 		ret =  rtl8723be_phy_config_with_headerfile(hw,
....@@ -786,8 +762,8 @@
786762 	case RF90_PATH_C:
787763 		break;
788764 	case RF90_PATH_D:
789
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
790
-			 "switch case %#x not processed\n", rfpath);
765
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
766
+			"switch case %#x not processed\n", rfpath);
791767 		break;
792768 	}
793769 	return ret;
....@@ -807,21 +783,21 @@
807783 	rtlphy->default_initialgain[3] =
808784 	    (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
809785 
810
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
811
-		 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
812
-		 rtlphy->default_initialgain[0],
813
-		 rtlphy->default_initialgain[1],
814
-		 rtlphy->default_initialgain[2],
815
-		 rtlphy->default_initialgain[3]);
786
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
787
+		"Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
788
+		rtlphy->default_initialgain[0],
789
+		rtlphy->default_initialgain[1],
790
+		rtlphy->default_initialgain[2],
791
+		rtlphy->default_initialgain[3]);
816792 
817793 	rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
818794 					       MASKBYTE0);
819795 	rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
820796 					      MASKDWORD);
821797 
822
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
823
-		 "Default framesync (0x%x) = 0x%x\n",
824
-		  ROFDM0_RXDETECTOR3, rtlphy->framesync);
798
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
799
+		"Default framesync (0x%x) = 0x%x\n",
800
+		ROFDM0_RXDETECTOR3, rtlphy->framesync);
825801 }
826802 
827803 static u8 _rtl8723be_phy_get_ratesection_intxpower_byrate(enum radio_path path,
....@@ -974,16 +950,16 @@
974950 
975951 	if (channel > 14 || channel < 1) {
976952 		index = 0;
977
-		RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
978
-			 "Illegal channel!\n");
953
+		rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
954
+			"Illegal channel!\n");
979955 	}
980956 	if (RX_HAL_IS_CCK_RATE(rate))
981957 		txpower = rtlefuse->txpwrlevel_cck[path][index];
982958 	else if (DESC92C_RATE6M <= rate)
983959 		txpower = rtlefuse->txpwrlevel_ht40_1s[path][index];
984960 	else
985
-		RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
986
-			 "invalid rate\n");
961
+		rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
962
+			"invalid rate\n");
987963 
988964 	if (DESC92C_RATE6M <= rate && rate <= DESC92C_RATE54M &&
989965 	    !RX_HAL_IS_CCK_RATE(rate))
....@@ -1123,11 +1099,11 @@
11231099 			break;
11241100 
11251101 		default:
1126
-			RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid Rate!!\n");
1102
+			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid Rate!!\n");
11271103 			break;
11281104 		}
11291105 	} else {
1130
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid RFPath!!\n");
1106
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid RFPath!!\n");
11311107 	}
11321108 }
11331109 
....@@ -1211,10 +1187,10 @@
12111187 	u8 reg_bw_opmode;
12121188 	u8 reg_prsr_rsc;
12131189 
1214
-	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1215
-		 "Switch to %s bandwidth\n",
1216
-		  rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1217
-		  "20MHz" : "40MHz");
1190
+	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
1191
+		"Switch to %s bandwidth\n",
1192
+		rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1193
+		"20MHz" : "40MHz");
12181194 
12191195 	if (is_hal_stop(rtlhal)) {
12201196 		rtlphy->set_bwmode_inprogress = false;
....@@ -1268,7 +1244,7 @@
12681244 	}
12691245 	rtl8723be_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
12701246 	rtlphy->set_bwmode_inprogress = false;
1271
-	RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, "\n");
1247
+	rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, "\n");
12721248 }
12731249 
12741250 void rtl8723be_phy_set_bw_mode(struct ieee80211_hw *hw,
....@@ -1285,8 +1261,8 @@
12851261 	if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
12861262 		rtl8723be_phy_set_bw_mode_callback(hw);
12871263 	} else {
1288
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1289
-			 "false driver sleep or unload\n");
1264
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1265
+			"false driver sleep or unload\n");
12901266 		rtlphy->set_bwmode_inprogress = false;
12911267 		rtlphy->current_chan_bw = tmp_bw;
12921268 	}
....@@ -1299,8 +1275,8 @@
12991275 	struct rtl_phy *rtlphy = &rtlpriv->phy;
13001276 	u32 delay = 0;
13011277 
1302
-	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1303
-		 "switch to channel%d\n", rtlphy->current_channel);
1278
+	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
1279
+		"switch to channel%d\n", rtlphy->current_channel);
13041280 	if (is_hal_stop(rtlhal))
13051281 		return;
13061282 	do {
....@@ -1320,7 +1296,7 @@
13201296 		}
13211297 		break;
13221298 	} while (true);
1323
-	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
1299
+	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
13241300 }
13251301 
13261302 u8 rtl8723be_phy_sw_chnl(struct ieee80211_hw *hw)
....@@ -1340,13 +1316,13 @@
13401316 	rtlphy->sw_chnl_step = 0;
13411317 	if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
13421318 		rtl8723be_phy_sw_chnl_callback(hw);
1343
-		RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1344
-			 "sw_chnl_inprogress false schedule workitem current channel %d\n",
1345
-			 rtlphy->current_channel);
1319
+		rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
1320
+			"sw_chnl_inprogress false schedule workitem current channel %d\n",
1321
+			rtlphy->current_channel);
13461322 		rtlphy->sw_chnl_inprogress = false;
13471323 	} else {
1348
-		RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1349
-			 "sw_chnl_inprogress false driver sleep or unload\n");
1324
+		rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
1325
+			"sw_chnl_inprogress false driver sleep or unload\n");
13501326 		rtlphy->sw_chnl_inprogress = false;
13511327 	}
13521328 	return 1;
....@@ -1452,9 +1428,9 @@
14521428 			}
14531429 			break;
14541430 		default:
1455
-			RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1456
-				 "switch case %#x not processed\n",
1457
-				 currentcmd->cmdid);
1431
+			rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1432
+				"switch case %#x not processed\n",
1433
+				currentcmd->cmdid);
14581434 			break;
14591435 		}
14601436 
....@@ -2082,7 +2058,7 @@
20822058 	for (i = 0; i < retrycount; i++) {
20832059 		patha_ok = _rtl8723be_phy_path_a_iqk(hw);
20842060 		if (patha_ok == 0x01) {
2085
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2061
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
20862062 				"Path A Tx IQK Success!!\n");
20872063 			result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
20882064 					0x3FF0000) >> 16;
....@@ -2090,36 +2066,36 @@
20902066 					0x3FF0000) >> 16;
20912067 			break;
20922068 		} else {
2093
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2094
-				 "Path A Tx IQK Fail!!\n");
2069
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2070
+				"Path A Tx IQK Fail!!\n");
20952071 		}
20962072 	}
20972073 	/* path A RX IQK */
20982074 	for (i = 0; i < retrycount; i++) {
20992075 		patha_ok = _rtl8723be_phy_path_a_rx_iqk(hw);
21002076 		if (patha_ok == 0x03) {
2101
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2102
-				 "Path A Rx IQK Success!!\n");
2077
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2078
+				"Path A Rx IQK Success!!\n");
21032079 			result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
21042080 					0x3FF0000) >> 16;
21052081 			result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
21062082 					0x3FF0000) >> 16;
21072083 			break;
21082084 		}
2109
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2110
-			 "Path A Rx IQK Fail!!\n");
2085
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2086
+			"Path A Rx IQK Fail!!\n");
21112087 	}
21122088 
21132089 	if (0x00 == patha_ok)
2114
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Path A IQK Fail!!\n");
2090
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Path A IQK Fail!!\n");
21152091 
21162092 	if (is2t) {
21172093 		/* path B TX IQK */
21182094 		for (i = 0; i < retrycount; i++) {
21192095 			pathb_ok = _rtl8723be_phy_path_b_iqk(hw);
21202096 			if (pathb_ok == 0x01) {
2121
-				RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2122
-					 "Path B Tx IQK Success!!\n");
2097
+				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2098
+					"Path B Tx IQK Success!!\n");
21232099 				result[t][4] = (rtl_get_bbreg(hw, 0xe94,
21242100 							      MASKDWORD) &
21252101 							      0x3FF0000) >> 16;
....@@ -2128,15 +2104,15 @@
21282104 							      0x3FF0000) >> 16;
21292105 				break;
21302106 			}
2131
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2132
-				 "Path B Tx IQK Fail!!\n");
2107
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2108
+				"Path B Tx IQK Fail!!\n");
21332109 		}
21342110 		/* path B RX IQK */
21352111 		for (i = 0; i < retrycount; i++) {
21362112 			pathb_ok = _rtl8723be_phy_path_b_rx_iqk(hw);
21372113 			if (pathb_ok == 0x03) {
2138
-				RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2139
-					 "Path B Rx IQK Success!!\n");
2114
+				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2115
+					"Path B Rx IQK Success!!\n");
21402116 				result[t][6] = (rtl_get_bbreg(hw, 0xea4,
21412117 							      MASKDWORD) &
21422118 							      0x3FF0000) >> 16;
....@@ -2145,8 +2121,8 @@
21452121 							      0x3FF0000) >> 16;
21462122 				break;
21472123 			}
2148
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2149
-				 "Path B Rx IQK Fail!!\n");
2124
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2125
+				"Path B Rx IQK Fail!!\n");
21502126 		}
21512127 	}
21522128 
....@@ -2174,7 +2150,7 @@
21742150 		rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
21752151 		rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
21762152 	}
2177
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "8723be IQK Finish!!\n");
2153
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "8723be IQK Finish!!\n");
21782154 }
21792155 
21802156 static u8 _get_right_chnl_place_for_iqk(u8 chnl)
....@@ -2248,14 +2224,14 @@
22482224 	} else {
22492225 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
22502226 	}
2251
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
2227
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
22522228 }
22532229 
22542230 static void _rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw,
22552231 					     bool bmain, bool is2t)
22562232 {
22572233 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2258
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
2234
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
22592235 
22602236 	if (bmain) /* left antenna */
22612237 		rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x1);
....@@ -2273,8 +2249,8 @@
22732249 	long result[4][8];
22742250 	u8 i, final_candidate, idx;
22752251 	bool b_patha_ok, b_pathb_ok;
2276
-	long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4;
2277
-	long reg_ecc, reg_tmp = 0;
2252
+	long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_ec4;
2253
+	long reg_tmp = 0;
22782254 	bool is12simular, is13simular, is23simular;
22792255 	u32 iqk_bb_reg[9] = {
22802256 		ROFDM0_XARXIQIMBALANCE,
....@@ -2356,11 +2332,9 @@
23562332 		reg_e94 = result[i][0];
23572333 		reg_e9c = result[i][1];
23582334 		reg_ea4 = result[i][2];
2359
-		reg_eac = result[i][3];
23602335 		reg_eb4 = result[i][4];
23612336 		reg_ebc = result[i][5];
23622337 		reg_ec4 = result[i][6];
2363
-		reg_ecc = result[i][7];
23642338 	}
23652339 	if (final_candidate != 0xff) {
23662340 		reg_e94 = result[final_candidate][0];
....@@ -2368,13 +2342,11 @@
23682342 		reg_e9c = result[final_candidate][1];
23692343 		rtlphy->reg_e9c = reg_e9c;
23702344 		reg_ea4 = result[final_candidate][2];
2371
-		reg_eac = result[final_candidate][3];
23722345 		reg_eb4 = result[final_candidate][4];
23732346 		rtlphy->reg_eb4 = reg_eb4;
23742347 		reg_ebc = result[final_candidate][5];
23752348 		rtlphy->reg_ebc = reg_ebc;
23762349 		reg_ec4 = result[final_candidate][6];
2377
-		reg_ecc = result[final_candidate][7];
23782350 		b_patha_ok = true;
23792351 		b_pathb_ok = true;
23802352 	} else {
....@@ -2446,24 +2418,24 @@
24462418 	struct rtl_phy *rtlphy = &rtlpriv->phy;
24472419 	bool b_postprocessing = false;
24482420 
2449
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2450
-		 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2451
-		  iotype, rtlphy->set_io_inprogress);
2421
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2422
+		"-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2423
+		iotype, rtlphy->set_io_inprogress);
24522424 	do {
24532425 		switch (iotype) {
24542426 		case IO_CMD_RESUME_DM_BY_SCAN:
2455
-			RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2456
-				 "[IO CMD] Resume DM after scan.\n");
2427
+			rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2428
+				"[IO CMD] Resume DM after scan.\n");
24572429 			b_postprocessing = true;
24582430 			break;
24592431 		case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
2460
-			RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2461
-				 "[IO CMD] Pause DM before scan.\n");
2432
+			rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2433
+				"[IO CMD] Pause DM before scan.\n");
24622434 			b_postprocessing = true;
24632435 			break;
24642436 		default:
2465
-			RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2466
-				 "switch case %#x not processed\n", iotype);
2437
+			rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
2438
+				"switch case %#x not processed\n", iotype);
24672439 			break;
24682440 		}
24692441 	} while (false);
....@@ -2474,7 +2446,7 @@
24742446 		return false;
24752447 	}
24762448 	rtl8723be_phy_set_io(hw);
2477
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
2449
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
24782450 	return true;
24792451 }
24802452 
....@@ -2484,9 +2456,9 @@
24842456 	struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
24852457 	struct rtl_phy *rtlphy = &rtlpriv->phy;
24862458 
2487
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2488
-		 "--->Cmd(%#x), set_io_inprogress(%d)\n",
2489
-		  rtlphy->current_io_type, rtlphy->set_io_inprogress);
2459
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2460
+		"--->Cmd(%#x), set_io_inprogress(%d)\n",
2461
+		rtlphy->current_io_type, rtlphy->set_io_inprogress);
24902462 	switch (rtlphy->current_io_type) {
24912463 	case IO_CMD_RESUME_DM_BY_SCAN:
24922464 		dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
....@@ -2500,14 +2472,14 @@
25002472 		rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40);
25012473 		break;
25022474 	default:
2503
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2504
-			 "switch case %#x not processed\n",
2505
-			 rtlphy->current_io_type);
2475
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
2476
+			"switch case %#x not processed\n",
2477
+			rtlphy->current_io_type);
25062478 		break;
25072479 	}
25082480 	rtlphy->set_io_inprogress = false;
2509
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2510
-		 "(%#x)\n", rtlphy->current_io_type);
2481
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2482
+		"(%#x)\n", rtlphy->current_io_type);
25112483 }
25122484 
25132485 static void rtl8723be_phy_set_rf_on(struct ieee80211_hw *hw)
....@@ -2550,16 +2522,16 @@
25502522 			u32 initializecount = 0;
25512523 			do {
25522524 				initializecount++;
2553
-				RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2554
-					 "IPS Set eRf nic enable\n");
2525
+				rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2526
+					"IPS Set eRf nic enable\n");
25552527 				rtstatus = rtl_ps_enable_nic(hw);
25562528 			} while (!rtstatus && (initializecount < 10));
25572529 			RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
25582530 		} else {
2559
-			RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2560
-				 "Set ERFON sleeped:%d ms\n",
2561
-				  jiffies_to_msecs(jiffies -
2562
-						   ppsc->last_sleep_jiffies));
2531
+			rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2532
+				"Set ERFON slept:%d ms\n",
2533
+				jiffies_to_msecs(jiffies -
2534
+						 ppsc->last_sleep_jiffies));
25632535 			ppsc->last_awake_jiffies = jiffies;
25642536 			rtl8723be_phy_set_rf_on(hw);
25652537 		}
....@@ -2583,27 +2555,27 @@
25832555 				queue_id++;
25842556 				continue;
25852557 			} else {
2586
-				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2587
-					 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2588
-					 (i + 1), queue_id,
2589
-					 skb_queue_len(&ring->queue));
2558
+				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
2559
+					"eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2560
+					(i + 1), queue_id,
2561
+					skb_queue_len(&ring->queue));
25902562 
25912563 				udelay(10);
25922564 				i++;
25932565 			}
25942566 			if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2595
-				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2596
-					 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2597
-					  MAX_DOZE_WAITING_TIMES_9x,
2598
-					  queue_id,
2599
-					  skb_queue_len(&ring->queue));
2567
+				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
2568
+					"ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2569
+					MAX_DOZE_WAITING_TIMES_9x,
2570
+					queue_id,
2571
+					skb_queue_len(&ring->queue));
26002572 				break;
26012573 			}
26022574 		}
26032575 
26042576 		if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
2605
-			RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2606
-				 "IPS Set eRf nic disable\n");
2577
+			rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2578
+				"IPS Set eRf nic disable\n");
26072579 			rtl_ps_disable_nic(hw);
26082580 			RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
26092581 		} else {
....@@ -2627,34 +2599,34 @@
26272599 				queue_id++;
26282600 				continue;
26292601 			} else {
2630
-				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2631
-					 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2632
-					 (i + 1), queue_id,
2633
-					 skb_queue_len(&ring->queue));
2602
+				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
2603
+					"eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2604
+					(i + 1), queue_id,
2605
+					skb_queue_len(&ring->queue));
26342606 
26352607 				udelay(10);
26362608 				i++;
26372609 			}
26382610 			if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2639
-				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2640
-					 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2641
-					 MAX_DOZE_WAITING_TIMES_9x,
2642
-					 queue_id,
2643
-					 skb_queue_len(&ring->queue));
2611
+				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
2612
+					"ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2613
+					MAX_DOZE_WAITING_TIMES_9x,
2614
+					queue_id,
2615
+					skb_queue_len(&ring->queue));
26442616 				break;
26452617 			}
26462618 		}
2647
-		RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2648
-			 "Set ERFSLEEP awaked:%d ms\n",
2649
-			  jiffies_to_msecs(jiffies -
2650
-					   ppsc->last_awake_jiffies));
2619
+		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2620
+			"Set ERFSLEEP awaked:%d ms\n",
2621
+			jiffies_to_msecs(jiffies -
2622
+					 ppsc->last_awake_jiffies));
26512623 		ppsc->last_sleep_jiffies = jiffies;
26522624 		_rtl8723be_phy_set_rf_sleep(hw);
26532625 		break;
26542626 
26552627 	default:
2656
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2657
-			 "switch case %#x not processed\n", rfpwr_state);
2628
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
2629
+			"switch case %#x not processed\n", rfpwr_state);
26582630 		bresult = false;
26592631 		break;
26602632 	}