forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc 
 kernel/drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c
....@@ -1,27 +1,5 @@
1
-/******************************************************************************
2
- *
3
- * Copyright(c) 2009-2014  Realtek Corporation.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of version 2 of the GNU General Public License as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
14
- * The full GNU General Public License is included in this distribution in the
15
- * file called LICENSE.
16
- *
17
- * Contact Information:
18
- * wlanfae <wlanfae@realtek.com>
19
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20
- * Hsinchu 300, Taiwan.
21
- *
22
- * Larry Finger <Larry.Finger@lwfinger.net>
23
- *
24
- *****************************************************************************/
1
+// SPDX-License-Identifier: GPL-2.0
2
+/* Copyright(c) 2009-2014  Realtek Corporation.*/
253 
264 #include "../wifi.h"
275 #include "../efuse.h"
....@@ -52,22 +30,25 @@
5230 	struct rtl_priv *rtlpriv = rtl_priv(hw);
5331 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
5432 	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
33
+	struct sk_buff_head free_list;
5534 	unsigned long flags;
5635 
36
+	skb_queue_head_init(&free_list);
5737 	spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
5838 	while (skb_queue_len(&ring->queue)) {
5939 		struct rtl_tx_desc *entry = &ring->desc[ring->idx];
6040 		struct sk_buff *skb = __skb_dequeue(&ring->queue);
6141 
62
-		pci_unmap_single(rtlpci->pdev,
63
-				 rtlpriv->cfg->ops->get_desc(
64
-				 hw,
65
-				 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
66
-				 skb->len, PCI_DMA_TODEVICE);
67
-		kfree_skb(skb);
42
+		dma_unmap_single(&rtlpci->pdev->dev,
43
+				 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
44
+						true, HW_DESC_TXBUFF_ADDR),
45
+				 skb->len, DMA_TO_DEVICE);
46
+		__skb_queue_tail(&free_list, skb);
6847 		ring->idx = (ring->idx + 1) % ring->entries;
6948 	}
7049 	spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
50
+
51
+	__skb_queue_purge(&free_list);
7152 }
7253 
7354 static void _rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
....@@ -168,9 +149,9 @@
168149 			if (content & IMR_CPWM) {
169150 				rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
170151 				rtlhal->fw_ps_state = FW_PS_STATE_RF_ON;
171
-				RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
172
-					 "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
173
-					 rtlhal->fw_ps_state);
152
+				rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
153
+					"Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
154
+					rtlhal->fw_ps_state);
174155 			}
175156 		}
176157 
....@@ -319,12 +300,12 @@
319300 		*((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
320301 		break;
321302 	case HW_VAR_FWLPS_RF_ON:{
322
-		enum rf_pwrstate rfState;
303
+		enum rf_pwrstate rfstate;
323304 		u32 val_rcr;
324305 
325306 		rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
326
-					      (u8 *)(&rfState));
327
-		if (rfState == ERFOFF) {
307
+					      (u8 *)(&rfstate));
308
+		if (rfstate == ERFOFF) {
328309 			*((bool *)(val)) = true;
329310 		} else {
330311 			val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
....@@ -353,8 +334,8 @@
353334 	case HAL_DEF_WOWLAN:
354335 		break;
355336 	default:
356
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
357
-			 "switch case %#x not processed\n", variable);
337
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
338
+			"switch case %#x not processed\n", variable);
358339 		break;
359340 	}
360341 }
....@@ -458,8 +439,8 @@
458439 	case HW_VAR_SLOT_TIME:{
459440 		u8 e_aci;
460441 
461
-		RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
462
-			 "HW_VAR_SLOT_TIME %x\n", val[0]);
442
+		rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
443
+			"HW_VAR_SLOT_TIME %x\n", val[0]);
463444 
464445 		rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
465446 
....@@ -501,9 +482,9 @@
501482 
502483 			*val = min_spacing_to_set;
503484 
504
-			RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
505
-				 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
506
-				  mac->min_space_cfg);
485
+			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
486
+				"Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
487
+				mac->min_space_cfg);
507488 
508489 			rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
509490 				       mac->min_space_cfg);
....@@ -516,9 +497,9 @@
516497 		density_to_set = *((u8 *)val);
517498 		mac->min_space_cfg |= (density_to_set << 3);
518499 
519
-		RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
520
-			 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
521
-			  mac->min_space_cfg);
500
+		rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
501
+			"Set HW_VAR_SHORTGI_DENSITY: %#x\n",
502
+			mac->min_space_cfg);
522503 
523504 		rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
524505 			       mac->min_space_cfg);
....@@ -556,9 +537,9 @@
556537 
557538 			}
558539 
559
-			RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
560
-				 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
561
-				  factor_toset);
540
+			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
541
+				"Set HW_VAR_AMPDU_FACTOR: %#x\n",
542
+				factor_toset);
562543 		}
563544 		}
564545 		break;
....@@ -593,9 +574,9 @@
593574 				acm_ctrl |= ACMHW_VOQEN;
594575 				break;
595576 			default:
596
-				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
597
-					 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
598
-					 acm);
577
+				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
578
+					"HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
579
+					acm);
599580 				break;
600581 			}
601582 		} else {
....@@ -610,16 +591,16 @@
610591 				acm_ctrl &= (~ACMHW_VOQEN);
611592 				break;
612593 			default:
613
-				RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
614
-					 "switch case %#x not processed\n",
615
-					 e_aci);
594
+				rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
595
+					"switch case %#x not processed\n",
596
+					e_aci);
616597 				break;
617598 			}
618599 		}
619600 
620
-		RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
621
-			 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
622
-			 acm_ctrl);
601
+		rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
602
+			"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
603
+			acm_ctrl);
623604 		rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
624605 		}
625606 		break;
....@@ -727,8 +708,8 @@
727708 		}
728709 		break;
729710 	default:
730
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
731
-			 "switch case %#x not processed\n", variable);
711
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
712
+			"switch case %#x not processed\n", variable);
732713 		break;
733714 	}
734715 }
....@@ -764,10 +745,10 @@
764745 	struct rtl_priv *rtlpriv = rtl_priv(hw);
765746 	unsigned short i;
766747 	u8 txpktbuf_bndy;
767
-	u8 maxPage;
748
+	u8 maxpage;
768749 	bool status;
769750 
770
-	maxPage = 255;
751
+	maxpage = 255;
771752 	txpktbuf_bndy = 245;
772753 
773754 	rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
....@@ -792,13 +773,13 @@
792773 	if (!status)
793774 		return status;
794775 
795
-	for (i = txpktbuf_bndy; i < maxPage; i++) {
776
+	for (i = txpktbuf_bndy; i < maxpage; i++) {
796777 		status = _rtl8723be_llt_write(hw, i, (i + 1));
797778 		if (!status)
798779 			return status;
799780 	}
800781 
801
-	status = _rtl8723be_llt_write(hw, maxPage, txpktbuf_bndy);
782
+	status = _rtl8723be_llt_write(hw, maxpage, txpktbuf_bndy);
802783 	if (!status)
803784 		return status;
804785 
....@@ -843,8 +824,8 @@
843824 	if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
844825 				      PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
845826 				      RTL8723_NIC_ENABLE_FLOW)) {
846
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
847
-			 "init MAC Fail as power on failure\n");
827
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
828
+			"init MAC Fail as power on failure\n");
848829 		return false;
849830 	}
850831 
....@@ -881,7 +862,7 @@
881862 	rtl_write_word(rtlpriv, REG_CR, 0x2ff);
882863 
883864 	if (!rtlhal->mac_func_enable) {
884
-		if (_rtl8723be_llt_table_init(hw) == false)
865
+		if (!_rtl8723be_llt_table_init(hw))
885866 			return false;
886867 	}
887868 
....@@ -1143,14 +1124,14 @@
11431124 	struct rtl_priv *rtlpriv = rtl_priv(hw);
11441125 	u8 sec_reg_value;
11451126 
1146
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1147
-		 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1148
-		  rtlpriv->sec.pairwise_enc_algorithm,
1149
-		  rtlpriv->sec.group_enc_algorithm);
1127
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1128
+		"PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1129
+		rtlpriv->sec.pairwise_enc_algorithm,
1130
+		rtlpriv->sec.group_enc_algorithm);
11501131 
11511132 	if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1152
-		RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1153
-			 "not open hw encryption\n");
1133
+		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1134
+			"not open hw encryption\n");
11541135 		return;
11551136 	}
11561137 
....@@ -1165,8 +1146,8 @@
11651146 
11661147 	rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
11671148 
1168
-	RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1169
-		 "The SECR-value %x\n", sec_reg_value);
1149
+	rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1150
+		"The SECR-value %x\n", sec_reg_value);
11701151 
11711152 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
11721153 }
....@@ -1230,8 +1211,8 @@
12301211 	 */
12311212 	tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
12321213 	if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1233
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1234
-			 "CheckPcieDMAHang8723BE(): true!!\n");
1214
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1215
+			"CheckPcieDMAHang8723BE(): true!!\n");
12351216 		return true;
12361217 	}
12371218 	return false;
....@@ -1244,8 +1225,8 @@
12441225 	bool release_mac_rx_pause;
12451226 	u8 backup_pcie_dma_pause;
12461227 
1247
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1248
-		 "ResetPcieInterfaceDMA8723BE()\n");
1228
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1229
+		"ResetPcieInterfaceDMA8723BE()\n");
12491230 
12501231 	/* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
12511232 	 * released by SD1 Alan.
....@@ -1397,8 +1378,8 @@
13971378 
13981379 	err = rtl8723_download_fw(hw, true, FW_8723B_POLLING_TIMEOUT_COUNT);
13991380 	if (err) {
1400
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1401
-			 "Failed to download FW. Init HW without FW now..\n");
1381
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1382
+			"Failed to download FW. Init HW without FW now..\n");
14021383 		err = 1;
14031384 		goto exit;
14041385 	}
....@@ -1482,7 +1463,7 @@
14821463 
14831464 	value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
14841465 	if ((value32 & (CHIP_8723B)) != CHIP_8723B)
1485
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "unknown chip version\n");
1466
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "unknown chip version\n");
14861467 	else
14871468 		version = (enum version_8723e)CHIP_8723B;
14881469 
....@@ -1498,9 +1479,9 @@
14981479 	if (((value32 & EXT_VENDOR_ID) >> 18) == 0x01)
14991480 		version = (enum version_8723e)(version | CHIP_VENDOR_SMIC);
15001481 
1501
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1502
-		 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1503
-		  "RF_2T2R" : "RF_1T1R");
1482
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1483
+		"Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1484
+		"RF_2T2R" : "RF_1T1R");
15041485 
15051486 	return version;
15061487 }
....@@ -1516,26 +1497,26 @@
15161497 	switch (type) {
15171498 	case NL80211_IFTYPE_UNSPECIFIED:
15181499 		mode = MSR_NOLINK;
1519
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1520
-			 "Set Network type to NO LINK!\n");
1500
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1501
+			"Set Network type to NO LINK!\n");
15211502 		break;
15221503 	case NL80211_IFTYPE_ADHOC:
15231504 	case NL80211_IFTYPE_MESH_POINT:
15241505 		mode = MSR_ADHOC;
1525
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1526
-			 "Set Network type to Ad Hoc!\n");
1506
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1507
+			"Set Network type to Ad Hoc!\n");
15271508 		break;
15281509 	case NL80211_IFTYPE_STATION:
15291510 		mode = MSR_INFRA;
15301511 		ledaction = LED_CTL_LINK;
1531
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1532
-			 "Set Network type to STA!\n");
1512
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1513
+			"Set Network type to STA!\n");
15331514 		break;
15341515 	case NL80211_IFTYPE_AP:
15351516 		mode = MSR_AP;
15361517 		ledaction = LED_CTL_LINK;
1537
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1538
-			 "Set Network type to AP!\n");
1518
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1519
+			"Set Network type to AP!\n");
15391520 		break;
15401521 	default:
15411522 		pr_err("Network type %d not support!\n", type);
....@@ -1560,9 +1541,9 @@
15601541 		_rtl8723be_resume_tx_beacon(hw);
15611542 		_rtl8723be_disable_bcn_sub_func(hw);
15621543 	} else {
1563
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1564
-			 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1565
-			 mode);
1544
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1545
+			"Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1546
+			mode);
15661547 	}
15671548 
15681549 	rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
....@@ -1724,8 +1705,8 @@
17241705 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
17251706 	u16 bcn_interval = mac->beacon_interval;
17261707 
1727
-	RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1728
-		 "beacon_interval:%d\n", bcn_interval);
1708
+	rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
1709
+		"beacon_interval:%d\n", bcn_interval);
17291710 	rtl8723be_disable_interrupt(hw);
17301711 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
17311712 	rtl8723be_enable_interrupt(hw);
....@@ -1737,8 +1718,8 @@
17371718 	struct rtl_priv *rtlpriv = rtl_priv(hw);
17381719 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
17391720 
1740
-	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1741
-		 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1721
+	rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
1722
+		"add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
17421723 
17431724 	if (add_msr)
17441725 		rtlpci->irq_mask[0] |= add_msr;
....@@ -1769,15 +1750,15 @@
17691750 	struct rtl_priv *rtlpriv = rtl_priv(hw);
17701751 	u32 path, addr = EEPROM_TX_PWR_INX, group, cnt = 0;
17711752 
1772
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1773
-		 "hal_ReadPowerValueFromPROM8723BE(): PROMContent[0x%x]=0x%x\n",
1774
-		 (addr + 1), hwinfo[addr + 1]);
1753
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1754
+		"hal_ReadPowerValueFromPROM8723BE(): PROMContent[0x%x]=0x%x\n",
1755
+		(addr + 1), hwinfo[addr + 1]);
17751756 	if (0xFF == hwinfo[addr + 1])  /*YJ,add,120316*/
17761757 		autoload_fail = true;
17771758 
17781759 	if (autoload_fail) {
1779
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1780
-			 "auto load fail : Use Default value!\n");
1760
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1761
+			"auto load fail : Use Default value!\n");
17811762 		for (path = 0; path < MAX_RF_PATH; path++) {
17821763 			/* 2.4G default value */
17831764 			for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
....@@ -2121,8 +2102,8 @@
21212102 		rtlefuse->board_type |= BIT(2); /* ODM_BOARD_BT */
21222103 
21232104 	rtlhal->board_type = rtlefuse->board_type;
2124
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2125
-		 "board_type = 0x%x\n", rtlefuse->board_type);
2105
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2106
+		"board_type = 0x%x\n", rtlefuse->board_type);
21262107 
21272108 	rtlhal->package_type = _rtl8723be_read_package_type(hw);
21282109 
....@@ -2259,8 +2240,8 @@
22592240 	default:
22602241 		break;
22612242 	}
2262
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2263
-		 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2243
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2244
+		"RT Customized ID: 0x%02X\n", rtlhal->oem_id);
22642245 }
22652246 
22662247 void rtl8723be_read_eeprom_info(struct ieee80211_hw *hw)
....@@ -2277,18 +2258,18 @@
22772258 	else
22782259 		rtlpriv->dm.rfpath_rxenable[0] =
22792260 		    rtlpriv->dm.rfpath_rxenable[1] = true;
2280
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2281
-		 rtlhal->version);
2261
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2262
+		rtlhal->version);
22822263 	tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
22832264 	if (tmp_u1b & BIT(4)) {
2284
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2265
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
22852266 		rtlefuse->epromtype = EEPROM_93C46;
22862267 	} else {
2287
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2268
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
22882269 		rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
22892270 	}
22902271 	if (tmp_u1b & BIT(5)) {
2291
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2272
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
22922273 		rtlefuse->autoload_failflag = false;
22932274 		_rtl8723be_read_adapter_info(hw, false);
22942275 	} else {
....@@ -2439,8 +2420,8 @@
24392420 
24402421 	sta_entry->ratr_index = ratr_index;
24412422 
2442
-	RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2443
-		 "ratr_bitmap :%x\n", ratr_bitmap);
2423
+	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2424
+		"ratr_bitmap :%x\n", ratr_bitmap);
24442425 	*(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
24452426 				       (ratr_index << 28);
24462427 	rate_mask[0] = macid;
....@@ -2453,13 +2434,13 @@
24532434 	rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
24542435 	rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
24552436 
2456
-	RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2457
-		 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2458
-		 ratr_index, ratr_bitmap,
2459
-		 rate_mask[0], rate_mask[1],
2460
-		 rate_mask[2], rate_mask[3],
2461
-		 rate_mask[4], rate_mask[5],
2462
-		 rate_mask[6]);
2437
+	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2438
+		"Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2439
+		ratr_index, ratr_bitmap,
2440
+		rate_mask[0], rate_mask[1],
2441
+		rate_mask[2], rate_mask[3],
2442
+		rate_mask[4], rate_mask[5],
2443
+		rate_mask[6]);
24632444 	rtl8723be_fill_h2c_cmd(hw, H2C_8723B_RA_MASK, 7, rate_mask);
24642445 	_rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
24652446 }
....@@ -2522,15 +2503,15 @@
25222503 		e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
25232504 
25242505 	if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2525
-		RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2526
-			 "GPIOChangeRF  - HW Radio ON, RF ON\n");
2506
+		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2507
+			"GPIOChangeRF  - HW Radio ON, RF ON\n");
25272508 
25282509 		e_rfpowerstate_toset = ERFON;
25292510 		ppsc->hwradiooff = false;
25302511 		b_actuallyset = true;
25312512 	} else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2532
-		RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2533
-			 "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2513
+		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2514
+			"GPIOChangeRF  - HW Radio OFF, RF OFF\n");
25342515 
25352516 		e_rfpowerstate_toset = ERFOFF;
25362517 		ppsc->hwradiooff = true;
....@@ -2581,7 +2562,7 @@
25812562 		u8 cam_offset = 0;
25822563 		u8 clear_number = 5;
25832564 
2584
-		RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2565
+		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
25852566 
25862567 		for (idx = 0; idx < clear_number; idx++) {
25872568 			rtl_cam_mark_invalid(hw, cam_offset + idx);
....@@ -2609,8 +2590,8 @@
26092590 			enc_algo = CAM_AES;
26102591 			break;
26112592 		default:
2612
-			RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2613
-				 "switch case %#x not processed\n", enc_algo);
2593
+			rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
2594
+				"switch case %#x not processed\n", enc_algo);
26142595 			enc_algo = CAM_TKIP;
26152596 			break;
26162597 		}
....@@ -2640,26 +2621,26 @@
26402621 		}
26412622 
26422623 		if (rtlpriv->sec.key_len[key_index] == 0) {
2643
-			RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2644
-				 "delete one entry, entry_id is %d\n",
2645
-				  entry_id);
2624
+			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2625
+				"delete one entry, entry_id is %d\n",
2626
+				entry_id);
26462627 			if (mac->opmode == NL80211_IFTYPE_AP)
26472628 				rtl_cam_del_entry(hw, p_macaddr);
26482629 			rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
26492630 		} else {
2650
-			RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2651
-				 "add one entry\n");
2631
+			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2632
+				"add one entry\n");
26522633 			if (is_pairwise) {
2653
-				RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2654
-					 "set Pairwise key\n");
2634
+				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2635
+					"set Pairwise key\n");
26552636 
26562637 				rtl_cam_add_one_entry(hw, macaddr, key_index,
26572638 					       entry_id, enc_algo,
26582639 					       CAM_CONFIG_NO_USEDK,
26592640 					       rtlpriv->sec.key_buf[key_index]);
26602641 			} else {
2661
-				RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2662
-					 "set group key\n");
2642
+				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2643
+					"set group key\n");
26632644 
26642645 				if (mac->opmode == NL80211_IFTYPE_ADHOC) {
26652646 					rtl_cam_add_one_entry(hw,