forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc 
 kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c
....@@ -1,27 +1,5 @@
1
-/******************************************************************************
2
- *
3
- * Copyright(c) 2009-2014  Realtek Corporation.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of version 2 of the GNU General Public License as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
14
- * The full GNU General Public License is included in this distribution in the
15
- * file called LICENSE.
16
- *
17
- * Contact Information:
18
- * wlanfae <wlanfae@realtek.com>
19
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20
- * Hsinchu 300, Taiwan.
21
- *
22
- * Larry Finger <Larry.Finger@lwfinger.net>
23
- *
24
- *****************************************************************************/
1
+// SPDX-License-Identifier: GPL-2.0
2
+/* Copyright(c) 2009-2014  Realtek Corporation.*/
253 
264 #include "../wifi.h"
275 #include "../efuse.h"
....@@ -141,9 +119,9 @@
141119 			if (content & IMR_CPWM) {
142120 				rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
143121 				rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_92E;
144
-				RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
145
-					 "Receive CPWM INT!!! PSState = %X\n",
146
-					 rtlhal->fw_ps_state);
122
+				rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
123
+					"Receive CPWM INT!!! PSState = %X\n",
124
+					rtlhal->fw_ps_state);
147125 			}
148126 		}
149127 
....@@ -341,8 +319,8 @@
341319 	case HAL_DEF_WOWLAN:
342320 		break;
343321 	default:
344
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
345
-			 "switch case %#x not processed\n", variable);
322
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,
323
+			"switch case %#x not processed\n", variable);
346324 		break;
347325 	}
348326 }
....@@ -412,8 +390,8 @@
412390 	} while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
413391 
414392 	if (!(bcnvalid_reg & BIT(0)))
415
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
416
-			 "Download RSVD page failed!\n");
393
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
394
+			"Download RSVD page failed!\n");
417395 
418396 	/* Enable Bcn */
419397 	_rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
....@@ -469,8 +447,8 @@
469447 	case HW_VAR_SLOT_TIME:{
470448 		u8 e_aci;
471449 
472
-		RT_TRACE(rtlpriv, COMP_MLME, DBG_TRACE,
473
-			 "HW_VAR_SLOT_TIME %x\n", val[0]);
450
+		rtl_dbg(rtlpriv, COMP_MLME, DBG_TRACE,
451
+			"HW_VAR_SLOT_TIME %x\n", val[0]);
474452 
475453 		rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
476454 
....@@ -516,8 +494,8 @@
516494 					       (REG_AGGLEN_LMT + i),
517495 					       reg[i]);
518496 			}
519
-			RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
520
-				 "Set HW_VAR_AMPDU_FACTOR:%#x\n", fac);
497
+			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
498
+				"Set HW_VAR_AMPDU_FACTOR:%#x\n", fac);
521499 		}
522500 		}
523501 		break;
....@@ -550,9 +528,9 @@
550528 				acm_ctrl |= ACMHW_VOQEN;
551529 				break;
552530 			default:
553
-				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
554
-					 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
555
-					 acm);
531
+				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
532
+					"HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
533
+					acm);
556534 				break;
557535 			}
558536 		} else {
....@@ -567,16 +545,16 @@
567545 				acm_ctrl &= (~ACMHW_VOQEN);
568546 				break;
569547 			default:
570
-				RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
571
-					 "switch case %#x not processed\n",
572
-					 e_aci);
548
+				rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,
549
+					"switch case %#x not processed\n",
550
+					e_aci);
573551 				break;
574552 			}
575553 		}
576554 
577
-		RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
578
-			 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
579
-			  acm_ctrl);
555
+		rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
556
+			"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
557
+			acm_ctrl);
580558 		rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
581559 		}
582560 		break;
....@@ -687,8 +665,8 @@
687665 		}
688666 		break;
689667 	default:
690
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
691
-			 "switch case %#x not processed\n", variable);
668
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,
669
+			"switch case %#x not processed\n", variable);
692670 		break;
693671 	}
694672 }
....@@ -793,8 +771,8 @@
793771 	if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
794772 				      PWR_INTF_PCI_MSK,
795773 				      RTL8192E_NIC_ENABLE_FLOW)) {
796
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
797
-			 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
774
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
775
+			"init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
798776 		return false;
799777 	}
800778 
....@@ -816,9 +794,9 @@
816794 	rtl_write_word(rtlpriv, REG_CR, 0x2ff);
817795 
818796 	if (!rtlhal->mac_func_enable) {
819
-		if (_rtl92ee_llt_table_init(hw) == false) {
820
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
821
-				 "LLT table init fail\n");
797
+		if (!_rtl92ee_llt_table_init(hw)) {
798
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
799
+				"LLT table init fail\n");
822800 			return false;
823801 		}
824802 	}
....@@ -1129,14 +1107,14 @@
11291107 	u8 sec_reg_value;
11301108 	u8 tmp;
11311109 
1132
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1133
-		 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1134
-		  rtlpriv->sec.pairwise_enc_algorithm,
1135
-		  rtlpriv->sec.group_enc_algorithm);
1110
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1111
+		"PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1112
+		rtlpriv->sec.pairwise_enc_algorithm,
1113
+		rtlpriv->sec.group_enc_algorithm);
11361114 
11371115 	if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1138
-		RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1139
-			 "not open hw encryption\n");
1116
+		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1117
+			"not open hw encryption\n");
11401118 		return;
11411119 	}
11421120 
....@@ -1152,8 +1130,8 @@
11521130 	tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
11531131 	rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
11541132 
1155
-	RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1156
-		 "The SECR-value %x\n", sec_reg_value);
1133
+	rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1134
+		"The SECR-value %x\n", sec_reg_value);
11571135 
11581136 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
11591137 }
....@@ -1175,8 +1153,8 @@
11751153 	 */
11761154 	tmp = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3);
11771155 	if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1178
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1179
-			 "CheckPcieDMAHang8192EE(): true!!\n");
1156
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1157
+			"CheckPcieDMAHang8192EE(): true!!\n");
11801158 		return true;
11811159 	}
11821160 	return false;
....@@ -1189,8 +1167,8 @@
11891167 	bool release_mac_rx_pause;
11901168 	u8 backup_pcie_dma_pause;
11911169 
1192
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1193
-		 "ResetPcieInterfaceDMA8192EE()\n");
1170
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1171
+		"ResetPcieInterfaceDMA8192EE()\n");
11941172 
11951173 	/* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
11961174 	 * released by SD1 Alan.
....@@ -1303,7 +1281,7 @@
13031281 	u8 tmp_u1b, u1byte;
13041282 	u32 tmp_u4b;
13051283 
1306
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, " Rtl8192EE hw init\n");
1284
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, " Rtl8192EE hw init\n");
13071285 	rtlpriv->rtlhal.being_init_adapter = true;
13081286 	rtlpriv->intf_ops->disable_aspm(hw);
13091287 
....@@ -1317,7 +1295,7 @@
13171295 	}
13181296 
13191297 	if (_rtl8192ee_check_pcie_dma_hang(rtlpriv)) {
1320
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "92ee dma hang!\n");
1298
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "92ee dma hang!\n");
13211299 		_rtl8192ee_reset_pcie_interface_dma(rtlpriv,
13221300 						    rtlhal->mac_func_enable);
13231301 		rtlhal->mac_func_enable = false;
....@@ -1346,8 +1324,8 @@
13461324 	rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, 0x8000);
13471325 	err = rtl92ee_download_fw(hw, false);
13481326 	if (err) {
1349
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1350
-			 "Failed to download FW. Init HW without FW now..\n");
1327
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1328
+			"Failed to download FW. Init HW without FW now..\n");
13511329 		err = 1;
13521330 		rtlhal->fw_ready = false;
13531331 		return err;
....@@ -1423,12 +1401,12 @@
14231401 	efuse_one_byte_read(hw, 0x1FA, &tmp_u1b);
14241402 	if (!(tmp_u1b & BIT(0))) {
14251403 		rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1426
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1404
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
14271405 	}
14281406 
14291407 	if ((!(tmp_u1b & BIT(1))) && (rtlphy->rf_type == RF_2T2R)) {
14301408 		rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1431
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path B\n");
1409
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path B\n");
14321410 	}
14331411 
14341412 	rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
....@@ -1443,8 +1421,8 @@
14431421 
14441422 	rtl_write_dword(rtlpriv, 0x4fc, 0);
14451423 
1446
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1447
-		 "end of Rtl8192EE hw init %x\n", err);
1424
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1425
+		"end of Rtl8192EE hw init %x\n", err);
14481426 	return 0;
14491427 }
14501428 
....@@ -1463,9 +1441,9 @@
14631441 	else
14641442 		version = (enum version_8192e)VERSION_NORMAL_CHIP_2T2R_8192E;
14651443 
1466
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1467
-		 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1468
-		  "RF_2T2R" : "RF_1T1R");
1444
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1445
+		"Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1446
+		"RF_2T2R" : "RF_1T1R");
14691447 
14701448 	return version;
14711449 }
....@@ -1481,26 +1459,26 @@
14811459 	switch (type) {
14821460 	case NL80211_IFTYPE_UNSPECIFIED:
14831461 		mode = MSR_NOLINK;
1484
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1485
-			 "Set Network type to NO LINK!\n");
1462
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1463
+			"Set Network type to NO LINK!\n");
14861464 		break;
14871465 	case NL80211_IFTYPE_ADHOC:
14881466 	case NL80211_IFTYPE_MESH_POINT:
14891467 		mode = MSR_ADHOC;
1490
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1491
-			 "Set Network type to Ad Hoc!\n");
1468
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1469
+			"Set Network type to Ad Hoc!\n");
14921470 		break;
14931471 	case NL80211_IFTYPE_STATION:
14941472 		mode = MSR_INFRA;
14951473 		ledaction = LED_CTL_LINK;
1496
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1497
-			 "Set Network type to STA!\n");
1474
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1475
+			"Set Network type to STA!\n");
14981476 		break;
14991477 	case NL80211_IFTYPE_AP:
15001478 		mode = MSR_AP;
15011479 		ledaction = LED_CTL_LINK;
1502
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1503
-			 "Set Network type to AP!\n");
1480
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1481
+			"Set Network type to AP!\n");
15041482 		break;
15051483 	default:
15061484 		pr_err("Network type %d not support!\n", type);
....@@ -1525,9 +1503,9 @@
15251503 		_rtl92ee_resume_tx_beacon(hw);
15261504 		_rtl92ee_disable_bcn_sub_func(hw);
15271505 	} else {
1528
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1529
-			 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1530
-			 mode);
1506
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1507
+			"Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1508
+			mode);
15311509 	}
15321510 
15331511 	rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
....@@ -1633,7 +1611,7 @@
16331611 
16341612 	rtlhal->mac_func_enable = false;
16351613 
1636
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1614
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
16371615 
16381616 	/* Run LPS WL RFOFF flow */
16391617 	rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
....@@ -1673,7 +1651,7 @@
16731651 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
16741652 	enum nl80211_iftype opmode;
16751653 
1676
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8192ee card disable\n");
1654
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8192ee card disable\n");
16771655 
16781656 	RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
16791657 
....@@ -1732,8 +1710,8 @@
17321710 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
17331711 	u16 bcn_interval = mac->beacon_interval;
17341712 
1735
-	RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1736
-		 "beacon_interval:%d\n", bcn_interval);
1713
+	rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
1714
+		"beacon_interval:%d\n", bcn_interval);
17371715 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
17381716 }
17391717 
....@@ -1743,8 +1721,8 @@
17431721 	struct rtl_priv *rtlpriv = rtl_priv(hw);
17441722 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
17451723 
1746
-	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1747
-		 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1724
+	rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
1725
+		"add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
17481726 
17491727 	if (add_msr)
17501728 		rtlpci->irq_mask[0] |= add_msr;
....@@ -1810,15 +1788,15 @@
18101788 	struct rtl_priv *rtlpriv = rtl_priv(hw);
18111789 	u32 rf, addr = EEPROM_TX_PWR_INX, group, i = 0;
18121790 
1813
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1814
-		 "hal_ReadPowerValueFromPROM92E(): PROMContent[0x%x]=0x%x\n",
1815
-		 (addr + 1), hwinfo[addr + 1]);
1791
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1792
+		"hal_ReadPowerValueFromPROM92E(): PROMContent[0x%x]=0x%x\n",
1793
+		(addr + 1), hwinfo[addr + 1]);
18161794 	if (0xFF == hwinfo[addr+1])  /*YJ,add,120316*/
18171795 		autoload_fail = true;
18181796 
18191797 	if (autoload_fail) {
1820
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1821
-			 "auto load fail : Use Default value!\n");
1798
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1799
+			"auto load fail : Use Default value!\n");
18221800 		for (rf = 0 ; rf < MAX_RF_PATH ; rf++) {
18231801 			/* 2.4G default value */
18241802 			for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
....@@ -2135,8 +2113,8 @@
21352113 	if (rtlefuse->eeprom_oemid == 0xFF)
21362114 		rtlefuse->eeprom_oemid = 0;
21372115 
2138
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2139
-		 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
2116
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2117
+		"EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
21402118 	/* set channel plan from efuse */
21412119 	rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
21422120 	/*tx power*/
....@@ -2156,8 +2134,8 @@
21562134 		rtlefuse->board_type |= BIT(2); /* ODM_BOARD_BT */
21572135 
21582136 	rtlhal->board_type = rtlefuse->board_type;
2159
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2160
-		 "board_type = 0x%x\n", rtlefuse->board_type);
2137
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2138
+		"board_type = 0x%x\n", rtlefuse->board_type);
21612139 	/*parse xtal*/
21622140 	rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_92E];
21632141 	if (hwinfo[EEPROM_XTAL_92E] == 0xFF)
....@@ -2194,8 +2172,8 @@
21942172 
21952173 	rtlpriv->ledctl.led_opendrain = true;
21962174 
2197
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2198
-		 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2175
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2176
+		"RT Customized ID: 0x%02X\n", rtlhal->oem_id);
21992177 }
22002178 
22012179 void rtl92ee_read_eeprom_info(struct ieee80211_hw *hw)
....@@ -2213,18 +2191,18 @@
22132191 		rtlpriv->dm.rfpath_rxenable[0] = true;
22142192 		rtlpriv->dm.rfpath_rxenable[1] = true;
22152193 	}
2216
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2217
-		 rtlhal->version);
2194
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2195
+		rtlhal->version);
22182196 	tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
22192197 	if (tmp_u1b & BIT(4)) {
2220
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2198
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
22212199 		rtlefuse->epromtype = EEPROM_93C46;
22222200 	} else {
2223
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2201
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
22242202 		rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
22252203 	}
22262204 	if (tmp_u1b & BIT(5)) {
2227
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2205
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
22282206 		rtlefuse->autoload_failflag = false;
22292207 		_rtl92ee_read_adapter_info(hw);
22302208 	} else {
....@@ -2383,8 +2361,8 @@
23832361 	ratr_index = _rtl92ee_mrate_idx_to_arfr_id(hw, ratr_index);
23842362 	sta_entry->ratr_index = ratr_index;
23852363 
2386
-	RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2387
-		 "ratr_bitmap :%x\n", ratr_bitmap);
2364
+	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2365
+		"ratr_bitmap :%x\n", ratr_bitmap);
23882366 	*(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
23892367 				       (ratr_index << 28);
23902368 	rate_mask[0] = macid;
....@@ -2394,11 +2372,11 @@
23942372 	rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
23952373 	rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
23962374 	rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2397
-	RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2398
-		 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2399
-		  ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1],
2400
-		  rate_mask[2], rate_mask[3], rate_mask[4],
2401
-		  rate_mask[5], rate_mask[6]);
2375
+	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2376
+		"Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2377
+		ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1],
2378
+		rate_mask[2], rate_mask[3], rate_mask[4],
2379
+		rate_mask[5], rate_mask[6]);
24022380 	rtl92ee_fill_h2c_cmd(hw, H2C_92E_RA_MASK, 7, rate_mask);
24032381 	_rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
24042382 }
....@@ -2460,7 +2438,7 @@
24602438 		u8 cam_offset = 0;
24612439 		u8 clear_number = 5;
24622440 
2463
-		RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2441
+		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
24642442 
24652443 		for (idx = 0; idx < clear_number; idx++) {
24662444 			rtl_cam_mark_invalid(hw, cam_offset + idx);
....@@ -2488,8 +2466,8 @@
24882466 			enc_algo = CAM_AES;
24892467 			break;
24902468 		default:
2491
-			RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
2492
-				 "switch case %#x not processed\n", enc_algo);
2469
+			rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,
2470
+				"switch case %#x not processed\n", enc_algo);
24932471 			enc_algo = CAM_TKIP;
24942472 			break;
24952473 		}
....@@ -2520,27 +2498,27 @@
25202498 		}
25212499 
25222500 		if (rtlpriv->sec.key_len[key_index] == 0) {
2523
-			RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2524
-				 "delete one entry, entry_id is %d\n",
2525
-				 entry_id);
2501
+			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2502
+				"delete one entry, entry_id is %d\n",
2503
+				entry_id);
25262504 			if (mac->opmode == NL80211_IFTYPE_AP ||
25272505 			    mac->opmode == NL80211_IFTYPE_MESH_POINT)
25282506 				rtl_cam_del_entry(hw, p_macaddr);
25292507 			rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
25302508 		} else {
2531
-			RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2532
-				 "add one entry\n");
2509
+			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2510
+				"add one entry\n");
25332511 			if (is_pairwise) {
2534
-				RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2535
-					 "set Pairwise key\n");
2512
+				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2513
+					"set Pairwise key\n");
25362514 
25372515 				rtl_cam_add_one_entry(hw, macaddr, key_index,
25382516 					       entry_id, enc_algo,
25392517 					       CAM_CONFIG_NO_USEDK,
25402518 					       rtlpriv->sec.key_buf[key_index]);
25412519 			} else {
2542
-				RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2543
-					 "set group key\n");
2520
+				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2521
+					"set group key\n");
25442522 
25452523 				if (mac->opmode == NL80211_IFTYPE_ADHOC) {
25462524 					rtl_cam_add_one_entry(hw,
....@@ -2625,7 +2603,7 @@
26252603 	if (write_into_reg)
26262604 		rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
26272605 
2628
-	RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2629
-		 "receive_config=0x%08X, write_into_reg=%d\n",
2630
-		  rtlpci->receive_config, write_into_reg);
2606
+	rtl_dbg(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2607
+		"receive_config=0x%08X, write_into_reg=%d\n",
2608
+		rtlpci->receive_config, write_into_reg);
26312609 }