forked from ~ljy/RK356X_SDK_RELEASE
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2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc 
 kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c
....@@ -1,27 +1,5 @@
1
-/******************************************************************************
2
- *
3
- * Copyright(c) 2009-2012  Realtek Corporation.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of version 2 of the GNU General Public License as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
14
- * The full GNU General Public License is included in this distribution in the
15
- * file called LICENSE.
16
- *
17
- * Contact Information:
18
- * wlanfae <wlanfae@realtek.com>
19
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20
- * Hsinchu 300, Taiwan.
21
- *
22
- * Larry Finger <Larry.Finger@lwfinger.net>
23
- *
24
- *****************************************************************************/
1
+// SPDX-License-Identifier: GPL-2.0
2
+/* Copyright(c) 2009-2012  Realtek Corporation.*/
253 
264 #include "../wifi.h"
275 #include "../pci.h"
....@@ -184,14 +162,9 @@
184162 
185163 static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask)
186164 {
187
-	u32 i;
165
+	u32 i = ffs(bitmask);
188166 
189
-	for (i = 0; i <= 31; i++) {
190
-		if (((bitmask >> i) & 0x1) == 1)
191
-			break;
192
-	}
193
-
194
-	return i;
167
+	return i ? i - 1 : 32;
195168 }
196169 
197170 u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
....@@ -200,8 +173,8 @@
200173 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
201174 	u32 returnvalue, originalvalue, bitshift;
202175 
203
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
204
-		 regaddr, bitmask);
176
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
177
+		regaddr, bitmask);
205178 	if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) {
206179 		u8 dbi_direct = 0;
207180 
....@@ -218,9 +191,9 @@
218191 	}
219192 	bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
220193 	returnvalue = (originalvalue & bitmask) >> bitshift;
221
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
222
-		 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
223
-		 bitmask, regaddr, originalvalue);
194
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
195
+		"BBR MASK=0x%x Addr[0x%x]=0x%x\n",
196
+		bitmask, regaddr, originalvalue);
224197 	return returnvalue;
225198 }
226199 
....@@ -232,9 +205,9 @@
232205 	u8 dbi_direct = 0;
233206 	u32 originalvalue, bitshift;
234207 
235
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
236
-		 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
237
-		 regaddr, bitmask, data);
208
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
209
+		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
210
+		regaddr, bitmask, data);
238211 	if (rtlhal->during_mac1init_radioa)
239212 		dbi_direct = BIT(3);
240213 	else if (rtlhal->during_mac0init_radiob)
....@@ -255,9 +228,9 @@
255228 		rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct);
256229 	else
257230 		rtl_write_dword(rtlpriv, regaddr, data);
258
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
259
-		 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
260
-		 regaddr, bitmask, data);
231
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
232
+		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
233
+		regaddr, bitmask, data);
261234 }
262235 
263236 static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
....@@ -301,8 +274,8 @@
301274 	else
302275 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
303276 			BLSSIREADBACKDATA);
304
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n",
305
-		 rfpath, pphyreg->rf_rb, retvalue);
277
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n",
278
+		rfpath, pphyreg->rf_rb, retvalue);
306279 	return retvalue;
307280 }
308281 
....@@ -320,8 +293,8 @@
320293 	/* T65 RF */
321294 	data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
322295 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
323
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
324
-		 rfpath, pphyreg->rf3wire_offset, data_and_addr);
296
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
297
+		rfpath, pphyreg->rf3wire_offset, data_and_addr);
325298 }
326299 
327300 u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
....@@ -329,19 +302,18 @@
329302 {
330303 	struct rtl_priv *rtlpriv = rtl_priv(hw);
331304 	u32 original_value, readback_value, bitshift;
332
-	unsigned long flags;
333305 
334
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
335
-		 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
336
-		 regaddr, rfpath, bitmask);
337
-	spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
306
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
307
+		"regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
308
+		regaddr, rfpath, bitmask);
309
+	spin_lock(&rtlpriv->locks.rf_lock);
338310 	original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);
339311 	bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
340312 	readback_value = (original_value & bitmask) >> bitshift;
341
-	spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
342
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
343
-		 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
344
-		 regaddr, rfpath, bitmask, original_value);
313
+	spin_unlock(&rtlpriv->locks.rf_lock);
314
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
315
+		"regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
316
+		regaddr, rfpath, bitmask, original_value);
345317 	return readback_value;
346318 }
347319 
....@@ -351,14 +323,13 @@
351323 	struct rtl_priv *rtlpriv = rtl_priv(hw);
352324 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
353325 	u32 original_value, bitshift;
354
-	unsigned long flags;
355326 
356
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
357
-		 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
358
-		 regaddr, bitmask, data, rfpath);
327
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
328
+		"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
329
+		regaddr, bitmask, data, rfpath);
359330 	if (bitmask == 0)
360331 		return;
361
-	spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
332
+	spin_lock(&rtlpriv->locks.rf_lock);
362333 	if (rtlphy->rf_mode != RF_OP_BY_FW) {
363334 		if (bitmask != RFREG_OFFSET_MASK) {
364335 			original_value = _rtl92d_phy_rf_serial_read(hw,
....@@ -369,10 +340,10 @@
369340 		}
370341 		_rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);
371342 	}
372
-	spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
373
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
374
-		 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
375
-		 regaddr, bitmask, data, rfpath);
343
+	spin_unlock(&rtlpriv->locks.rf_lock);
344
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
345
+		"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
346
+		regaddr, bitmask, data, rfpath);
376347 }
377348 
378349 bool rtl92d_phy_mac_config(struct ieee80211_hw *hw)
....@@ -382,10 +353,10 @@
382353 	u32 arraylength;
383354 	u32 *ptrarray;
384355 
385
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
356
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
386357 	arraylength = MAC_2T_ARRAYLENGTH;
387358 	ptrarray = rtl8192de_mac_2tarray;
388
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n");
359
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n");
389360 	for (i = 0; i < arraylength; i = i + 2)
390361 		rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
391362 	if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
....@@ -506,16 +477,16 @@
506477 	rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
507478 
508479 	/* Tx AFE control 1 */
509
-	rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATxIQIMBALANCE;
510
-	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTxIQIMBALANCE;
511
-	rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTxIQIMBALANCE;
512
-	rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTxIQIMBALANCE;
480
+	rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
481
+	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
482
+	rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
483
+	rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
513484 
514485 	/* Tx AFE control 2 */
515
-	rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATxAFE;
516
-	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE;
517
-	rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTxAFE;
518
-	rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE;
486
+	rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
487
+	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
488
+	rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
489
+	rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
519490 
520491 	/* Tranceiver LSSI Readback SI mode */
521492 	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
....@@ -543,36 +514,36 @@
543514 	if (rtlhal->interfaceindex == 0) {
544515 		agctab_arraylen = AGCTAB_ARRAYLENGTH;
545516 		agctab_array_table = rtl8192de_agctab_array;
546
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
547
-			 " ===> phy:MAC0, Rtl819XAGCTAB_Array\n");
517
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
518
+			" ===> phy:MAC0, Rtl819XAGCTAB_Array\n");
548519 	} else {
549520 		if (rtlhal->current_bandtype == BAND_ON_2_4G) {
550521 			agctab_arraylen = AGCTAB_2G_ARRAYLENGTH;
551522 			agctab_array_table = rtl8192de_agctab_2garray;
552
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
553
-				 " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n");
523
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
524
+				" ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n");
554525 		} else {
555526 			agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH;
556527 			agctab_5garray_table = rtl8192de_agctab_5garray;
557
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
558
-				 " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n");
528
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
529
+				" ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n");
559530 
560531 		}
561532 	}
562533 	phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH;
563534 	phy_regarray_table = rtl8192de_phy_reg_2tarray;
564
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
565
-		 " ===> phy:Rtl819XPHY_REG_Array_PG\n");
535
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
536
+		" ===> phy:Rtl819XPHY_REG_Array_PG\n");
566537 	if (configtype == BASEBAND_CONFIG_PHY_REG) {
567538 		for (i = 0; i < phy_reg_arraylen; i = i + 2) {
568539 			rtl_addr_delay(phy_regarray_table[i]);
569540 			rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
570541 				      phy_regarray_table[i + 1]);
571542 			udelay(1);
572
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
573
-				 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
574
-				 phy_regarray_table[i],
575
-				 phy_regarray_table[i + 1]);
543
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
544
+				"The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
545
+				phy_regarray_table[i],
546
+				phy_regarray_table[i + 1]);
576547 		}
577548 	} else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
578549 		if (rtlhal->interfaceindex == 0) {
....@@ -583,13 +554,13 @@
583554 				/* Add 1us delay between BB/RF register
584555 				 * setting. */
585556 				udelay(1);
586
-				RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
587
-					 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
588
-					 agctab_array_table[i],
589
-					 agctab_array_table[i + 1]);
557
+				rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
558
+					"The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
559
+					agctab_array_table[i],
560
+					agctab_array_table[i + 1]);
590561 			}
591
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
592
-				 "Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n");
562
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
563
+				"Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n");
593564 		} else {
594565 			if (rtlhal->current_bandtype == BAND_ON_2_4G) {
595566 				for (i = 0; i < agctab_arraylen; i = i + 2) {
....@@ -599,13 +570,13 @@
599570 					/* Add 1us delay between BB/RF register
600571 					 * setting. */
601572 					udelay(1);
602
-					RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
603
-						 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
604
-						 agctab_array_table[i],
605
-						 agctab_array_table[i + 1]);
573
+					rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
574
+						"The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
575
+						agctab_array_table[i],
576
+						agctab_array_table[i + 1]);
606577 				}
607
-				RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
608
-					 "Load Rtl819XAGCTAB_2GArray\n");
578
+				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
579
+					"Load Rtl819XAGCTAB_2GArray\n");
609580 			} else {
610581 				for (i = 0; i < agctab_5garraylen; i = i + 2) {
611582 					rtl_set_bbreg(hw,
....@@ -615,13 +586,13 @@
615586 					/* Add 1us delay between BB/RF registeri
616587 					 * setting. */
617588 					udelay(1);
618
-					RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
619
-						 "The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
620
-						 agctab_5garray_table[i],
621
-						 agctab_5garray_table[i + 1]);
589
+					rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
590
+						"The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
591
+						agctab_5garray_table[i],
592
+						agctab_5garray_table[i + 1]);
622593 				}
623
-				RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
624
-					 "Load Rtl819XAGCTAB_5GArray\n");
594
+				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
595
+					"Load Rtl819XAGCTAB_5GArray\n");
625596 			}
626597 		}
627598 	}
....@@ -672,10 +643,10 @@
672643 		return;
673644 
674645 	rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
675
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
676
-		 "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
677
-		 rtlphy->pwrgroup_cnt, index,
678
-		 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]);
646
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
647
+		"MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
648
+		rtlphy->pwrgroup_cnt, index,
649
+		rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]);
679650 	if (index == 13)
680651 		rtlphy->pwrgroup_cnt++;
681652 }
....@@ -699,8 +670,8 @@
699670 				phy_regarray_table_pg[i + 2]);
700671 		}
701672 	} else {
702
-		RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
703
-			 "configtype != BaseBand_Config_PHY_REG\n");
673
+		rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,
674
+			"configtype != BaseBand_Config_PHY_REG\n");
704675 	}
705676 	return true;
706677 }
....@@ -712,7 +683,7 @@
712683 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
713684 	bool rtstatus = true;
714685 
715
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
686
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
716687 	rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
717688 		BASEBAND_CONFIG_PHY_REG);
718689 	if (!rtstatus) {
....@@ -722,7 +693,7 @@
722693 
723694 	/* if (rtlphy->rf_type == RF_1T2R) {
724695 	 *      _rtl92c_phy_bb_config_1t(hw);
725
-	 *     RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
696
+	 *     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
726697 	 *} */
727698 
728699 	if (rtlefuse->autoload_failflag == false) {
....@@ -764,7 +735,7 @@
764735 	rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
765736 		RF_SDMRSTB);
766737 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
767
-		FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
738
+		FEN_DIO_PCIE | FEN_BB_GLB_RSTN | FEN_BBRSTB);
768739 	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
769740 	if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
770741 		regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
....@@ -801,18 +772,18 @@
801772 		radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH;
802773 		radiob_array_table = rtl8192de_radiob_2t_int_paarray;
803774 	}
804
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
805
-		 "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n");
806
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
807
-		 "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n");
808
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
775
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
776
+		"PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n");
777
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
778
+		"PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n");
779
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
809780 
810781 	/* this only happens when DMDP, mac0 start on 2.4G,
811782 	 * mac1 start on 5G, mac 0 has to set phy0&phy1
812783 	 * pathA or mac1 has to set phy0&phy1 pathA */
813784 	if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) {
814
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
815
-			 " ===> althougth Path A, we load radiob.txt\n");
785
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
786
+			" ===> althougth Path A, we load radiob.txt\n");
816787 		radioa_arraylen = radiob_arraylen;
817788 		radioa_array_table = radiob_array_table;
818789 	}
....@@ -852,19 +823,19 @@
852823 	    (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
853824 	rtlphy->default_initialgain[3] =
854825 	    (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
855
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
856
-		 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
857
-		 rtlphy->default_initialgain[0],
858
-		 rtlphy->default_initialgain[1],
859
-		 rtlphy->default_initialgain[2],
860
-		 rtlphy->default_initialgain[3]);
826
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
827
+		"Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
828
+		rtlphy->default_initialgain[0],
829
+		rtlphy->default_initialgain[1],
830
+		rtlphy->default_initialgain[2],
831
+		rtlphy->default_initialgain[3]);
861832 	rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
862833 					      MASKBYTE0);
863834 	rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
864835 					      MASKDWORD);
865
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
866
-		 "Default framesync (0x%x) = 0x%x\n",
867
-		 ROFDM0_RXDETECTOR3, rtlphy->framesync);
836
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
837
+		"Default framesync (0x%x) = 0x%x\n",
838
+		ROFDM0_RXDETECTOR3, rtlphy->framesync);
868839 }
869840 
870841 static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
....@@ -962,14 +933,14 @@
962933 	if (rtlphy->set_bwmode_inprogress)
963934 		return;
964935 	if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
965
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
966
-			 "FALSE driver sleep or unload\n");
936
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
937
+			"FALSE driver sleep or unload\n");
967938 		return;
968939 	}
969940 	rtlphy->set_bwmode_inprogress = true;
970
-	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
971
-		 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
972
-		 "20MHz" : "40MHz");
941
+	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
942
+		rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
943
+		"20MHz" : "40MHz");
973944 	reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
974945 	reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
975946 	switch (rtlphy->current_chan_bw) {
....@@ -1025,7 +996,7 @@
1025996 	}
1026997 	rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1027998 	rtlphy->set_bwmode_inprogress = false;
1028
-	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
999
+	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
10291000 }
10301001 
10311002 static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
....@@ -1042,7 +1013,7 @@
10421013 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
10431014 	u8 value8;
10441015 
1045
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
1016
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
10461017 	rtlhal->bandset = band;
10471018 	rtlhal->current_bandtype = band;
10481019 	if (IS_92D_SINGLEPHY(rtlhal->version))
....@@ -1052,13 +1023,13 @@
10521023 	/* reconfig BB/RF according to wireless mode */
10531024 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
10541025 		/* BB & RF Config */
1055
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n");
1026
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n");
10561027 		if (rtlhal->interfaceindex == 1)
10571028 			_rtl92d_phy_config_bb_with_headerfile(hw,
10581029 				BASEBAND_CONFIG_AGC_TAB);
10591030 	} else {
10601031 		/* 5G band */
1061
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n");
1032
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n");
10621033 		if (rtlhal->interfaceindex == 1)
10631034 			_rtl92d_phy_config_bb_with_headerfile(hw,
10641035 				BASEBAND_CONFIG_AGC_TAB);
....@@ -1086,7 +1057,7 @@
10861057 			0 ? REG_MAC0 : REG_MAC1), value8);
10871058 	}
10881059 	mdelay(1);
1089
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n");
1060
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n");
10901061 }
10911062 
10921063 static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
....@@ -1098,9 +1069,9 @@
10981069 	u8 group, i;
10991070 	unsigned long flag = 0;
11001071 
1101
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath);
1072
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath);
11021073 	if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
1103
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1074
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
11041075 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
11051076 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
11061077 		/* fc area 0xd2c */
....@@ -1121,14 +1092,14 @@
11211092 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1);
11221093 	} else {
11231094 		/* G band. */
1124
-		RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1125
-			 "Load RF IMR parameters for G band. IMR already setting %d\n",
1126
-			 rtlpriv->rtlhal.load_imrandiqk_setting_for2g);
1127
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1095
+		rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
1096
+			"Load RF IMR parameters for G band. IMR already setting %d\n",
1097
+			rtlpriv->rtlhal.load_imrandiqk_setting_for2g);
1098
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
11281099 		if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) {
1129
-			RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1130
-				 "Load RF IMR parameters for G band. %d\n",
1131
-				 rfpath);
1100
+			rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
1101
+				"Load RF IMR parameters for G band. %d\n",
1102
+				rfpath);
11321103 			rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
11331104 			rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
11341105 			rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
....@@ -1146,7 +1117,7 @@
11461117 			rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
11471118 		}
11481119 	}
1149
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1120
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
11501121 }
11511122 
11521123 static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw,
....@@ -1156,7 +1127,7 @@
11561127 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
11571128 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
11581129 
1159
-	RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "====>\n");
1130
+	rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "====>\n");
11601131 	/*----Store original RFENV control type----*/
11611132 	switch (rfpath) {
11621133 	case RF90_PATH_A:
....@@ -1182,7 +1153,7 @@
11821153 	/*Set 0 to 12 bits for 8255 */
11831154 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
11841155 	udelay(1);
1185
-	RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<====\n");
1156
+	rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<====\n");
11861157 }
11871158 
11881159 static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath,
....@@ -1192,7 +1163,7 @@
11921163 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
11931164 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
11941165 
1195
-	RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n");
1166
+	rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n");
11961167 	/*----Restore RFENV control type----*/
11971168 	switch (rfpath) {
11981169 	case RF90_PATH_A:
....@@ -1205,7 +1176,7 @@
12051176 			      *pu4_regval);
12061177 		break;
12071178 	}
1208
-	RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n");
1179
+	rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n");
12091180 }
12101181 
12111182 static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
....@@ -1219,10 +1190,10 @@
12191190 	bool need_pwr_down = false, internal_pa = false;
12201191 	u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2;
12211192 
1222
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n");
1193
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n");
12231194 	/* config path A for 5G */
12241195 	if (rtlhal->current_bandtype == BAND_ON_5G) {
1225
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1196
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
12261197 		u4tmp = curveindex_5g[channel - 1];
12271198 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
12281199 			"ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
....@@ -1270,14 +1241,14 @@
12701241 					      RFREG_OFFSET_MASK,
12711242 					      rf_reg_pram_c_5g[index][i]);
12721243 			}
1273
-			RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1274
-				 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n",
1275
-				 rf_reg_for_c_cut_5g[i],
1276
-				 rf_reg_pram_c_5g[index][i],
1277
-				 path, index,
1278
-				 rtl_get_rfreg(hw, (enum radio_path)path,
1279
-					       rf_reg_for_c_cut_5g[i],
1280
-					       RFREG_OFFSET_MASK));
1244
+			rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
1245
+				"offset 0x%x value 0x%x path %d index %d readback 0x%x\n",
1246
+				rf_reg_for_c_cut_5g[i],
1247
+				rf_reg_pram_c_5g[index][i],
1248
+				path, index,
1249
+				rtl_get_rfreg(hw, (enum radio_path)path,
1250
+					      rf_reg_for_c_cut_5g[i],
1251
+					      RFREG_OFFSET_MASK));
12811252 		}
12821253 		if (need_pwr_down)
12831254 			_rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
....@@ -1309,11 +1280,11 @@
13091280 						rf_for_c_cut_5g_internal_pa[i],
13101281 						RFREG_OFFSET_MASK,
13111282 						rf_pram_c_5g_int_pa[index][i]);
1312
-					RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
1313
-						 "offset 0x%x value 0x%x path %d index %d\n",
1314
-						 rf_for_c_cut_5g_internal_pa[i],
1315
-						 rf_pram_c_5g_int_pa[index][i],
1316
-						 rfpath, index);
1283
+					rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
1284
+						"offset 0x%x value 0x%x path %d index %d\n",
1285
+						rf_for_c_cut_5g_internal_pa[i],
1286
+						rf_pram_c_5g_int_pa[index][i],
1287
+						rfpath, index);
13171288 				}
13181289 			} else {
13191290 				rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
....@@ -1321,7 +1292,7 @@
13211292 			}
13221293 		}
13231294 	} else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1324
-		RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1295
+		rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
13251296 		u4tmp = curveindex_2g[channel - 1];
13261297 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
13271298 			"ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
....@@ -1357,14 +1328,14 @@
13571328 					      RFREG_OFFSET_MASK,
13581329 					      rf_reg_param_for_c_cut_2g
13591330 					      [index][i]);
1360
-			RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1361
-				 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n",
1362
-				 rf_reg_for_c_cut_2g[i],
1363
-				 rf_reg_param_for_c_cut_2g[index][i],
1364
-				 rf_reg_mask_for_c_cut_2g[i], path, index,
1365
-				 rtl_get_rfreg(hw, (enum radio_path)path,
1366
-					       rf_reg_for_c_cut_2g[i],
1367
-					       RFREG_OFFSET_MASK));
1331
+			rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
1332
+				"offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n",
1333
+				rf_reg_for_c_cut_2g[i],
1334
+				rf_reg_param_for_c_cut_2g[index][i],
1335
+				rf_reg_mask_for_c_cut_2g[i], path, index,
1336
+				rtl_get_rfreg(hw, (enum radio_path)path,
1337
+					      rf_reg_for_c_cut_2g[i],
1338
+					      RFREG_OFFSET_MASK));
13681339 		}
13691340 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
13701341 			"cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
....@@ -1378,7 +1349,7 @@
13781349 		if (rtlhal->during_mac0init_radiob)
13791350 			rtl92d_phy_powerdown_anotherphy(hw, true);
13801351 	}
1381
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1352
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
13821353 }
13831354 
13841355 u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl)
....@@ -1480,11 +1451,11 @@
14801451 	u8 result = 0;
14811452 	u8 i;
14821453 	u8 retrycount = 2;
1483
-	u32 TxOKBit = BIT(28), RxOKBit = BIT(27);
1454
+	u32 TXOKBIT = BIT(28), RXOKBIT = BIT(27);
14841455 
14851456 	if (rtlhal->interfaceindex == 1) {	/* PHY1 */
1486
-		TxOKBit = BIT(31);
1487
-		RxOKBit = BIT(30);
1457
+		TXOKBIT = BIT(31);
1458
+		RXOKBIT = BIT(30);
14881459 	}
14891460 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK!\n");
14901461 	/* path-A IQK setting */
....@@ -1526,7 +1497,7 @@
15261497 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe9c = 0x%x\n", rege9c);
15271498 		regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
15281499 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xea4 = 0x%x\n", regea4);
1529
-		if (!(regeac & TxOKBit) &&
1500
+		if (!(regeac & TXOKBIT) &&
15301501 		     (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
15311502 			result |= 0x01;
15321503 		} else { /* if Tx not OK, ignore Rx */
....@@ -1536,7 +1507,7 @@
15361507 		}
15371508 
15381509 		/* if Tx is OK, check whether Rx is OK */
1539
-		if (!(regeac & RxOKBit) &&
1510
+		if (!(regeac & RXOKBIT) &&
15401511 		    (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
15411512 			result |= 0x02;
15421513 			break;
....@@ -2165,7 +2136,7 @@
21652136 	if (final_candidate == 0xFF) {
21662137 		return;
21672138 	} else if (iqk_ok) {
2168
-		oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2139
+		oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
21692140 			MASKDWORD) >> 22) & 0x3FF;	/* OFDM0_D */
21702141 		val_x = result[final_candidate][0];
21712142 		if ((val_x & 0x00000200) != 0)
....@@ -2174,7 +2145,7 @@
21742145 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
21752146 			"X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n",
21762147 			val_x, tx0_a, oldval_0);
2177
-		rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a);
2148
+		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
21782149 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
21792150 			      ((val_x * oldval_0 >> 7) & 0x1));
21802151 		val_y = result[final_candidate][1];
....@@ -2188,15 +2159,15 @@
21882159 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
21892160 			"Y = 0x%lx, tx0_c = 0x%lx\n",
21902161 			val_y, tx0_c);
2191
-		rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000,
2162
+		rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
21922163 			      ((tx0_c & 0x3C0) >> 6));
2193
-		rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000,
2164
+		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
21942165 			      (tx0_c & 0x3F));
21952166 		if (is2t)
21962167 			rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
21972168 				      ((val_y * oldval_0 >> 7) & 0x1));
21982169 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
2199
-			rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2170
+			rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
22002171 				      MASKDWORD));
22012172 		if (txonly) {
22022173 			RTPRINT(rtlpriv, FINIT, INIT_IQK,  "only Tx OK\n");
....@@ -2224,7 +2195,7 @@
22242195 	if (final_candidate == 0xFF) {
22252196 		return;
22262197 	} else if (iqk_ok) {
2227
-		oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
2198
+		oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
22282199 					  MASKDWORD) >> 22) & 0x3FF;
22292200 		val_x = result[final_candidate][4];
22302201 		if ((val_x & 0x00000200) != 0)
....@@ -2232,7 +2203,7 @@
22322203 		tx1_a = (val_x * oldval_1) >> 8;
22332204 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n",
22342205 			val_x, tx1_a);
2235
-		rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a);
2206
+		rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
22362207 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
22372208 			      ((val_x * oldval_1 >> 7) & 0x1));
22382209 		val_y = result[final_candidate][5];
....@@ -2243,9 +2214,9 @@
22432214 		tx1_c = (val_y * oldval_1) >> 8;
22442215 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n",
22452216 			val_y, tx1_c);
2246
-		rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000,
2217
+		rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
22472218 			      ((tx1_c & 0x3C0) >> 6));
2248
-		rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000,
2219
+		rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
22492220 			      (tx1_c & 0x3F));
22502221 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
22512222 			      ((val_y * oldval_1 >> 7) & 0x1));
....@@ -2382,8 +2353,8 @@
23822353 		rtlphy->iqk_matrix[indexforchannel].iqk_done =
23832354 			true;
23842355 
2385
-		RT_TRACE(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD,
2386
-			 "IQK OK indexforchannel %d\n", indexforchannel);
2356
+		rtl_dbg(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD,
2357
+			"IQK OK indexforchannel %d\n", indexforchannel);
23872358 	}
23882359 }
23892360 
....@@ -2394,34 +2365,30 @@
23942365 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
23952366 	u8 indexforchannel;
23962367 
2397
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel);
2368
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel);
23982369 	/*------Do IQK for normal chip and test chip 5G band------- */
23992370 	indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
2400
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n",
2401
-		 indexforchannel,
2371
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n",
2372
+		indexforchannel,
24022373 		 rtlphy->iqk_matrix[indexforchannel].iqk_done);
24032374 	if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done &&
24042375 		rtlphy->need_iqk) {
24052376 		/* Re Do IQK. */
2406
-		RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD,
2407
-			 "Do IQK Matrix reg for channel:%d....\n", channel);
2377
+		rtl_dbg(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD,
2378
+			"Do IQK Matrix reg for channel:%d....\n", channel);
24082379 		rtl92d_phy_iq_calibrate(hw);
24092380 	} else {
24102381 		/* Just load the value. */
24112382 		/* 2G band just load once. */
24122383 		if (((!rtlhal->load_imrandiqk_setting_for2g) &&
24132384 		    indexforchannel == 0) || indexforchannel > 0) {
2414
-			RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
2415
-				 "Just Read IQK Matrix reg for channel:%d....\n",
2416
-				 channel);
2417
-			if ((rtlphy->iqk_matrix[indexforchannel].
2418
-			     value[0] != NULL)
2419
-				/*&&(regea4 != 0) */)
2385
+			rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
2386
+				"Just Read IQK Matrix reg for channel:%d....\n",
2387
+				channel);
2388
+			if (rtlphy->iqk_matrix[indexforchannel].value[0][0] != 0)
24202389 				_rtl92d_phy_patha_fill_iqk_matrix(hw, true,
2421
-					rtlphy->iqk_matrix[
2422
-					indexforchannel].value,	0,
2423
-					(rtlphy->iqk_matrix[
2424
-					indexforchannel].value[0][2] == 0));
2390
+					rtlphy->iqk_matrix[indexforchannel].value, 0,
2391
+					rtlphy->iqk_matrix[indexforchannel].value[0][2] == 0);
24252392 			if (IS_92D_SINGLEPHY(rtlhal->version)) {
24262393 				if ((rtlphy->iqk_matrix[
24272394 					indexforchannel].value[0][4] != 0)
....@@ -2437,7 +2404,7 @@
24372404 		}
24382405 	}
24392406 	rtlphy->need_iqk = false;
2440
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2407
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
24412408 }
24422409 
24432410 static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2)
....@@ -2501,7 +2468,7 @@
25012468 	u32 u4tmp = 0, u4regvalue = 0;
25022469 	bool bneed_powerdown_radio = false;
25032470 
2504
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath);
2471
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath);
25052472 	RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n",
25062473 		rtlpriv->rtlhal.current_bandtype);
25072474 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "channel = %d\n", channel);
....@@ -2546,7 +2513,7 @@
25462513 		if (rtlpriv->rtlhal.during_mac0init_radiob)
25472514 			rtl92d_phy_powerdown_anotherphy(hw, true);
25482515 	}
2549
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2516
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
25502517 }
25512518 
25522519 static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
....@@ -2719,11 +2686,11 @@
27192686 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
27202687 	u8 i;
27212688 
2722
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2723
-		 "settings regs %d default regs %d\n",
2724
-		 (int)(sizeof(rtlphy->iqk_matrix) /
2725
-		       sizeof(struct iqk_matrix_regs)),
2726
-		 IQK_MATRIX_REG_NUM);
2689
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2690
+		"settings regs %d default regs %d\n",
2691
+		(int)(sizeof(rtlphy->iqk_matrix) /
2692
+		      sizeof(struct iqk_matrix_regs)),
2693
+		IQK_MATRIX_REG_NUM);
27272694 	/* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
27282695 	for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
27292696 		rtlphy->iqk_matrix[i].value[0][0] = 0x100;
....@@ -2868,8 +2835,8 @@
28682835 		return 0;
28692836 
28702837 	if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
2871
-		RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
2872
-			 "sw_chnl_inprogress false driver sleep or unload\n");
2838
+		rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
2839
+			"sw_chnl_inprogress false driver sleep or unload\n");
28732840 		return 0;
28742841 	}
28752842 	while (rtlphy->lck_inprogress && timecount < timeout) {
....@@ -2910,8 +2877,8 @@
29102877 		channel = 1;
29112878 	rtlphy->sw_chnl_stage = 0;
29122879 	rtlphy->sw_chnl_step = 0;
2913
-	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
2914
-		 "switch to channel%d\n", rtlphy->current_channel);
2880
+	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
2881
+		"switch to channel%d\n", rtlphy->current_channel);
29152882 
29162883 	do {
29172884 		if (!rtlphy->sw_chnl_inprogress)
....@@ -2928,7 +2895,7 @@
29282895 		}
29292896 		break;
29302897 	} while (true);
2931
-	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
2898
+	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
29322899 	rtlphy->sw_chnl_inprogress = false;
29332900 	return 1;
29342901 }
....@@ -2939,9 +2906,9 @@
29392906 	struct dig_t *de_digtable = &rtlpriv->dm_digtable;
29402907 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
29412908 
2942
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2943
-		 "--->Cmd(%#x), set_io_inprogress(%d)\n",
2944
-		 rtlphy->current_io_type, rtlphy->set_io_inprogress);
2909
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2910
+		"--->Cmd(%#x), set_io_inprogress(%d)\n",
2911
+		rtlphy->current_io_type, rtlphy->set_io_inprogress);
29452912 	switch (rtlphy->current_io_type) {
29462913 	case IO_CMD_RESUME_DM_BY_SCAN:
29472914 		de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
....@@ -2959,8 +2926,8 @@
29592926 		break;
29602927 	}
29612928 	rtlphy->set_io_inprogress = false;
2962
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n",
2963
-		 rtlphy->current_io_type);
2929
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n",
2930
+		rtlphy->current_io_type);
29642931 }
29652932 
29662933 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
....@@ -2969,19 +2936,19 @@
29692936 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
29702937 	bool postprocessing = false;
29712938 
2972
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2973
-		 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2939
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2940
+		"-->IO Cmd(%#x), set_io_inprogress(%d)\n",
29742941 		 iotype, rtlphy->set_io_inprogress);
29752942 	do {
29762943 		switch (iotype) {
29772944 		case IO_CMD_RESUME_DM_BY_SCAN:
2978
-			RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2979
-				 "[IO CMD] Resume DM after scan\n");
2945
+			rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2946
+				"[IO CMD] Resume DM after scan\n");
29802947 			postprocessing = true;
29812948 			break;
29822949 		case IO_CMD_PAUSE_DM_BY_SCAN:
2983
-			RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2984
-				 "[IO CMD] Pause DM before scan\n");
2950
+			rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2951
+				"[IO CMD] Pause DM before scan\n");
29852952 			postprocessing = true;
29862953 			break;
29872954 		default:
....@@ -2997,7 +2964,7 @@
29972964 		return false;
29982965 	}
29992966 	rtl92d_phy_set_io(hw);
3000
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
2967
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
30012968 	return true;
30022969 }
30032970 
....@@ -3054,8 +3021,8 @@
30543021 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
30553022 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
30563023 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3057
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3058
-			 "Fail !!! Switch RF timeout\n");
3024
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
3025
+			"Fail !!! Switch RF timeout\n");
30593026 		return;
30603027 	}
30613028 	/* e.   For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */
....@@ -3086,21 +3053,21 @@
30863053 		if ((ppsc->rfpwr_state == ERFOFF) &&
30873054 		    RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
30883055 			bool rtstatus;
3089
-			u32 InitializeCount = 0;
3056
+			u32 initializecount = 0;
30903057 			do {
3091
-				InitializeCount++;
3092
-				RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3093
-					 "IPS Set eRf nic enable\n");
3058
+				initializecount++;
3059
+				rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3060
+					"IPS Set eRf nic enable\n");
30943061 				rtstatus = rtl_ps_enable_nic(hw);
3095
-			} while (!rtstatus && (InitializeCount < 10));
3062
+			} while (!rtstatus && (initializecount < 10));
30963063 
30973064 			RT_CLEAR_PS_LEVEL(ppsc,
30983065 					  RT_RF_OFF_LEVL_HALT_NIC);
30993066 		} else {
3100
-			RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3101
-				 "awake, sleeped:%d ms state_inap:%x\n",
3102
-				 jiffies_to_msecs(jiffies -
3103
-						  ppsc->last_sleep_jiffies),
3067
+			rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
3068
+				"awake, slept:%d ms state_inap:%x\n",
3069
+				jiffies_to_msecs(jiffies -
3070
+						 ppsc->last_sleep_jiffies),
31043071 				 rtlpriv->psc.state_inap);
31053072 			ppsc->last_awake_jiffies = jiffies;
31063073 			_rtl92d_phy_set_rfon(hw);
....@@ -3115,8 +3082,8 @@
31153082 		break;
31163083 	case ERFOFF:
31173084 		if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3118
-			RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3119
-				 "IPS Set eRf nic disable\n");
3085
+			rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3086
+				"IPS Set eRf nic disable\n");
31203087 			rtl_ps_disable_nic(hw);
31213088 			RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
31223089 		} else {
....@@ -3140,35 +3107,35 @@
31403107 				queue_id++;
31413108 				continue;
31423109 			} else if (rtlpci->pdev->current_state != PCI_D0) {
3143
-				RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3144
-					 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n",
3145
-					 i + 1, queue_id);
3110
+				rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
3111
+					"eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n",
3112
+					i + 1, queue_id);
31463113 				break;
31473114 			} else {
3148
-				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3149
-					 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3150
-					 i + 1, queue_id,
3151
-					 skb_queue_len(&ring->queue));
3115
+				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3116
+					"eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3117
+					i + 1, queue_id,
3118
+					skb_queue_len(&ring->queue));
31523119 				udelay(10);
31533120 				i++;
31543121 			}
31553122 
31563123 			if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3157
-				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3158
-					 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
3159
-					 MAX_DOZE_WAITING_TIMES_9x, queue_id,
3160
-					 skb_queue_len(&ring->queue));
3124
+				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3125
+					"ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
3126
+					MAX_DOZE_WAITING_TIMES_9x, queue_id,
3127
+					skb_queue_len(&ring->queue));
31613128 				break;
31623129 			}
31633130 		}
3164
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3165
-			 "Set rfsleep awaked:%d ms\n",
3131
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
3132
+			"Set rfsleep awakened:%d ms\n",
31663133 			 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
3167
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3168
-			 "sleep awaked:%d ms state_inap:%x\n",
3169
-			 jiffies_to_msecs(jiffies -
3170
-					  ppsc->last_awake_jiffies),
3171
-			 rtlpriv->psc.state_inap);
3134
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
3135
+			"sleep awakened:%d ms state_inap:%x\n",
3136
+			jiffies_to_msecs(jiffies -
3137
+					 ppsc->last_awake_jiffies),
3138
+			rtlpriv->psc.state_inap);
31723139 		ppsc->last_sleep_jiffies = jiffies;
31733140 		_rtl92d_phy_set_rfsleep(hw);
31743141 		break;
....@@ -3191,18 +3158,18 @@
31913158 
31923159 	switch (rtlhal->macphymode) {
31933160 	case DUALMAC_DUALPHY:
3194
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3195
-			 "MacPhyMode: DUALMAC_DUALPHY\n");
3161
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3162
+			"MacPhyMode: DUALMAC_DUALPHY\n");
31963163 		rtl_write_byte(rtlpriv, offset, 0xF3);
31973164 		break;
31983165 	case SINGLEMAC_SINGLEPHY:
3199
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3200
-			 "MacPhyMode: SINGLEMAC_SINGLEPHY\n");
3166
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3167
+			"MacPhyMode: SINGLEMAC_SINGLEPHY\n");
32013168 		rtl_write_byte(rtlpriv, offset, 0xF4);
32023169 		break;
32033170 	case DUALMAC_SINGLEPHY:
3204
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3205
-			 "MacPhyMode: DUALMAC_SINGLEPHY\n");
3171
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3172
+			"MacPhyMode: DUALMAC_SINGLEPHY\n");
32063173 		rtl_write_byte(rtlpriv, offset, 0xF1);
32073174 		break;
32083175 	}
....@@ -3370,7 +3337,7 @@
33703337 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
33713338 	u8 rfpath, i;
33723339 
3373
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
3340
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
33743341 	/* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */
33753342 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
33763343 		/* r_select_5G for path_A/B,0x878 */
....@@ -3387,9 +3354,9 @@
33873354 		/* 5G LAN ON */
33883355 		rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
33893356 		/* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3390
-		rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3357
+		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
33913358 			      0x40000100);
3392
-		rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3359
+		rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
33933360 			      0x40000100);
33943361 		if (rtlhal->macphymode == DUALMAC_DUALPHY) {
33953362 			rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
....@@ -3443,16 +3410,16 @@
34433410 		rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
34443411 		/* TX BB gain shift,Just for testchip,0xc80,0xc88 */
34453412 		if (rtlefuse->internal_pa_5g[0])
3446
-			rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3413
+			rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
34473414 				      0x2d4000b5);
34483415 		else
3449
-			rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3416
+			rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
34503417 				      0x20000080);
34513418 		if (rtlefuse->internal_pa_5g[1])
3452
-			rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3419
+			rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
34533420 				      0x2d4000b5);
34543421 		else
3455
-			rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3422
+			rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
34563423 				      0x20000080);
34573424 		if (rtlhal->macphymode == DUALMAC_DUALPHY) {
34583425 			rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
....@@ -3481,10 +3448,10 @@
34813448 	/* update IQK related settings */
34823449 	rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
34833450 	rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
3484
-	rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00);
3451
+	rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00);
34853452 	rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
34863453 		      BIT(26) | BIT(24), 0x00);
3487
-	rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 0x00);
3454
+	rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00);
34883455 	rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
34893456 	rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
34903457 
....@@ -3518,8 +3485,8 @@
35183485 				      BIT(13), 0x3);
35193486 		} else {
35203487 			rtl92d_phy_enable_anotherphy(hw, false);
3521
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3522
-				 "MAC1 use DBI to update 0x888\n");
3488
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3489
+				"MAC1 use DBI to update 0x888\n");
35233490 			/* 0x888 */
35243491 			rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN,
35253492 						rtl92de_read_dword_dbi(hw,
....@@ -3544,9 +3511,9 @@
35443511 			RFREG_OFFSET_MASK);
35453512 	}
35463513 	for (i = 0; i < 2; i++)
3547
-		RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n",
3548
-			 rtlphy->rfreg_chnlval[i]);
3549
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n");
3514
+		rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n",
3515
+			rtlphy->rfreg_chnlval[i]);
3516
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n");
35503517 
35513518 }
35523519