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2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc 
 kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h
....@@ -1,27 +1,5 @@
1
-/******************************************************************************
2
- *
3
- * Copyright(c) 2009-2012  Realtek Corporation.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of version 2 of the GNU General Public License as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
14
- * The full GNU General Public License is included in this distribution in the
15
- * file called LICENSE.
16
- *
17
- * Contact Information:
18
- * wlanfae <wlanfae@realtek.com>
19
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20
- * Hsinchu 300, Taiwan.
21
- *
22
- * Larry Finger <Larry.Finger@lwfinger.net>
23
- *
24
- *****************************************************************************/
1
+/* SPDX-License-Identifier: GPL-2.0 */
2
+/* Copyright(c) 2009-2012  Realtek Corporation.*/
253 
264 #ifndef __RTL92CE_TRX_H__
275 #define __RTL92CE_TRX_H__
....@@ -36,497 +14,322 @@
3614 #define USB_HWDESC_HEADER_LEN			32
3715 #define CRCLENGTH				4
3816 
39
-/* Define a macro that takes a le32 word, converts it to host ordering,
40
- * right shifts by a specified count, creates a mask of the specified
41
- * bit count, and extracts that number of bits.
42
- */
43
-
44
-#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask)		\
45
-	((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) &	\
46
-	BIT_LEN_MASK_32(__mask))
47
-
48
-/* Define a macro that clears a bit field in an le32 word and
49
- * sets the specified value into that bit field. The resulting
50
- * value remains in le32 ordering; however, it is properly converted
51
- * to host ordering for the clear and set operations before conversion
52
- * back to le32.
53
- */
54
-
55
-#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val)	\
56
-	(*(__le32 *)(__pdesc) = 				\
57
-	(cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) &	\
58
-	(~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) |		\
59
-	(((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
60
-
6117 /* macros to read/write various fields in RX or TX descriptors */
6218 
63
-#define SET_TX_DESC_PKT_SIZE(__pdesc, __val)		\
64
-	SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
65
-#define SET_TX_DESC_OFFSET(__pdesc, __val)		\
66
-	SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
67
-#define SET_TX_DESC_BMC(__pdesc, __val)			\
68
-	SET_BITS_OFFSET_LE(__pdesc, 24, 1, __val)
69
-#define SET_TX_DESC_HTC(__pdesc, __val)			\
70
-	SET_BITS_OFFSET_LE(__pdesc, 25, 1, __val)
71
-#define SET_TX_DESC_LAST_SEG(__pdesc, __val)		\
72
-	SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
73
-#define SET_TX_DESC_FIRST_SEG(__pdesc, __val)		\
74
-	SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
75
-#define SET_TX_DESC_LINIP(__pdesc, __val)		\
76
-	SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
77
-#define SET_TX_DESC_NO_ACM(__pdesc, __val)		\
78
-	SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
79
-#define SET_TX_DESC_GF(__pdesc, __val)			\
80
-	SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
81
-#define SET_TX_DESC_OWN(__pdesc, __val)			\
82
-	SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
19
+static inline void set_tx_desc_pkt_size(__le32 *__pdesc, u32  __val)
20
+{
21
+	le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));
22
+}
8323 
84
-#define GET_TX_DESC_PKT_SIZE(__pdesc)			\
85
-	SHIFT_AND_MASK_LE(__pdesc, 0, 16)
86
-#define GET_TX_DESC_OFFSET(__pdesc)			\
87
-	SHIFT_AND_MASK_LE(__pdesc, 16, 8)
88
-#define GET_TX_DESC_BMC(__pdesc)			\
89
-	SHIFT_AND_MASK_LE(__pdesc, 24, 1)
90
-#define GET_TX_DESC_HTC(__pdesc)			\
91
-	SHIFT_AND_MASK_LE(__pdesc, 25, 1)
92
-#define GET_TX_DESC_LAST_SEG(__pdesc)			\
93
-	SHIFT_AND_MASK_LE(__pdesc, 26, 1)
94
-#define GET_TX_DESC_FIRST_SEG(__pdesc)			\
95
-	SHIFT_AND_MASK_LE(__pdesc, 27, 1)
96
-#define GET_TX_DESC_LINIP(__pdesc)			\
97
-	SHIFT_AND_MASK_LE(__pdesc, 28, 1)
98
-#define GET_TX_DESC_NO_ACM(__pdesc)			\
99
-	SHIFT_AND_MASK_LE(__pdesc, 29, 1)
100
-#define GET_TX_DESC_GF(__pdesc)				\
101
-	SHIFT_AND_MASK_LE(__pdesc, 30, 1)
102
-#define GET_TX_DESC_OWN(__pdesc)			\
103
-	SHIFT_AND_MASK_LE(__pdesc, 31, 1)
24
+static inline void set_tx_desc_offset(__le32 *__pdesc, u32  __val)
25
+{
26
+	le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));
27
+}
10428 
105
-#define SET_TX_DESC_MACID(__pdesc, __val)		\
106
-	SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val)
107
-#define SET_TX_DESC_AGG_BREAK(__pdesc, __val)		\
108
-	SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val)
109
-#define SET_TX_DESC_BK(__pdesc, __val)			\
110
-	SET_BITS_OFFSET_LE(__pdesc+4, 6, 1, __val)
111
-#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val)		\
112
-	SET_BITS_OFFSET_LE(__pdesc+4, 7, 1, __val)
113
-#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val)		\
114
-	SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val)
115
-#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val)	\
116
-	SET_BITS_OFFSET_LE(__pdesc+4, 13, 1, __val)
117
-#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val)	\
118
-	SET_BITS_OFFSET_LE(__pdesc+4, 14, 1, __val)
119
-#define SET_TX_DESC_PIFS(__pdesc, __val)		\
120
-	SET_BITS_OFFSET_LE(__pdesc+4, 15, 1, __val)
121
-#define SET_TX_DESC_RATE_ID(__pdesc, __val)		\
122
-	SET_BITS_OFFSET_LE(__pdesc+4, 16, 4, __val)
123
-#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val)	\
124
-	SET_BITS_OFFSET_LE(__pdesc+4, 20, 1, __val)
125
-#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val)		\
126
-	SET_BITS_OFFSET_LE(__pdesc+4, 21, 1, __val)
127
-#define SET_TX_DESC_SEC_TYPE(__pdesc, __val)		\
128
-	SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val)
129
-#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val)		\
130
-	SET_BITS_OFFSET_LE(__pdesc+4, 24, 8, __val)
29
+static inline void set_tx_desc_bmc(__le32 *__pdesc, u32  __val)
30
+{
31
+	le32p_replace_bits(__pdesc, __val, BIT(24));
32
+}
13133 
132
-#define GET_TX_DESC_MACID(__pdesc)			\
133
-	SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
134
-#define GET_TX_DESC_AGG_ENABLE(__pdesc)			\
135
-	SHIFT_AND_MASK_LE(__pdesc+4, 5, 1)
136
-#define GET_TX_DESC_AGG_BREAK(__pdesc)			\
137
-	SHIFT_AND_MASK_LE(__pdesc+4, 6, 1)
138
-#define GET_TX_DESC_RDG_ENABLE(__pdesc)			\
139
-	SHIFT_AND_MASK_LE(__pdesc+4, 7, 1)
140
-#define GET_TX_DESC_QUEUE_SEL(__pdesc)			\
141
-	SHIFT_AND_MASK_LE(__pdesc+4, 8, 5)
142
-#define GET_TX_DESC_RDG_NAV_EXT(__pdesc)		\
143
-	SHIFT_AND_MASK_LE(__pdesc+4, 13, 1)
144
-#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc)		\
145
-	SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
146
-#define GET_TX_DESC_PIFS(__pdesc)			\
147
-	SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
148
-#define GET_TX_DESC_RATE_ID(__pdesc)			\
149
-	SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
150
-#define GET_TX_DESC_NAV_USE_HDR(__pdesc)		\
151
-	SHIFT_AND_MASK_LE(__pdesc+4, 20, 1)
152
-#define GET_TX_DESC_EN_DESC_ID(__pdesc)			\
153
-	SHIFT_AND_MASK_LE(__pdesc+4, 21, 1)
154
-#define GET_TX_DESC_SEC_TYPE(__pdesc)			\
155
-	SHIFT_AND_MASK_LE(__pdesc+4, 22, 2)
156
-#define GET_TX_DESC_PKT_OFFSET(__pdesc)			\
157
-	SHIFT_AND_MASK_LE(__pdesc+4, 24, 8)
34
+static inline void set_tx_desc_htc(__le32 *__pdesc, u32  __val)
35
+{
36
+	le32p_replace_bits(__pdesc, __val, BIT(25));
37
+}
15838 
159
-#define SET_TX_DESC_RTS_RC(__pdesc, __val)		\
160
-	SET_BITS_OFFSET_LE(__pdesc+8, 0, 6, __val)
161
-#define SET_TX_DESC_DATA_RC(__pdesc, __val)		\
162
-	SET_BITS_OFFSET_LE(__pdesc+8, 6, 6, __val)
163
-#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val)		\
164
-	SET_BITS_OFFSET_LE(__pdesc+8, 14, 2, __val)
165
-#define SET_TX_DESC_MORE_FRAG(__pdesc, __val)		\
166
-	SET_BITS_OFFSET_LE(__pdesc+8, 17, 1, __val)
167
-#define SET_TX_DESC_RAW(__pdesc, __val)			\
168
-	SET_BITS_OFFSET_LE(__pdesc+8, 18, 1, __val)
169
-#define SET_TX_DESC_CCX(__pdesc, __val)			\
170
-	SET_BITS_OFFSET_LE(__pdesc+8, 19, 1, __val)
171
-#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val)	\
172
-	SET_BITS_OFFSET_LE(__pdesc+8, 20, 3, __val)
173
-#define SET_TX_DESC_ANTSEL_A(__pdesc, __val)		\
174
-	SET_BITS_OFFSET_LE(__pdesc+8, 24, 1, __val)
175
-#define SET_TX_DESC_ANTSEL_B(__pdesc, __val)		\
176
-	SET_BITS_OFFSET_LE(__pdesc+8, 25, 1, __val)
177
-#define SET_TX_DESC_TX_ANT_CCK(__pdesc, __val)		\
178
-	SET_BITS_OFFSET_LE(__pdesc+8, 26, 2, __val)
179
-#define SET_TX_DESC_TX_ANTL(__pdesc, __val)		\
180
-	SET_BITS_OFFSET_LE(__pdesc+8, 28, 2, __val)
181
-#define SET_TX_DESC_TX_ANT_HT(__pdesc, __val)		\
182
-	SET_BITS_OFFSET_LE(__pdesc+8, 30, 2, __val)
39
+static inline void set_tx_desc_last_seg(__le32 *__pdesc, u32  __val)
40
+{
41
+	le32p_replace_bits(__pdesc, __val, BIT(26));
42
+}
18343 
184
-#define GET_TX_DESC_RTS_RC(__pdesc)			\
185
-	SHIFT_AND_MASK_LE(__pdesc+8, 0, 6)
186
-#define GET_TX_DESC_DATA_RC(__pdesc)			\
187
-	SHIFT_AND_MASK_LE(__pdesc+8, 6, 6)
188
-#define GET_TX_DESC_BAR_RTY_TH(__pdesc)			\
189
-	SHIFT_AND_MASK_LE(__pdesc+8, 14, 2)
190
-#define GET_TX_DESC_MORE_FRAG(__pdesc)			\
191
-	SHIFT_AND_MASK_LE(__pdesc+8, 17, 1)
192
-#define GET_TX_DESC_RAW(__pdesc)			\
193
-	SHIFT_AND_MASK_LE(__pdesc+8, 18, 1)
194
-#define GET_TX_DESC_CCX(__pdesc)			\
195
-	SHIFT_AND_MASK_LE(__pdesc+8, 19, 1)
196
-#define GET_TX_DESC_AMPDU_DENSITY(__pdesc)		\
197
-	SHIFT_AND_MASK_LE(__pdesc+8, 20, 3)
198
-#define GET_TX_DESC_ANTSEL_A(__pdesc)			\
199
-	SHIFT_AND_MASK_LE(__pdesc+8, 24, 1)
200
-#define GET_TX_DESC_ANTSEL_B(__pdesc)			\
201
-	SHIFT_AND_MASK_LE(__pdesc+8, 25, 1)
202
-#define GET_TX_DESC_TX_ANT_CCK(__pdesc)			\
203
-	SHIFT_AND_MASK_LE(__pdesc+8, 26, 2)
204
-#define GET_TX_DESC_TX_ANTL(__pdesc)			\
205
-	SHIFT_AND_MASK_LE(__pdesc+8, 28, 2)
206
-#define GET_TX_DESC_TX_ANT_HT(__pdesc)			\
207
-	SHIFT_AND_MASK_LE(__pdesc+8, 30, 2)
44
+static inline void set_tx_desc_first_seg(__le32 *__pdesc, u32  __val)
45
+{
46
+	le32p_replace_bits(__pdesc, __val, BIT(27));
47
+}
20848 
209
-#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val)	\
210
-	SET_BITS_OFFSET_LE(__pdesc+12, 0, 8, __val)
211
-#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val)		\
212
-	SET_BITS_OFFSET_LE(__pdesc+12, 8, 8, __val)
213
-#define SET_TX_DESC_SEQ(__pdesc, __val)			\
214
-	SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val)
215
-#define SET_TX_DESC_PKT_ID(__pdesc, __val)		\
216
-	SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val)
49
+static inline void set_tx_desc_linip(__le32 *__pdesc, u32  __val)
50
+{
51
+	le32p_replace_bits(__pdesc, __val, BIT(28));
52
+}
21753 
218
-#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc)		\
219
-	SHIFT_AND_MASK_LE(__pdesc+12, 0, 8)
220
-#define GET_TX_DESC_TAIL_PAGE(__pdesc)			\
221
-	SHIFT_AND_MASK_LE(__pdesc+12, 8, 8)
222
-#define GET_TX_DESC_SEQ(__pdesc)			\
223
-	SHIFT_AND_MASK_LE(__pdesc+12, 16, 12)
224
-#define GET_TX_DESC_PKT_ID(__pdesc)			\
225
-	SHIFT_AND_MASK_LE(__pdesc+12, 28, 4)
54
+static inline void set_tx_desc_own(__le32 *__pdesc, u32  __val)
55
+{
56
+	le32p_replace_bits(__pdesc, __val, BIT(31));
57
+}
22658 
227
-#define SET_TX_DESC_RTS_RATE(__pdesc, __val)		\
228
-	SET_BITS_OFFSET_LE(__pdesc+16, 0, 5, __val)
229
-#define SET_TX_DESC_AP_DCFE(__pdesc, __val)		\
230
-	SET_BITS_OFFSET_LE(__pdesc+16, 5, 1, __val)
231
-#define SET_TX_DESC_QOS(__pdesc, __val)			\
232
-	SET_BITS_OFFSET_LE(__pdesc+16, 6, 1, __val)
233
-#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val)		\
234
-	SET_BITS_OFFSET_LE(__pdesc+16, 7, 1, __val)
235
-#define SET_TX_DESC_USE_RATE(__pdesc, __val)		\
236
-	SET_BITS_OFFSET_LE(__pdesc+16, 8, 1, __val)
237
-#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val)	\
238
-	SET_BITS_OFFSET_LE(__pdesc+16, 9, 1, __val)
239
-#define SET_TX_DESC_DISABLE_FB(__pdesc, __val)		\
240
-	SET_BITS_OFFSET_LE(__pdesc+16, 10, 1, __val)
241
-#define SET_TX_DESC_CTS2SELF(__pdesc, __val)		\
242
-	SET_BITS_OFFSET_LE(__pdesc+16, 11, 1, __val)
243
-#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val)		\
244
-	SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val)
245
-#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val)	\
246
-	SET_BITS_OFFSET_LE(__pdesc+16, 13, 1, __val)
247
-#define SET_TX_DESC_PORT_ID(__pdesc, __val)		\
248
-	SET_BITS_OFFSET_LE(__pdesc+16, 14, 1, __val)
249
-#define SET_TX_DESC_WAIT_DCTS(__pdesc, __val)		\
250
-	SET_BITS_OFFSET_LE(__pdesc+16, 18, 1, __val)
251
-#define SET_TX_DESC_CTS2AP_EN(__pdesc, __val)		\
252
-	SET_BITS_OFFSET_LE(__pdesc+16, 19, 1, __val)
253
-#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val)	\
254
-	SET_BITS_OFFSET_LE(__pdesc+16, 20, 2, __val)
255
-#define SET_TX_DESC_TX_STBC(__pdesc, __val)		\
256
-	SET_BITS_OFFSET_LE(__pdesc+16, 22, 2, __val)
257
-#define SET_TX_DESC_DATA_SHORT(__pdesc, __val)		\
258
-	SET_BITS_OFFSET_LE(__pdesc+16, 24, 1, __val)
259
-#define SET_TX_DESC_DATA_BW(__pdesc, __val)		\
260
-	SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val)
261
-#define SET_TX_DESC_RTS_SHORT(__pdesc, __val)		\
262
-	SET_BITS_OFFSET_LE(__pdesc+16, 26, 1, __val)
263
-#define SET_TX_DESC_RTS_BW(__pdesc, __val)		\
264
-	SET_BITS_OFFSET_LE(__pdesc+16, 27, 1, __val)
265
-#define SET_TX_DESC_RTS_SC(__pdesc, __val)		\
266
-	SET_BITS_OFFSET_LE(__pdesc+16, 28, 2, __val)
267
-#define SET_TX_DESC_RTS_STBC(__pdesc, __val)		\
268
-	SET_BITS_OFFSET_LE(__pdesc+16, 30, 2, __val)
59
+static inline int get_tx_desc_own(__le32 *__pdesc)
60
+{
61
+	return le32_get_bits(*(__pdesc), BIT(31));
62
+}
26963 
270
-#define GET_TX_DESC_RTS_RATE(__pdesc)			\
271
-	SHIFT_AND_MASK_LE(__pdesc+16, 0, 5)
272
-#define GET_TX_DESC_AP_DCFE(__pdesc)			\
273
-	SHIFT_AND_MASK_LE(__pdesc+16, 5, 1)
274
-#define GET_TX_DESC_QOS(__pdesc)			\
275
-	SHIFT_AND_MASK_LE(__pdesc+16, 6, 1)
276
-#define GET_TX_DESC_HWSEQ_EN(__pdesc)			\
277
-	SHIFT_AND_MASK_LE(__pdesc+16, 7, 1)
278
-#define GET_TX_DESC_USE_RATE(__pdesc)			\
279
-	SHIFT_AND_MASK_LE(__pdesc+16, 8, 1)
280
-#define GET_TX_DESC_DISABLE_RTS_FB(__pdesc)		\
281
-	SHIFT_AND_MASK_LE(__pdesc+16, 9, 1)
282
-#define GET_TX_DESC_DISABLE_FB(__pdesc)			\
283
-	SHIFT_AND_MASK_LE(__pdesc+16, 10, 1)
284
-#define GET_TX_DESC_CTS2SELF(__pdesc)			\
285
-	SHIFT_AND_MASK_LE(__pdesc+16, 11, 1)
286
-#define GET_TX_DESC_RTS_ENABLE(__pdesc)			\
287
-	SHIFT_AND_MASK_LE(__pdesc+16, 12, 1)
288
-#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc)		\
289
-	SHIFT_AND_MASK_LE(__pdesc+16, 13, 1)
290
-#define GET_TX_DESC_PORT_ID(__pdesc)			\
291
-	SHIFT_AND_MASK_LE(__pdesc+16, 14, 1)
292
-#define GET_TX_DESC_WAIT_DCTS(__pdesc)			\
293
-	SHIFT_AND_MASK_LE(__pdesc+16, 18, 1)
294
-#define GET_TX_DESC_CTS2AP_EN(__pdesc)			\
295
-	SHIFT_AND_MASK_LE(__pdesc+16, 19, 1)
296
-#define GET_TX_DESC_TX_SUB_CARRIER(__pdesc)		\
297
-	SHIFT_AND_MASK_LE(__pdesc+16, 20, 2)
298
-#define GET_TX_DESC_TX_STBC(__pdesc)			\
299
-	SHIFT_AND_MASK_LE(__pdesc+16, 22, 2)
300
-#define GET_TX_DESC_DATA_SHORT(__pdesc)			\
301
-	SHIFT_AND_MASK_LE(__pdesc+16, 24, 1)
302
-#define GET_TX_DESC_DATA_BW(__pdesc)			\
303
-	SHIFT_AND_MASK_LE(__pdesc+16, 25, 1)
304
-#define GET_TX_DESC_RTS_SHORT(__pdesc)			\
305
-	SHIFT_AND_MASK_LE(__pdesc+16, 26, 1)
306
-#define GET_TX_DESC_RTS_BW(__pdesc)			\
307
-	SHIFT_AND_MASK_LE(__pdesc+16, 27, 1)
308
-#define GET_TX_DESC_RTS_SC(__pdesc)			\
309
-	SHIFT_AND_MASK_LE(__pdesc+16, 28, 2)
310
-#define GET_TX_DESC_RTS_STBC(__pdesc)			\
311
-	SHIFT_AND_MASK_LE(__pdesc+16, 30, 2)
64
+static inline void set_tx_desc_macid(__le32 *__pdesc, u32  __val)
65
+{
66
+	le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0));
67
+}
31268 
313
-#define SET_TX_DESC_TX_RATE(__pdesc, __val)		\
314
-	SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val)
315
-#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val)	\
316
-	SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
317
-#define SET_TX_DESC_CCX_TAG(__pdesc, __val)		\
318
-	SET_BITS_OFFSET_LE(__pdesc+20, 7, 1, __val)
319
-#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val)	\
320
-	SET_BITS_OFFSET_LE(__pdesc+20, 8, 5, __val)
321
-#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val)	\
322
-	SET_BITS_OFFSET_LE(__pdesc+20, 13, 4, __val)
323
-#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val)	\
324
-	SET_BITS_OFFSET_LE(__pdesc+20, 17, 1, __val)
325
-#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val)	\
326
-	SET_BITS_OFFSET_LE(__pdesc+20, 18, 6, __val)
327
-#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val)	\
328
-	SET_BITS_OFFSET_LE(__pdesc+20, 24, 8, __val)
69
+static inline void set_tx_desc_agg_break(__le32 *__pdesc, u32  __val)
70
+{
71
+	le32p_replace_bits((__pdesc + 1), __val, BIT(5));
72
+}
32973 
330
-#define GET_TX_DESC_TX_RATE(__pdesc)			\
331
-	SHIFT_AND_MASK_LE(__pdesc+20, 0, 6)
332
-#define GET_TX_DESC_DATA_SHORTGI(__pdesc)		\
333
-	SHIFT_AND_MASK_LE(__pdesc+20, 6, 1)
334
-#define GET_TX_DESC_CCX_TAG(__pdesc)			\
335
-	SHIFT_AND_MASK_LE(__pdesc+20, 7, 1)
336
-#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc)		\
337
-	SHIFT_AND_MASK_LE(__pdesc+20, 8, 5)
338
-#define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc)		\
339
-	SHIFT_AND_MASK_LE(__pdesc+20, 13, 4)
340
-#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc)		\
341
-	SHIFT_AND_MASK_LE(__pdesc+20, 17, 1)
342
-#define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc)		\
343
-	SHIFT_AND_MASK_LE(__pdesc+20, 18, 6)
344
-#define GET_TX_DESC_USB_TXAGG_NUM(__pdesc)		\
345
-	SHIFT_AND_MASK_LE(__pdesc+20, 24, 8)
74
+static inline void set_tx_desc_rdg_enable(__le32 *__pdesc, u32  __val)
75
+{
76
+	le32p_replace_bits((__pdesc + 1), __val, BIT(7));
77
+}
34678 
347
-#define SET_TX_DESC_TXAGC_A(__pdesc, __val)		\
348
-	SET_BITS_OFFSET_LE(__pdesc+24, 0, 5, __val)
349
-#define SET_TX_DESC_TXAGC_B(__pdesc, __val)		\
350
-	SET_BITS_OFFSET_LE(__pdesc+24, 5, 5, __val)
351
-#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val)		\
352
-	SET_BITS_OFFSET_LE(__pdesc+24, 10, 1, __val)
353
-#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val)		\
354
-	SET_BITS_OFFSET_LE(__pdesc+24, 11, 5, __val)
355
-#define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val)	\
356
-	SET_BITS_OFFSET_LE(__pdesc+24, 16, 4, __val)
357
-#define SET_TX_DESC_MCSG2_MAX_LEN(__pdesc, __val)	\
358
-	SET_BITS_OFFSET_LE(__pdesc+24, 20, 4, __val)
359
-#define SET_TX_DESC_MCSG3_MAX_LEN(__pdesc, __val)	\
360
-	SET_BITS_OFFSET_LE(__pdesc+24, 24, 4, __val)
361
-#define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val)	\
362
-	SET_BITS_OFFSET_LE(__pdesc+24, 28, 4, __val)
79
+static inline void set_tx_desc_queue_sel(__le32 *__pdesc, u32  __val)
80
+{
81
+	le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));
82
+}
36383 
364
-#define GET_TX_DESC_TXAGC_A(__pdesc)			\
365
-	SHIFT_AND_MASK_LE(__pdesc+24, 0, 5)
366
-#define GET_TX_DESC_TXAGC_B(__pdesc)			\
367
-	SHIFT_AND_MASK_LE(__pdesc+24, 5, 5)
368
-#define GET_TX_DESC_USE_MAX_LEN(__pdesc)		\
369
-	SHIFT_AND_MASK_LE(__pdesc+24, 10, 1)
370
-#define GET_TX_DESC_MAX_AGG_NUM(__pdesc)		\
371
-	SHIFT_AND_MASK_LE(__pdesc+24, 11, 5)
372
-#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc)		\
373
-	SHIFT_AND_MASK_LE(__pdesc+24, 16, 4)
374
-#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc)		\
375
-	SHIFT_AND_MASK_LE(__pdesc+24, 20, 4)
376
-#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc)		\
377
-	SHIFT_AND_MASK_LE(__pdesc+24, 24, 4)
378
-#define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc)		\
379
-	SHIFT_AND_MASK_LE(__pdesc+24, 28, 4)
84
+static inline void set_tx_desc_rate_id(__le32 *__pdesc, u32  __val)
85
+{
86
+	le32p_replace_bits((__pdesc + 1), __val, GENMASK(19, 16));
87
+}
38088 
381
-#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val)	\
382
-	SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val)
383
-#define SET_TX_DESC_MCSG4_MAX_LEN(__pdesc, __val)	\
384
-	SET_BITS_OFFSET_LE(__pdesc+28, 16, 4, __val)
385
-#define SET_TX_DESC_MCSG5_MAX_LEN(__pdesc, __val)	\
386
-	SET_BITS_OFFSET_LE(__pdesc+28, 20, 4, __val)
387
-#define SET_TX_DESC_MCSG6_MAX_LEN(__pdesc, __val)	\
388
-	SET_BITS_OFFSET_LE(__pdesc+28, 24, 4, __val)
389
-#define SET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc, __val)	\
390
-	SET_BITS_OFFSET_LE(__pdesc+28, 28, 4, __val)
89
+static inline void set_tx_desc_sec_type(__le32 *__pdesc, u32  __val)
90
+{
91
+	le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));
92
+}
39193 
392
-#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc)		\
393
-	SHIFT_AND_MASK_LE(__pdesc+28, 0, 16)
394
-#define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc)		\
395
-	SHIFT_AND_MASK_LE(__pdesc+28, 16, 4)
396
-#define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc)		\
397
-	SHIFT_AND_MASK_LE(__pdesc+28, 20, 4)
398
-#define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc)		\
399
-	SHIFT_AND_MASK_LE(__pdesc+28, 24, 4)
400
-#define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc)		\
401
-	SHIFT_AND_MASK_LE(__pdesc+28, 28, 4)
94
+static inline void set_tx_desc_more_frag(__le32 *__pdesc, u32  __val)
95
+{
96
+	le32p_replace_bits((__pdesc + 2), __val, BIT(17));
97
+}
40298 
403
-#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val)	\
404
-	SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val)
405
-#define SET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc, __val) \
406
-	SET_BITS_OFFSET_LE(__pdesc+36, 0, 32, __val)
99
+static inline void set_tx_desc_ampdu_density(__le32 *__pdesc, u32  __val)
100
+{
101
+	le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20));
102
+}
407103 
408
-#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc)		\
409
-	SHIFT_AND_MASK_LE(__pdesc+32, 0, 32)
410
-#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc)	\
411
-	SHIFT_AND_MASK_LE(__pdesc+36, 0, 32)
104
+static inline void set_tx_desc_seq(__le32 *__pdesc, u32  __val)
105
+{
106
+	le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16));
107
+}
412108 
413
-#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val)	\
414
-	SET_BITS_OFFSET_LE(__pdesc+40, 0, 32, __val)
415
-#define SET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc, __val) \
416
-	SET_BITS_OFFSET_LE(__pdesc+44, 0, 32, __val)
109
+static inline void set_tx_desc_pkt_id(__le32 *__pdesc, u32  __val)
110
+{
111
+	le32p_replace_bits((__pdesc + 3), __val, GENMASK(31, 28));
112
+}
417113 
418
-#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc)		\
419
-	SHIFT_AND_MASK_LE(__pdesc+40, 0, 32)
420
-#define GET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc)	\
421
-	SHIFT_AND_MASK_LE(__pdesc+44, 0, 32)
114
+static inline void set_tx_desc_rts_rate(__le32 *__pdesc, u32  __val)
115
+{
116
+	le32p_replace_bits((__pdesc + 4), __val, GENMASK(4, 0));
117
+}
422118 
423
-#define GET_RX_DESC_PKT_LEN(__pdesc)			\
424
-	SHIFT_AND_MASK_LE(__pdesc, 0, 14)
425
-#define GET_RX_DESC_CRC32(__pdesc)			\
426
-	SHIFT_AND_MASK_LE(__pdesc, 14, 1)
427
-#define GET_RX_DESC_ICV(__pdesc)			\
428
-	SHIFT_AND_MASK_LE(__pdesc, 15, 1)
429
-#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc)		\
430
-	SHIFT_AND_MASK_LE(__pdesc, 16, 4)
431
-#define GET_RX_DESC_SECURITY(__pdesc)			\
432
-	SHIFT_AND_MASK_LE(__pdesc, 20, 3)
433
-#define GET_RX_DESC_QOS(__pdesc)			\
434
-	SHIFT_AND_MASK_LE(__pdesc, 23, 1)
435
-#define GET_RX_DESC_SHIFT(__pdesc)			\
436
-	SHIFT_AND_MASK_LE(__pdesc, 24, 2)
437
-#define GET_RX_DESC_PHYST(__pdesc)			\
438
-	SHIFT_AND_MASK_LE(__pdesc, 26, 1)
439
-#define GET_RX_DESC_SWDEC(__pdesc)			\
440
-	SHIFT_AND_MASK_LE(__pdesc, 27, 1)
441
-#define GET_RX_DESC_LS(__pdesc)				\
442
-	SHIFT_AND_MASK_LE(__pdesc, 28, 1)
443
-#define GET_RX_DESC_FS(__pdesc)				\
444
-	SHIFT_AND_MASK_LE(__pdesc, 29, 1)
445
-#define GET_RX_DESC_EOR(__pdesc)			\
446
-	SHIFT_AND_MASK_LE(__pdesc, 30, 1)
447
-#define GET_RX_DESC_OWN(__pdesc)			\
448
-	SHIFT_AND_MASK_LE(__pdesc, 31, 1)
119
+static inline void set_tx_desc_qos(__le32 *__pdesc, u32  __val)
120
+{
121
+	le32p_replace_bits((__pdesc + 4), __val, BIT(6));
122
+}
449123 
450
-#define SET_RX_DESC_PKT_LEN(__pdesc, __val)		\
451
-	SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
452
-#define SET_RX_DESC_EOR(__pdesc, __val)			\
453
-	SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
454
-#define SET_RX_DESC_OWN(__pdesc, __val)			\
455
-	SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
124
+static inline void set_tx_desc_hwseq_en(__le32 *__pdesc, u32  __val)
125
+{
126
+	le32p_replace_bits((__pdesc + 4), __val, BIT(7));
127
+}
456128 
457
-#define GET_RX_DESC_MACID(__pdesc)			\
458
-	SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
459
-#define GET_RX_DESC_TID(__pdesc)			\
460
-	SHIFT_AND_MASK_LE(__pdesc+4, 5, 4)
461
-#define GET_RX_DESC_HWRSVD(__pdesc)			\
462
-	SHIFT_AND_MASK_LE(__pdesc+4, 9, 5)
463
-#define GET_RX_DESC_PAGGR(__pdesc)			\
464
-	SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
465
-#define GET_RX_DESC_FAGGR(__pdesc)			\
466
-	SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
467
-#define GET_RX_DESC_A1_FIT(__pdesc)			\
468
-	SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
469
-#define GET_RX_DESC_A2_FIT(__pdesc)			\
470
-	SHIFT_AND_MASK_LE(__pdesc+4, 20, 4)
471
-#define GET_RX_DESC_PAM(__pdesc)			\
472
-	SHIFT_AND_MASK_LE(__pdesc+4, 24, 1)
473
-#define GET_RX_DESC_PWR(__pdesc)			\
474
-	SHIFT_AND_MASK_LE(__pdesc+4, 25, 1)
475
-#define GET_RX_DESC_MD(__pdesc)				\
476
-	SHIFT_AND_MASK_LE(__pdesc+4, 26, 1)
477
-#define GET_RX_DESC_MF(__pdesc)				\
478
-	SHIFT_AND_MASK_LE(__pdesc+4, 27, 1)
479
-#define GET_RX_DESC_TYPE(__pdesc)			\
480
-	SHIFT_AND_MASK_LE(__pdesc+4, 28, 2)
481
-#define GET_RX_DESC_MC(__pdesc)				\
482
-	SHIFT_AND_MASK_LE(__pdesc+4, 30, 1)
483
-#define GET_RX_DESC_BC(__pdesc)				\
484
-	SHIFT_AND_MASK_LE(__pdesc+4, 31, 1)
485
-#define GET_RX_DESC_SEQ(__pdesc)			\
486
-	SHIFT_AND_MASK_LE(__pdesc+8, 0, 12)
487
-#define GET_RX_DESC_FRAG(__pdesc)			\
488
-	SHIFT_AND_MASK_LE(__pdesc+8, 12, 4)
489
-#define GET_RX_DESC_NEXT_PKT_LEN(__pdesc)		\
490
-	SHIFT_AND_MASK_LE(__pdesc+8, 16, 14)
491
-#define GET_RX_DESC_NEXT_IND(__pdesc)			\
492
-	SHIFT_AND_MASK_LE(__pdesc+8, 30, 1)
493
-#define GET_RX_DESC_RSVD(__pdesc)			\
494
-	SHIFT_AND_MASK_LE(__pdesc+8, 31, 1)
129
+static inline void set_tx_desc_use_rate(__le32 *__pdesc, u32  __val)
130
+{
131
+	le32p_replace_bits((__pdesc + 4), __val, BIT(8));
132
+}
495133 
496
-#define GET_RX_DESC_RXMCS(__pdesc)			\
497
-	SHIFT_AND_MASK_LE(__pdesc+12, 0, 6)
498
-#define GET_RX_DESC_RXHT(__pdesc)			\
499
-	SHIFT_AND_MASK_LE(__pdesc+12, 6, 1)
500
-#define GET_RX_DESC_SPLCP(__pdesc)			\
501
-	SHIFT_AND_MASK_LE(__pdesc+12, 8, 1)
502
-#define GET_RX_DESC_BW(__pdesc)				\
503
-	SHIFT_AND_MASK_LE(__pdesc+12, 9, 1)
504
-#define GET_RX_DESC_HTC(__pdesc)			\
505
-	SHIFT_AND_MASK_LE(__pdesc+12, 10, 1)
506
-#define GET_RX_DESC_HWPC_ERR(__pdesc)			\
507
-	SHIFT_AND_MASK_LE(__pdesc+12, 14, 1)
508
-#define GET_RX_DESC_HWPC_IND(__pdesc)			\
509
-	SHIFT_AND_MASK_LE(__pdesc+12, 15, 1)
510
-#define GET_RX_DESC_IV0(__pdesc)			\
511
-	SHIFT_AND_MASK_LE(__pdesc+12, 16, 16)
134
+static inline void set_tx_desc_disable_fb(__le32 *__pdesc, u32  __val)
135
+{
136
+	le32p_replace_bits((__pdesc + 4), __val, BIT(10));
137
+}
512138 
513
-#define GET_RX_DESC_IV1(__pdesc)			\
514
-	SHIFT_AND_MASK_LE(__pdesc+16, 0, 32)
515
-#define GET_RX_DESC_TSFL(__pdesc)			\
516
-	SHIFT_AND_MASK_LE(__pdesc+20, 0, 32)
139
+static inline void set_tx_desc_cts2self(__le32 *__pdesc, u32  __val)
140
+{
141
+	le32p_replace_bits((__pdesc + 4), __val, BIT(11));
142
+}
517143 
518
-#define GET_RX_DESC_BUFF_ADDR(__pdesc)			\
519
-	SHIFT_AND_MASK_LE(__pdesc+24, 0, 32)
520
-#define GET_RX_DESC_BUFF_ADDR64(__pdesc)		\
521
-	SHIFT_AND_MASK_LE(__pdesc+28, 0, 32)
144
+static inline void set_tx_desc_rts_enable(__le32 *__pdesc, u32  __val)
145
+{
146
+	le32p_replace_bits((__pdesc + 4), __val, BIT(12));
147
+}
522148 
523
-#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val)		\
524
-	SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val)
525
-#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) 	\
526
-	SET_BITS_OFFSET_LE(__pdesc+28, 0, 32, __val)
149
+static inline void set_tx_desc_hw_rts_enable(__le32 *__pdesc, u32  __val)
150
+{
151
+	le32p_replace_bits((__pdesc + 4), __val, BIT(13));
152
+}
527153 
528
-#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size)	\
529
-	memset(__pdesc, 0, min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET))
154
+static inline void set_tx_desc_tx_sub_carrier(__le32 *__pdesc, u32  __val)
155
+{
156
+	le32p_replace_bits((__pdesc + 4), __val, GENMASK(21, 20));
157
+}
158
+
159
+static inline void set_tx_desc_data_bw(__le32 *__pdesc, u32  __val)
160
+{
161
+	le32p_replace_bits((__pdesc + 4), __val, BIT(25));
162
+}
163
+
164
+static inline void set_tx_desc_rts_short(__le32 *__pdesc, u32  __val)
165
+{
166
+	le32p_replace_bits((__pdesc + 4), __val, BIT(26));
167
+}
168
+
169
+static inline void set_tx_desc_rts_bw(__le32 *__pdesc, u32  __val)
170
+{
171
+	le32p_replace_bits((__pdesc + 4), __val, BIT(27));
172
+}
173
+
174
+static inline void set_tx_desc_rts_sc(__le32 *__pdesc, u32  __val)
175
+{
176
+	le32p_replace_bits((__pdesc + 4), __val, GENMASK(29, 28));
177
+}
178
+
179
+static inline void set_tx_desc_rts_stbc(__le32 *__pdesc, u32  __val)
180
+{
181
+	le32p_replace_bits((__pdesc + 4), __val, GENMASK(31, 30));
182
+}
183
+
184
+static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32  __val)
185
+{
186
+	le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0));
187
+}
188
+
189
+static inline void set_tx_desc_data_shortgi(__le32 *__pdesc, u32  __val)
190
+{
191
+	le32p_replace_bits((__pdesc + 5), __val, BIT(6));
192
+}
193
+
194
+static inline void set_tx_desc_data_rate_fb_limit(__le32 *__pdesc, u32  __val)
195
+{
196
+	le32p_replace_bits((__pdesc + 5), __val, GENMASK(12, 8));
197
+}
198
+
199
+static inline void set_tx_desc_rts_rate_fb_limit(__le32 *__pdesc, u32  __val)
200
+{
201
+	le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13));
202
+}
203
+
204
+static inline void set_tx_desc_max_agg_num(__le32 *__pdesc, u32  __val)
205
+{
206
+	le32p_replace_bits((__pdesc + 6), __val, GENMASK(15, 11));
207
+}
208
+
209
+static inline void set_tx_desc_tx_buffer_size(__le32 *__pdesc, u32  __val)
210
+{
211
+	le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));
212
+}
213
+
214
+static inline void set_tx_desc_tx_buffer_address(__le32 *__pdesc, u32  __val)
215
+{
216
+	*(__pdesc + 8) = cpu_to_le32(__val);
217
+}
218
+
219
+static inline u32 get_tx_desc_tx_buffer_address(__le32 *__pdesc)
220
+{
221
+	return le32_to_cpu(*((__pdesc + 8)));
222
+}
223
+
224
+static inline void set_tx_desc_next_desc_address(__le32 *__pdesc, u32  __val)
225
+{
226
+	*(__pdesc + 10) = cpu_to_le32(__val);
227
+}
228
+
229
+static inline int get_rx_desc_pkt_len(__le32 *__pdesc)
230
+{
231
+	return le32_get_bits(*(__pdesc), GENMASK(13, 0));
232
+}
233
+
234
+static inline int get_rx_desc_crc32(__le32 *__pdesc)
235
+{
236
+	return le32_get_bits(*(__pdesc), BIT(14));
237
+}
238
+
239
+static inline int get_rx_desc_icv(__le32 *__pdesc)
240
+{
241
+	return le32_get_bits(*(__pdesc), BIT(15));
242
+}
243
+
244
+static inline int get_rx_desc_drv_info_size(__le32 *__pdesc)
245
+{
246
+	return le32_get_bits(*(__pdesc), GENMASK(19, 16));
247
+}
248
+
249
+static inline int get_rx_desc_shift(__le32 *__pdesc)
250
+{
251
+	return le32_get_bits(*(__pdesc), GENMASK(25, 24));
252
+}
253
+
254
+static inline int get_rx_desc_physt(__le32 *__pdesc)
255
+{
256
+	return le32_get_bits(*(__pdesc), BIT(26));
257
+}
258
+
259
+static inline int get_rx_desc_swdec(__le32 *__pdesc)
260
+{
261
+	return le32_get_bits(*(__pdesc), BIT(27));
262
+}
263
+
264
+static inline int get_rx_desc_own(__le32 *__pdesc)
265
+{
266
+	return le32_get_bits(*(__pdesc), BIT(31));
267
+}
268
+
269
+static inline void set_rx_desc_pkt_len(__le32 *__pdesc, u32  __val)
270
+{
271
+	le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));
272
+}
273
+
274
+static inline void set_rx_desc_eor(__le32 *__pdesc, u32  __val)
275
+{
276
+	le32p_replace_bits(__pdesc, __val, BIT(30));
277
+}
278
+
279
+static inline void set_rx_desc_own(__le32 *__pdesc, u32  __val)
280
+{
281
+	le32p_replace_bits(__pdesc, __val, BIT(31));
282
+}
283
+
284
+static inline int get_rx_desc_paggr(__le32 *__pdesc)
285
+{
286
+	return le32_get_bits(*((__pdesc + 1)), BIT(14));
287
+}
288
+
289
+static inline int get_rx_desc_faggr(__le32 *__pdesc)
290
+{
291
+	return le32_get_bits(*((__pdesc + 1)), BIT(15));
292
+}
293
+
294
+static inline int get_rx_desc_rxmcs(__le32 *__pdesc)
295
+{
296
+	return le32_get_bits(*((__pdesc + 3)), GENMASK(5, 0));
297
+}
298
+
299
+static inline int get_rx_desc_rxht(__le32 *__pdesc)
300
+{
301
+	return le32_get_bits(*((__pdesc + 3)), BIT(6));
302
+}
303
+
304
+static inline int get_rx_desc_splcp(__le32 *__pdesc)
305
+{
306
+	return le32_get_bits(*((__pdesc + 3)), BIT(8));
307
+}
308
+
309
+static inline int get_rx_desc_bw(__le32 *__pdesc)
310
+{
311
+	return le32_get_bits(*((__pdesc + 3)), BIT(9));
312
+}
313
+
314
+static inline u32 get_rx_desc_tsfl(__le32 *__pdesc)
315
+{
316
+	return le32_to_cpu(*((__pdesc + 5)));
317
+}
318
+
319
+static inline u32 get_rx_desc_buff_addr(__le32 *__pdesc)
320
+{
321
+	return le32_to_cpu(*((__pdesc + 6)));
322
+}
323
+
324
+static inline void set_rx_desc_buff_addr(__le32 *__pdesc, u32  __val)
325
+{
326
+	*(__pdesc + 6) = cpu_to_le32(__val);
327
+}
328
+
329
+static inline void clear_pci_tx_desc_content(__le32 *__pdesc, int _size)
330
+{
331
+	memset(__pdesc, 0, min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET));
332
+}
530333 
531334 struct rx_fwinfo_92c {
532335 	u8 gain_trsw[4];