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| 1 | +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) |
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| 1 | 2 | /* QLogic qed NIC Driver |
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| 2 | 3 | * Copyright (c) 2015-2017 QLogic Corporation |
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| 3 | | - * |
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| 4 | | - * This software is available to you under a choice of one of two |
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| 5 | | - * licenses. You may choose to be licensed under the terms of the GNU |
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| 6 | | - * General Public License (GPL) Version 2, available from the file |
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| 7 | | - * COPYING in the main directory of this source tree, or the |
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| 8 | | - * OpenIB.org BSD license below: |
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| 9 | | - * |
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| 10 | | - * Redistribution and use in source and binary forms, with or |
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| 11 | | - * without modification, are permitted provided that the following |
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| 12 | | - * conditions are met: |
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| 13 | | - * |
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| 14 | | - * - Redistributions of source code must retain the above |
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| 15 | | - * copyright notice, this list of conditions and the following |
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| 16 | | - * disclaimer. |
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| 17 | | - * |
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| 18 | | - * - Redistributions in binary form must reproduce the above |
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| 19 | | - * copyright notice, this list of conditions and the following |
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| 20 | | - * disclaimer in the documentation and /or other materials |
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| 21 | | - * provided with the distribution. |
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| 22 | | - * |
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| 23 | | - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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| 24 | | - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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| 25 | | - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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| 26 | | - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
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| 27 | | - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
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| 28 | | - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 29 | | - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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| 30 | | - * SOFTWARE. |
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| 4 | + * Copyright (c) 2019-2020 Marvell International Ltd. |
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| 31 | 5 | */ |
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| 32 | 6 | |
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| 33 | 7 | #include <linux/types.h> |
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| .. | .. |
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| 326 | 300 | struct qed_tunnel_info *p_tunn, |
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| 327 | 301 | bool allow_npar_tx_switch) |
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| 328 | 302 | { |
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| 303 | + struct outer_tag_config_struct *outer_tag_config; |
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| 329 | 304 | struct pf_start_ramrod_data *p_ramrod = NULL; |
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| 330 | 305 | u16 sb = qed_int_get_sp_sb_id(p_hwfn); |
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| 331 | 306 | u8 sb_index = p_hwfn->p_eq->eq_sb_index; |
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| 332 | 307 | struct qed_spq_entry *p_ent = NULL; |
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| 333 | 308 | struct qed_sp_init_data init_data; |
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| 334 | | - int rc = -EINVAL; |
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| 335 | 309 | u8 page_cnt, i; |
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| 310 | + int rc; |
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| 336 | 311 | |
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| 337 | 312 | /* update initial eq producer */ |
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| 338 | 313 | qed_eq_prod_update(p_hwfn, |
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| .. | .. |
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| 362 | 337 | else |
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| 363 | 338 | p_ramrod->mf_mode = MF_NPAR; |
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| 364 | 339 | |
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| 365 | | - p_ramrod->outer_tag_config.outer_tag.tci = |
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| 366 | | - cpu_to_le16(p_hwfn->hw_info.ovlan); |
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| 340 | + outer_tag_config = &p_ramrod->outer_tag_config; |
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| 341 | + outer_tag_config->outer_tag.tci = cpu_to_le16(p_hwfn->hw_info.ovlan); |
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| 342 | + |
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| 367 | 343 | if (test_bit(QED_MF_8021Q_TAGGING, &p_hwfn->cdev->mf_bits)) { |
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| 368 | | - p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021Q; |
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| 344 | + outer_tag_config->outer_tag.tpid = cpu_to_le16(ETH_P_8021Q); |
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| 369 | 345 | } else if (test_bit(QED_MF_8021AD_TAGGING, &p_hwfn->cdev->mf_bits)) { |
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| 370 | | - p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021AD; |
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| 371 | | - p_ramrod->outer_tag_config.enable_stag_pri_change = 1; |
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| 346 | + outer_tag_config->outer_tag.tpid = cpu_to_le16(ETH_P_8021AD); |
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| 347 | + outer_tag_config->enable_stag_pri_change = 1; |
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| 372 | 348 | } |
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| 373 | 349 | |
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| 374 | | - p_ramrod->outer_tag_config.pri_map_valid = 1; |
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| 350 | + outer_tag_config->pri_map_valid = 1; |
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| 375 | 351 | for (i = 0; i < QED_MAX_PFC_PRIORITIES; i++) |
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| 376 | | - p_ramrod->outer_tag_config.inner_to_outer_pri_map[i] = i; |
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| 352 | + outer_tag_config->inner_to_outer_pri_map[i] = i; |
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| 377 | 353 | |
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| 378 | 354 | /* enable_stag_pri_change should be set if port is in BD mode or, |
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| 379 | 355 | * UFP with Host Control mode. |
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| 380 | 356 | */ |
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| 381 | 357 | if (test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) { |
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| 382 | 358 | if (p_hwfn->ufp_info.pri_type == QED_UFP_PRI_OS) |
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| 383 | | - p_ramrod->outer_tag_config.enable_stag_pri_change = 1; |
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| 359 | + outer_tag_config->enable_stag_pri_change = 1; |
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| 384 | 360 | else |
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| 385 | | - p_ramrod->outer_tag_config.enable_stag_pri_change = 0; |
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| 361 | + outer_tag_config->enable_stag_pri_change = 0; |
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| 386 | 362 | |
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| 387 | | - p_ramrod->outer_tag_config.outer_tag.tci |= |
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| 363 | + outer_tag_config->outer_tag.tci |= |
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| 388 | 364 | cpu_to_le16(((u16)p_hwfn->ufp_info.tc << 13)); |
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| 389 | 365 | } |
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| 390 | 366 | |
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| 391 | 367 | /* Place EQ address in RAMROD */ |
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| 392 | 368 | DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr, |
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| 393 | | - p_hwfn->p_eq->chain.pbl_sp.p_phys_table); |
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| 369 | + qed_chain_get_pbl_phys(&p_hwfn->p_eq->chain)); |
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| 394 | 370 | page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain); |
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| 395 | 371 | p_ramrod->event_ring_num_pages = page_cnt; |
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| 396 | 372 | DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr, |
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| 397 | | - p_hwfn->p_consq->chain.pbl_sp.p_phys_table); |
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| 373 | + qed_chain_get_pbl_phys(&p_hwfn->p_consq->chain)); |
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| 398 | 374 | |
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| 399 | 375 | qed_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config); |
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| 400 | 376 | |
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| .. | .. |
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| 432 | 408 | |
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| 433 | 409 | DP_VERBOSE(p_hwfn, QED_MSG_SPQ, |
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| 434 | 410 | "Setting event_ring_sb [id %04x index %02x], outer_tag.tci [%d]\n", |
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| 435 | | - sb, sb_index, p_ramrod->outer_tag_config.outer_tag.tci); |
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| 411 | + sb, sb_index, outer_tag_config->outer_tag.tci); |
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| 436 | 412 | |
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| 437 | 413 | rc = qed_spq_post(p_hwfn, p_ent, NULL); |
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| 438 | 414 | |
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| .. | .. |
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| 447 | 423 | { |
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| 448 | 424 | struct qed_spq_entry *p_ent = NULL; |
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| 449 | 425 | struct qed_sp_init_data init_data; |
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| 450 | | - int rc = -EINVAL; |
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| 426 | + int rc; |
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| 451 | 427 | |
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| 452 | 428 | /* Get SPQ entry */ |
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| 453 | 429 | memset(&init_data, 0, sizeof(init_data)); |
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| .. | .. |
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| 471 | 447 | { |
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| 472 | 448 | struct qed_spq_entry *p_ent = NULL; |
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| 473 | 449 | struct qed_sp_init_data init_data; |
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| 474 | | - int rc = -EOPNOTSUPP; |
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| 450 | + int rc; |
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| 475 | 451 | |
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| 476 | 452 | if (p_hwfn->ufp_info.pri_type == QED_UFP_PRI_UNKNOWN) { |
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| 477 | 453 | DP_INFO(p_hwfn, "Invalid priority type %d\n", |
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| .. | .. |
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| 509 | 485 | { |
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| 510 | 486 | struct qed_spq_entry *p_ent = NULL; |
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| 511 | 487 | struct qed_sp_init_data init_data; |
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| 512 | | - int rc = -EINVAL; |
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| 488 | + int rc; |
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| 513 | 489 | |
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| 514 | 490 | if (IS_VF(p_hwfn->cdev)) |
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| 515 | 491 | return qed_vf_pf_tunnel_param_update(p_hwfn, p_tunn); |
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| .. | .. |
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| 546 | 522 | { |
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| 547 | 523 | struct qed_spq_entry *p_ent = NULL; |
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| 548 | 524 | struct qed_sp_init_data init_data; |
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| 549 | | - int rc = -EINVAL; |
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| 525 | + int rc; |
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| 550 | 526 | |
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| 551 | 527 | /* Get SPQ entry */ |
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| 552 | 528 | memset(&init_data, 0, sizeof(init_data)); |
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| .. | .. |
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| 588 | 564 | { |
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| 589 | 565 | struct qed_spq_entry *p_ent = NULL; |
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| 590 | 566 | struct qed_sp_init_data init_data; |
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| 591 | | - int rc = -EINVAL; |
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| 567 | + int rc; |
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| 592 | 568 | |
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| 593 | 569 | /* Get SPQ entry */ |
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| 594 | 570 | memset(&init_data, 0, sizeof(init_data)); |
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| .. | .. |
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| 604 | 580 | |
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| 605 | 581 | p_ent->ramrod.pf_update.update_mf_vlan_flag = true; |
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| 606 | 582 | p_ent->ramrod.pf_update.mf_vlan = cpu_to_le16(p_hwfn->hw_info.ovlan); |
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| 583 | + if (test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits)) |
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| 584 | + p_ent->ramrod.pf_update.mf_vlan |= |
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| 585 | + cpu_to_le16(((u16)p_hwfn->ufp_info.tc << 13)); |
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| 607 | 586 | |
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| 608 | 587 | return qed_spq_post(p_hwfn, p_ent, NULL); |
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| 609 | 588 | } |
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