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2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc 
 kernel/drivers/net/ethernet/qlogic/qed/qed_l2.c
....@@ -1,33 +1,7 @@
1
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
12 /* QLogic qed NIC Driver
23  * Copyright (c) 2015-2017  QLogic Corporation
3
- *
4
- * This software is available to you under a choice of one of two
5
- * licenses.  You may choose to be licensed under the terms of the GNU
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- * General Public License (GPL) Version 2, available from the file
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- * COPYING in the main directory of this source tree, or the
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- * OpenIB.org BSD license below:
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- *
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- *     Redistribution and use in source and binary forms, with or
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- *     without modification, are permitted provided that the following
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- *     conditions are met:
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- *
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- *      - Redistributions of source code must retain the above
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- *        copyright notice, this list of conditions and the following
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- *        disclaimer.
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- *
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- *      - Redistributions in binary form must reproduce the above
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- *        copyright notice, this list of conditions and the following
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- *        disclaimer in the documentation and /or other materials
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- *        provided with the distribution.
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- *
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- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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- * SOFTWARE.
4
+ * Copyright (c) 2019-2020 Marvell International Ltd.
315  */
326 
337 #include <linux/types.h>
....@@ -50,6 +24,7 @@
5024 #include "qed.h"
5125 #include <linux/qed/qed_chain.h>
5226 #include "qed_cxt.h"
27
+#include "qed_dcbx.h"
5328 #include "qed_dev_api.h"
5429 #include <linux/qed/qed_eth_if.h>
5530 #include "qed_hsi.h"
....@@ -57,6 +32,7 @@
5732 #include "qed_int.h"
5833 #include "qed_l2.h"
5934 #include "qed_mcp.h"
35
+#include "qed_ptp.h"
6036 #include "qed_reg_addr.h"
6137 #include "qed_sp.h"
6238 #include "qed_sriov.h"
....@@ -366,11 +342,12 @@
366342 			   struct qed_sp_vport_start_params *p_params)
367343 {
368344 	struct vport_start_ramrod_data *p_ramrod = NULL;
345
+	struct eth_vport_tpa_param *tpa_param;
369346 	struct qed_spq_entry *p_ent =  NULL;
370347 	struct qed_sp_init_data init_data;
348
+	u16 min_size, rx_mode = 0;
371349 	u8 abs_vport_id = 0;
372
-	int rc = -EINVAL;
373
-	u16 rx_mode = 0;
350
+	int rc;
374351 
375352 	rc = qed_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id);
376353 	if (rc)
....@@ -402,21 +379,23 @@
402379 	p_ramrod->rx_mode.state = cpu_to_le16(rx_mode);
403380 
404381 	/* TPA related fields */
405
-	memset(&p_ramrod->tpa_param, 0, sizeof(struct eth_vport_tpa_param));
382
+	tpa_param = &p_ramrod->tpa_param;
383
+	memset(tpa_param, 0, sizeof(*tpa_param));
406384 
407
-	p_ramrod->tpa_param.max_buff_num = p_params->max_buffers_per_cqe;
385
+	tpa_param->max_buff_num = p_params->max_buffers_per_cqe;
408386 
409387 	switch (p_params->tpa_mode) {
410388 	case QED_TPA_MODE_GRO:
411
-		p_ramrod->tpa_param.tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
412
-		p_ramrod->tpa_param.tpa_max_size = (u16)-1;
413
-		p_ramrod->tpa_param.tpa_min_size_to_cont = p_params->mtu / 2;
414
-		p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
415
-		p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
416
-		p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
417
-		p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
418
-		p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
419
-		break;
389
+		min_size = p_params->mtu / 2;
390
+
391
+		tpa_param->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
392
+		tpa_param->tpa_max_size = cpu_to_le16(U16_MAX);
393
+		tpa_param->tpa_min_size_to_cont = cpu_to_le16(min_size);
394
+		tpa_param->tpa_min_size_to_start = cpu_to_le16(min_size);
395
+		tpa_param->tpa_ipv4_en_flg = 1;
396
+		tpa_param->tpa_ipv6_en_flg = 1;
397
+		tpa_param->tpa_pkt_split_flg = 1;
398
+		tpa_param->tpa_gro_consistent_flg = 1;
420399 	default:
421400 		break;
422401 	}
....@@ -625,33 +604,33 @@
625604 static void
626605 qed_sp_vport_update_sge_tpa(struct qed_hwfn *p_hwfn,
627606 			    struct vport_update_ramrod_data *p_ramrod,
628
-			    struct qed_sge_tpa_params *p_params)
607
+			    const struct qed_sge_tpa_params *param)
629608 {
630
-	struct eth_vport_tpa_param *p_tpa;
609
+	struct eth_vport_tpa_param *tpa;
631610 
632
-	if (!p_params) {
611
+	if (!param) {
633612 		p_ramrod->common.update_tpa_param_flg = 0;
634613 		p_ramrod->common.update_tpa_en_flg = 0;
635614 		p_ramrod->common.update_tpa_param_flg = 0;
636615 		return;
637616 	}
638617 
639
-	p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg;
640
-	p_tpa = &p_ramrod->tpa_param;
641
-	p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg;
642
-	p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg;
643
-	p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg;
644
-	p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg;
618
+	p_ramrod->common.update_tpa_en_flg = param->update_tpa_en_flg;
619
+	tpa = &p_ramrod->tpa_param;
620
+	tpa->tpa_ipv4_en_flg = param->tpa_ipv4_en_flg;
621
+	tpa->tpa_ipv6_en_flg = param->tpa_ipv6_en_flg;
622
+	tpa->tpa_ipv4_tunn_en_flg = param->tpa_ipv4_tunn_en_flg;
623
+	tpa->tpa_ipv6_tunn_en_flg = param->tpa_ipv6_tunn_en_flg;
645624 
646
-	p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg;
647
-	p_tpa->max_buff_num = p_params->max_buffers_per_cqe;
648
-	p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg;
649
-	p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg;
650
-	p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg;
651
-	p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num;
652
-	p_tpa->tpa_max_size = p_params->tpa_max_size;
653
-	p_tpa->tpa_min_size_to_start = p_params->tpa_min_size_to_start;
654
-	p_tpa->tpa_min_size_to_cont = p_params->tpa_min_size_to_cont;
625
+	p_ramrod->common.update_tpa_param_flg = param->update_tpa_param_flg;
626
+	tpa->max_buff_num = param->max_buffers_per_cqe;
627
+	tpa->tpa_pkt_split_flg = param->tpa_pkt_split_flg;
628
+	tpa->tpa_hdr_data_split_flg = param->tpa_hdr_data_split_flg;
629
+	tpa->tpa_gro_consistent_flg = param->tpa_gro_consistent_flg;
630
+	tpa->tpa_max_aggs_num = param->tpa_max_aggs_num;
631
+	tpa->tpa_max_size = cpu_to_le16(param->tpa_max_size);
632
+	tpa->tpa_min_size_to_start = cpu_to_le16(param->tpa_min_size_to_start);
633
+	tpa->tpa_min_size_to_cont = cpu_to_le16(param->tpa_min_size_to_cont);
655634 }
656635 
657636 static void
....@@ -1894,6 +1873,7 @@
18941873 		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
18951874 		struct qed_ptt *p_ptt = IS_PF(cdev) ? qed_ptt_acquire(p_hwfn)
18961875 						    :  NULL;
1876
+		bool b_get_port_stats;
18971877 
18981878 		if (IS_PF(cdev)) {
18991879 			/* The main vport index is relative first */
....@@ -1908,8 +1888,9 @@
19081888 			continue;
19091889 		}
19101890 
1891
+		b_get_port_stats = IS_PF(cdev) && IS_LEAD_HWFN(p_hwfn);
19111892 		__qed_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport,
1912
-				      IS_PF(cdev) ? true : false);
1893
+				      b_get_port_stats);
19131894 
19141895 out:
19151896 		if (IS_PF(cdev) && p_ptt)
....@@ -1921,7 +1902,7 @@
19211902 {
19221903 	u32 i;
19231904 
1924
-	if (!cdev) {
1905
+	if (!cdev || cdev->recov_in_prog) {
19251906 		memset(stats, 0, sizeof(*stats));
19261907 		return;
19271908 	}
....@@ -1999,6 +1980,9 @@
19991980 			     struct qed_ptt *p_ptt,
20001981 			     struct qed_arfs_config_params *p_cfg_params)
20011982 {
1983
+	if (test_bit(QED_MF_DISABLE_ARFS, &p_hwfn->cdev->mf_bits))
1984
+		return;
1985
+
20021986 	if (p_cfg_params->mode != QED_FILTER_CONFIG_MODE_DISABLE) {
20031987 		qed_gft_config(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
20041988 			       p_cfg_params->tcp,
....@@ -2105,13 +2089,14 @@
21052089 
21062090 	rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
21072091 			       p_cid->sb_igu_id * sizeof(u64),
2108
-			       (u64)(uintptr_t)&sb_entry, 2, 0);
2092
+			       (u64)(uintptr_t)&sb_entry, 2, NULL);
21092093 	if (rc) {
21102094 		DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
21112095 		return rc;
21122096 	}
21132097 
2114
-	timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0);
2098
+	timer_res = GET_FIELD(le32_to_cpu(sb_entry.params),
2099
+			      CAU_SB_ENTRY_TIMER_RES0);
21152100 
21162101 	address = BAR0_MAP_REG_USDM_RAM +
21172102 		  USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
....@@ -2138,13 +2123,14 @@
21382123 
21392124 	rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
21402125 			       p_cid->sb_igu_id * sizeof(u64),
2141
-			       (u64)(uintptr_t)&sb_entry, 2, 0);
2126
+			       (u64)(uintptr_t)&sb_entry, 2, NULL);
21422127 	if (rc) {
21432128 		DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
21442129 		return rc;
21452130 	}
21462131 
2147
-	timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1);
2132
+	timer_res = GET_FIELD(le32_to_cpu(sb_entry.params),
2133
+			      CAU_SB_ENTRY_TIMER_RES1);
21482134 
21492135 	address = BAR0_MAP_REG_XSDM_RAM +
21502136 		  XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
....@@ -2867,7 +2853,8 @@
28672853 	p_hwfn = p_cid->p_owner;
28682854 	rc = qed_get_queue_coalesce(p_hwfn, coal, handle);
28692855 	if (rc)
2870
-		DP_NOTICE(p_hwfn, "Unable to read queue coalescing\n");
2856
+		DP_VERBOSE(cdev, QED_MSG_DEBUG,
2857
+			   "Unable to read queue coalescing\n");
28712858 
28722859 	return rc;
28732860 }
....@@ -2896,16 +2883,6 @@
28962883 
28972884 	return 0;
28982885 }
2899
-
2900
-#ifdef CONFIG_QED_SRIOV
2901
-extern const struct qed_iov_hv_ops qed_iov_ops_pass;
2902
-#endif
2903
-
2904
-#ifdef CONFIG_DCB
2905
-extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
2906
-#endif
2907
-
2908
-extern const struct qed_eth_ptp_ops qed_ptp_ops_pass;
29092886 
29102887 static const struct qed_eth_ops qed_eth_ops_pass = {
29112888 	.common = &qed_common_ops_pass,