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2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc 
 kernel/drivers/net/ethernet/qlogic/qed/qed_debug.c
....@@ -1,15 +1,14 @@
1
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
12 /* QLogic qed NIC Driver
23  * Copyright (c) 2015 QLogic Corporation
3
- *
4
- * This software is available under the terms of the GNU General Public License
5
- * (GPL) Version 2, available from the file COPYING in the main directory of
6
- * this source tree.
4
+ * Copyright (c) 2019-2020 Marvell International Ltd.
75  */
86 
97 #include <linux/module.h>
108 #include <linux/vmalloc.h>
119 #include <linux/crc32.h>
1210 #include "qed.h"
11
+#include "qed_cxt.h"
1312 #include "qed_hsi.h"
1413 #include "qed_hw.h"
1514 #include "qed_mcp.h"
....@@ -25,27 +24,28 @@
2524 	MEM_GROUP_BRB_RAM,
2625 	MEM_GROUP_BRB_MEM,
2726 	MEM_GROUP_PRS_MEM,
28
-	MEM_GROUP_IOR,
29
-	MEM_GROUP_BTB_RAM,
30
-	MEM_GROUP_CONN_CFC_MEM,
31
-	MEM_GROUP_TASK_CFC_MEM,
32
-	MEM_GROUP_CAU_PI,
33
-	MEM_GROUP_CAU_MEM,
34
-	MEM_GROUP_PXP_ILT,
35
-	MEM_GROUP_TM_MEM,
3627 	MEM_GROUP_SDM_MEM,
3728 	MEM_GROUP_PBUF,
29
+	MEM_GROUP_IOR,
3830 	MEM_GROUP_RAM,
39
-	MEM_GROUP_MULD_MEM,
40
-	MEM_GROUP_BTB_MEM,
31
+	MEM_GROUP_BTB_RAM,
4132 	MEM_GROUP_RDIF_CTX,
4233 	MEM_GROUP_TDIF_CTX,
4334 	MEM_GROUP_CFC_MEM,
35
+	MEM_GROUP_CONN_CFC_MEM,
36
+	MEM_GROUP_CAU_PI,
37
+	MEM_GROUP_CAU_MEM,
38
+	MEM_GROUP_CAU_MEM_EXT,
39
+	MEM_GROUP_PXP_ILT,
40
+	MEM_GROUP_MULD_MEM,
41
+	MEM_GROUP_BTB_MEM,
4442 	MEM_GROUP_IGU_MEM,
4543 	MEM_GROUP_IGU_MSIX,
4644 	MEM_GROUP_CAU_SB,
4745 	MEM_GROUP_BMB_RAM,
4846 	MEM_GROUP_BMB_MEM,
47
+	MEM_GROUP_TM_MEM,
48
+	MEM_GROUP_TASK_CFC_MEM,
4949 	MEM_GROUPS_NUM
5050 };
5151 
....@@ -59,27 +59,28 @@
5959 	"BRB_RAM",
6060 	"BRB_MEM",
6161 	"PRS_MEM",
62
-	"IOR",
63
-	"BTB_RAM",
64
-	"CONN_CFC_MEM",
65
-	"TASK_CFC_MEM",
66
-	"CAU_PI",
67
-	"CAU_MEM",
68
-	"PXP_ILT",
69
-	"TM_MEM",
7062 	"SDM_MEM",
7163 	"PBUF",
64
+	"IOR",
7265 	"RAM",
73
-	"MULD_MEM",
74
-	"BTB_MEM",
66
+	"BTB_RAM",
7567 	"RDIF_CTX",
7668 	"TDIF_CTX",
7769 	"CFC_MEM",
70
+	"CONN_CFC_MEM",
71
+	"CAU_PI",
72
+	"CAU_MEM",
73
+	"CAU_MEM_EXT",
74
+	"PXP_ILT",
75
+	"MULD_MEM",
76
+	"BTB_MEM",
7877 	"IGU_MEM",
7978 	"IGU_MSIX",
8079 	"CAU_SB",
8180 	"BMB_RAM",
8281 	"BMB_MEM",
82
+	"TM_MEM",
83
+	"TASK_CFC_MEM",
8384 };
8485 
8586 /* Idle check conditions */
....@@ -173,27 +174,58 @@
173174 	cond13,
174175 };
175176 
177
+#define NUM_PHYS_BLOCKS 84
178
+
179
+#define NUM_DBG_RESET_REGS 8
180
+
176181 /******************************* Data Types **********************************/
177182 
178
-enum platform_ids {
179
-	PLATFORM_ASIC,
183
+enum hw_types {
184
+	HW_TYPE_ASIC,
180185 	PLATFORM_RESERVED,
181186 	PLATFORM_RESERVED2,
182187 	PLATFORM_RESERVED3,
183
-	MAX_PLATFORM_IDS
188
+	PLATFORM_RESERVED4,
189
+	MAX_HW_TYPES
190
+};
191
+
192
+/* CM context types */
193
+enum cm_ctx_types {
194
+	CM_CTX_CONN_AG,
195
+	CM_CTX_CONN_ST,
196
+	CM_CTX_TASK_AG,
197
+	CM_CTX_TASK_ST,
198
+	NUM_CM_CTX_TYPES
199
+};
200
+
201
+/* Debug bus frame modes */
202
+enum dbg_bus_frame_modes {
203
+	DBG_BUS_FRAME_MODE_4ST = 0,	/* 4 Storm dwords (no HW) */
204
+	DBG_BUS_FRAME_MODE_2ST_2HW = 1,	/* 2 Storm dwords, 2 HW dwords */
205
+	DBG_BUS_FRAME_MODE_1ST_3HW = 2,	/* 1 Storm dwords, 3 HW dwords */
206
+	DBG_BUS_FRAME_MODE_4HW = 3,	/* 4 HW dwords (no Storms) */
207
+	DBG_BUS_FRAME_MODE_8HW = 4,	/* 8 HW dwords (no Storms) */
208
+	DBG_BUS_NUM_FRAME_MODES
184209 };
185210 
186211 /* Chip constant definitions */
187212 struct chip_defs {
188213 	const char *name;
214
+	u32 num_ilt_pages;
189215 };
190216 
191
-/* Platform constant definitions */
192
-struct platform_defs {
217
+/* HW type constant definitions */
218
+struct hw_type_defs {
193219 	const char *name;
194220 	u32 delay_factor;
195221 	u32 dmae_thresh;
196222 	u32 log_thresh;
223
+};
224
+
225
+/* RBC reset definitions */
226
+struct rbc_reset_defs {
227
+	u32 reset_reg_addr;
228
+	u32 reset_val[MAX_CHIP_IDS];
197229 };
198230 
199231 /* Storm constant definitions.
....@@ -201,7 +233,7 @@
201233  */
202234 struct storm_defs {
203235 	char letter;
204
-	enum block_id block_id;
236
+	enum block_id sem_block_id;
205237 	enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS];
206238 	bool has_vfc;
207239 	u32 sem_fast_mem_addr;
....@@ -210,47 +242,26 @@
210242 	u32 sem_slow_mode_addr;
211243 	u32 sem_slow_mode1_conf_addr;
212244 	u32 sem_sync_dbg_empty_addr;
213
-	u32 sem_slow_dbg_empty_addr;
245
+	u32 sem_gpre_vect_addr;
214246 	u32 cm_ctx_wr_addr;
215
-	u32 cm_conn_ag_ctx_lid_size;
216
-	u32 cm_conn_ag_ctx_rd_addr;
217
-	u32 cm_conn_st_ctx_lid_size;
218
-	u32 cm_conn_st_ctx_rd_addr;
219
-	u32 cm_task_ag_ctx_lid_size;
220
-	u32 cm_task_ag_ctx_rd_addr;
221
-	u32 cm_task_st_ctx_lid_size;
222
-	u32 cm_task_st_ctx_rd_addr;
247
+	u32 cm_ctx_rd_addr[NUM_CM_CTX_TYPES];
248
+	u32 cm_ctx_lid_sizes[MAX_CHIP_IDS][NUM_CM_CTX_TYPES];
223249 };
224250 
225
-/* Block constant definitions */
226
-struct block_defs {
251
+/* Debug Bus Constraint operation constant definitions */
252
+struct dbg_bus_constraint_op_defs {
253
+	u8 hw_op_val;
254
+	bool is_cyclic;
255
+};
256
+
257
+/* Storm Mode definitions */
258
+struct storm_mode_defs {
227259 	const char *name;
260
+	bool is_fast_dbg;
261
+	u8 id_in_hw;
262
+	u32 src_disable_reg_addr;
263
+	u32 src_enable_val;
228264 	bool exists[MAX_CHIP_IDS];
229
-	bool associated_to_storm;
230
-
231
-	/* Valid only if associated_to_storm is true */
232
-	u32 storm_id;
233
-	enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS];
234
-	u32 dbg_select_addr;
235
-	u32 dbg_enable_addr;
236
-	u32 dbg_shift_addr;
237
-	u32 dbg_force_valid_addr;
238
-	u32 dbg_force_frame_addr;
239
-	bool has_reset_bit;
240
-
241
-	/* If true, block is taken out of reset before dump */
242
-	bool unreset;
243
-	enum dbg_reset_regs reset_reg;
244
-
245
-	/* Bit offset in reset register */
246
-	u8 reset_bit_offset;
247
-};
248
-
249
-/* Reset register definitions */
250
-struct reset_reg_defs {
251
-	u32 addr;
252
-	bool exists[MAX_CHIP_IDS];
253
-	u32 unreset_val[MAX_CHIP_IDS];
254265 };
255266 
256267 struct grc_param_defs {
....@@ -260,7 +271,7 @@
260271 	bool is_preset;
261272 	bool is_persistent;
262273 	u32 exclude_all_preset_val;
263
-	u32 crash_preset_val;
274
+	u32 crash_preset_val[MAX_CHIP_IDS];
264275 };
265276 
266277 /* Address is in 128b units. Width is in bits. */
....@@ -317,15 +328,7 @@
317328 
318329 /******************************** Constants **********************************/
319330 
320
-#define MAX_LCIDS			320
321
-#define MAX_LTIDS			320
322
-
323
-#define NUM_IOR_SETS			2
324
-#define IORS_PER_SET			176
325
-#define IOR_SET_OFFSET(set_id)		((set_id) * 256)
326
-
327331 #define BYTES_IN_DWORD			sizeof(u32)
328
-
329332 /* In the macros below, size and offset are specified in bits */
330333 #define CEIL_DWORDS(size)		DIV_ROUND_UP(size, 32)
331334 #define FIELD_BIT_OFFSET(type, field)	type ## _ ## field ## _ ## OFFSET
....@@ -351,20 +354,17 @@
351354 			qed_wr(dev, ptt, addr,	(arr)[i]); \
352355 	} while (0)
353356 
354
-#define ARR_REG_RD(dev, ptt, addr, arr, arr_size) \
355
-	do { \
356
-		for (i = 0; i < (arr_size); i++) \
357
-			(arr)[i] = qed_rd(dev, ptt, addr); \
358
-	} while (0)
359
-
360357 #define DWORDS_TO_BYTES(dwords)		((dwords) * BYTES_IN_DWORD)
361358 #define BYTES_TO_DWORDS(bytes)		((bytes) / BYTES_IN_DWORD)
362359 
363
-/* Extra lines include a signature line + optional latency events line */
364
-#define NUM_EXTRA_DBG_LINES(block_desc) \
365
-	(1 + ((block_desc)->has_latency_events ? 1 : 0))
366
-#define NUM_DBG_LINES(block_desc) \
367
-	((block_desc)->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc))
360
+/* extra lines include a signature line + optional latency events line */
361
+#define NUM_EXTRA_DBG_LINES(block) \
362
+	(GET_FIELD((block)->flags, DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS) ? 2 : 1)
363
+#define NUM_DBG_LINES(block) \
364
+	((block)->num_of_dbg_bus_lines + NUM_EXTRA_DBG_LINES(block))
365
+
366
+#define USE_DMAE			true
367
+#define PROTECT_WIDE_BUS		true
368368 
369369 #define RAM_LINES_TO_DWORDS(lines)	((lines) * 2)
370370 #define RAM_LINES_TO_BYTES(lines) \
....@@ -382,6 +382,9 @@
382382 
383383 #define IDLE_CHK_RESULT_REG_HDR_DWORDS \
384384 	BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_reg_hdr))
385
+
386
+#define PAGE_MEM_DESC_SIZE_DWORDS \
387
+	BYTES_TO_DWORDS(sizeof(struct phys_mem_desc))
385388 
386389 #define IDLE_CHK_MAX_ENTRIES_SIZE	32
387390 
....@@ -428,7 +431,9 @@
428431 
429432 #define STATIC_DEBUG_LINE_DWORDS	9
430433 
431
-#define NUM_COMMON_GLOBAL_PARAMS	8
434
+#define NUM_COMMON_GLOBAL_PARAMS	9
435
+
436
+#define MAX_RECURSION_DEPTH		10
432437 
433438 #define FW_IMG_MAIN			1
434439 
....@@ -452,1054 +457,121 @@
452457 	(MCP_REG_SCRATCH + \
453458 	 offsetof(struct static_init, sections[SPAD_SECTION_TRACE]))
454459 
460
+#define MAX_SW_PLTAFORM_STR_SIZE	64
461
+
455462 #define EMPTY_FW_VERSION_STR		"???_???_???_???"
456463 #define EMPTY_FW_IMAGE_STR		"???????????????"
457464 
458465 /***************************** Constant Arrays *******************************/
459466 
460
-struct dbg_array {
461
-	const u32 *ptr;
462
-	u32 size_in_dwords;
463
-};
464
-
465
-/* Debug arrays */
466
-static struct dbg_array s_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { {NULL} };
467
-
468467 /* Chip constant definitions array */
469468 static struct chip_defs s_chip_defs[MAX_CHIP_IDS] = {
470
-	{"bb"},
471
-	{"ah"},
472
-	{"reserved"},
469
+	{"bb", PSWRQ2_REG_ILT_MEMORY_SIZE_BB / 2},
470
+	{"ah", PSWRQ2_REG_ILT_MEMORY_SIZE_K2 / 2}
473471 };
474472 
475473 /* Storm constant definitions array */
476474 static struct storm_defs s_storm_defs[] = {
477475 	/* Tstorm */
478476 	{'T', BLOCK_TSEM,
479
-	 {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT,
480
-	  DBG_BUS_CLIENT_RBCT}, true,
481
-	 TSEM_REG_FAST_MEMORY,
482
-	 TSEM_REG_DBG_FRAME_MODE_BB_K2, TSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
483
-	 TSEM_REG_SLOW_DBG_MODE_BB_K2, TSEM_REG_DBG_MODE1_CFG_BB_K2,
484
-	 TSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2,
485
-	 TCM_REG_CTX_RBC_ACCS,
486
-	 4, TCM_REG_AGG_CON_CTX,
487
-	 16, TCM_REG_SM_CON_CTX,
488
-	 2, TCM_REG_AGG_TASK_CTX,
489
-	 4, TCM_REG_SM_TASK_CTX},
477
+		{DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
478
+		true,
479
+		TSEM_REG_FAST_MEMORY,
480
+		TSEM_REG_DBG_FRAME_MODE_BB_K2, TSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
481
+		TSEM_REG_SLOW_DBG_MODE_BB_K2, TSEM_REG_DBG_MODE1_CFG_BB_K2,
482
+		TSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_DBG_GPRE_VECT,
483
+		TCM_REG_CTX_RBC_ACCS,
484
+		{TCM_REG_AGG_CON_CTX, TCM_REG_SM_CON_CTX, TCM_REG_AGG_TASK_CTX,
485
+		 TCM_REG_SM_TASK_CTX},
486
+		{{4, 16, 2, 4}, {4, 16, 2, 4}} /* {bb} {k2} */
487
+	},
490488 
491489 	/* Mstorm */
492490 	{'M', BLOCK_MSEM,
493
-	 {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM,
494
-	  DBG_BUS_CLIENT_RBCM}, false,
495
-	 MSEM_REG_FAST_MEMORY,
496
-	 MSEM_REG_DBG_FRAME_MODE_BB_K2, MSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
497
-	 MSEM_REG_SLOW_DBG_MODE_BB_K2, MSEM_REG_DBG_MODE1_CFG_BB_K2,
498
-	 MSEM_REG_SYNC_DBG_EMPTY, MSEM_REG_SLOW_DBG_EMPTY_BB_K2,
499
-	 MCM_REG_CTX_RBC_ACCS,
500
-	 1, MCM_REG_AGG_CON_CTX,
501
-	 10, MCM_REG_SM_CON_CTX,
502
-	 2, MCM_REG_AGG_TASK_CTX,
503
-	 7, MCM_REG_SM_TASK_CTX},
491
+		{DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM},
492
+		false,
493
+		MSEM_REG_FAST_MEMORY,
494
+		MSEM_REG_DBG_FRAME_MODE_BB_K2,
495
+		MSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
496
+		MSEM_REG_SLOW_DBG_MODE_BB_K2,
497
+		MSEM_REG_DBG_MODE1_CFG_BB_K2,
498
+		MSEM_REG_SYNC_DBG_EMPTY,
499
+		MSEM_REG_DBG_GPRE_VECT,
500
+		MCM_REG_CTX_RBC_ACCS,
501
+		{MCM_REG_AGG_CON_CTX, MCM_REG_SM_CON_CTX, MCM_REG_AGG_TASK_CTX,
502
+		 MCM_REG_SM_TASK_CTX },
503
+		{{1, 10, 2, 7}, {1, 10, 2, 7}} /* {bb} {k2}*/
504
+	},
504505 
505506 	/* Ustorm */
506507 	{'U', BLOCK_USEM,
507
-	 {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU,
508
-	  DBG_BUS_CLIENT_RBCU}, false,
509
-	 USEM_REG_FAST_MEMORY,
510
-	 USEM_REG_DBG_FRAME_MODE_BB_K2, USEM_REG_SLOW_DBG_ACTIVE_BB_K2,
511
-	 USEM_REG_SLOW_DBG_MODE_BB_K2, USEM_REG_DBG_MODE1_CFG_BB_K2,
512
-	 USEM_REG_SYNC_DBG_EMPTY, USEM_REG_SLOW_DBG_EMPTY_BB_K2,
513
-	 UCM_REG_CTX_RBC_ACCS,
514
-	 2, UCM_REG_AGG_CON_CTX,
515
-	 13, UCM_REG_SM_CON_CTX,
516
-	 3, UCM_REG_AGG_TASK_CTX,
517
-	 3, UCM_REG_SM_TASK_CTX},
508
+		{DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
509
+		false,
510
+		USEM_REG_FAST_MEMORY,
511
+		USEM_REG_DBG_FRAME_MODE_BB_K2,
512
+		USEM_REG_SLOW_DBG_ACTIVE_BB_K2,
513
+		USEM_REG_SLOW_DBG_MODE_BB_K2,
514
+		USEM_REG_DBG_MODE1_CFG_BB_K2,
515
+		USEM_REG_SYNC_DBG_EMPTY,
516
+		USEM_REG_DBG_GPRE_VECT,
517
+		UCM_REG_CTX_RBC_ACCS,
518
+		{UCM_REG_AGG_CON_CTX, UCM_REG_SM_CON_CTX, UCM_REG_AGG_TASK_CTX,
519
+		 UCM_REG_SM_TASK_CTX},
520
+		{{2, 13, 3, 3}, {2, 13, 3, 3}} /* {bb} {k2} */
521
+	},
518522 
519523 	/* Xstorm */
520524 	{'X', BLOCK_XSEM,
521
-	 {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX,
522
-	  DBG_BUS_CLIENT_RBCX}, false,
523
-	 XSEM_REG_FAST_MEMORY,
524
-	 XSEM_REG_DBG_FRAME_MODE_BB_K2, XSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
525
-	 XSEM_REG_SLOW_DBG_MODE_BB_K2, XSEM_REG_DBG_MODE1_CFG_BB_K2,
526
-	 XSEM_REG_SYNC_DBG_EMPTY, XSEM_REG_SLOW_DBG_EMPTY_BB_K2,
527
-	 XCM_REG_CTX_RBC_ACCS,
528
-	 9, XCM_REG_AGG_CON_CTX,
529
-	 15, XCM_REG_SM_CON_CTX,
530
-	 0, 0,
531
-	 0, 0},
525
+		{DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
526
+		false,
527
+		XSEM_REG_FAST_MEMORY,
528
+		XSEM_REG_DBG_FRAME_MODE_BB_K2,
529
+		XSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
530
+		XSEM_REG_SLOW_DBG_MODE_BB_K2,
531
+		XSEM_REG_DBG_MODE1_CFG_BB_K2,
532
+		XSEM_REG_SYNC_DBG_EMPTY,
533
+		XSEM_REG_DBG_GPRE_VECT,
534
+		XCM_REG_CTX_RBC_ACCS,
535
+		{XCM_REG_AGG_CON_CTX, XCM_REG_SM_CON_CTX, 0, 0},
536
+		{{9, 15, 0, 0}, {9, 15,	0, 0}} /* {bb} {k2} */
537
+	},
532538 
533539 	/* Ystorm */
534540 	{'Y', BLOCK_YSEM,
535
-	 {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY,
536
-	  DBG_BUS_CLIENT_RBCY}, false,
537
-	 YSEM_REG_FAST_MEMORY,
538
-	 YSEM_REG_DBG_FRAME_MODE_BB_K2, YSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
539
-	 YSEM_REG_SLOW_DBG_MODE_BB_K2, YSEM_REG_DBG_MODE1_CFG_BB_K2,
540
-	 YSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2,
541
-	 YCM_REG_CTX_RBC_ACCS,
542
-	 2, YCM_REG_AGG_CON_CTX,
543
-	 3, YCM_REG_SM_CON_CTX,
544
-	 2, YCM_REG_AGG_TASK_CTX,
545
-	 12, YCM_REG_SM_TASK_CTX},
541
+		{DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY},
542
+		false,
543
+		YSEM_REG_FAST_MEMORY,
544
+		YSEM_REG_DBG_FRAME_MODE_BB_K2,
545
+		YSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
546
+		YSEM_REG_SLOW_DBG_MODE_BB_K2,
547
+		YSEM_REG_DBG_MODE1_CFG_BB_K2,
548
+		YSEM_REG_SYNC_DBG_EMPTY,
549
+		YSEM_REG_DBG_GPRE_VECT,
550
+		YCM_REG_CTX_RBC_ACCS,
551
+		{YCM_REG_AGG_CON_CTX, YCM_REG_SM_CON_CTX, YCM_REG_AGG_TASK_CTX,
552
+		 YCM_REG_SM_TASK_CTX},
553
+		{{2, 3, 2, 12}, {2, 3, 2, 12}} /* {bb} {k2} */
554
+	},
546555 
547556 	/* Pstorm */
548557 	{'P', BLOCK_PSEM,
549
-	 {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS,
550
-	  DBG_BUS_CLIENT_RBCS}, true,
551
-	 PSEM_REG_FAST_MEMORY,
552
-	 PSEM_REG_DBG_FRAME_MODE_BB_K2, PSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
553
-	 PSEM_REG_SLOW_DBG_MODE_BB_K2, PSEM_REG_DBG_MODE1_CFG_BB_K2,
554
-	 PSEM_REG_SYNC_DBG_EMPTY, PSEM_REG_SLOW_DBG_EMPTY_BB_K2,
555
-	 PCM_REG_CTX_RBC_ACCS,
556
-	 0, 0,
557
-	 10, PCM_REG_SM_CON_CTX,
558
-	 0, 0,
559
-	 0, 0}
558
+		{DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
559
+		true,
560
+		PSEM_REG_FAST_MEMORY,
561
+		PSEM_REG_DBG_FRAME_MODE_BB_K2,
562
+		PSEM_REG_SLOW_DBG_ACTIVE_BB_K2,
563
+		PSEM_REG_SLOW_DBG_MODE_BB_K2,
564
+		PSEM_REG_DBG_MODE1_CFG_BB_K2,
565
+		PSEM_REG_SYNC_DBG_EMPTY,
566
+		PSEM_REG_DBG_GPRE_VECT,
567
+		PCM_REG_CTX_RBC_ACCS,
568
+		{0, PCM_REG_SM_CON_CTX, 0, 0},
569
+		{{0, 10, 0, 0}, {0, 10, 0, 0}} /* {bb} {k2} */
570
+	},
560571 };
561572 
562
-/* Block definitions array */
563
-
564
-static struct block_defs block_grc_defs = {
565
-	"grc",
566
-	{true, true, true}, false, 0,
567
-	{DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN},
568
-	GRC_REG_DBG_SELECT, GRC_REG_DBG_DWORD_ENABLE,
569
-	GRC_REG_DBG_SHIFT, GRC_REG_DBG_FORCE_VALID,
570
-	GRC_REG_DBG_FORCE_FRAME,
571
-	true, false, DBG_RESET_REG_MISC_PL_UA, 1
572
-};
573
-
574
-static struct block_defs block_miscs_defs = {
575
-	"miscs", {true, true, true}, false, 0,
576
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
577
-	0, 0, 0, 0, 0,
578
-	false, false, MAX_DBG_RESET_REGS, 0
579
-};
580
-
581
-static struct block_defs block_misc_defs = {
582
-	"misc", {true, true, true}, false, 0,
583
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
584
-	0, 0, 0, 0, 0,
585
-	false, false, MAX_DBG_RESET_REGS, 0
586
-};
587
-
588
-static struct block_defs block_dbu_defs = {
589
-	"dbu", {true, true, true}, false, 0,
590
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
591
-	0, 0, 0, 0, 0,
592
-	false, false, MAX_DBG_RESET_REGS, 0
593
-};
594
-
595
-static struct block_defs block_pglue_b_defs = {
596
-	"pglue_b",
597
-	{true, true, true}, false, 0,
598
-	{DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH},
599
-	PGLUE_B_REG_DBG_SELECT, PGLUE_B_REG_DBG_DWORD_ENABLE,
600
-	PGLUE_B_REG_DBG_SHIFT, PGLUE_B_REG_DBG_FORCE_VALID,
601
-	PGLUE_B_REG_DBG_FORCE_FRAME,
602
-	true, false, DBG_RESET_REG_MISCS_PL_HV, 1
603
-};
604
-
605
-static struct block_defs block_cnig_defs = {
606
-	"cnig",
607
-	{true, true, true}, false, 0,
608
-	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW,
609
-	 DBG_BUS_CLIENT_RBCW},
610
-	CNIG_REG_DBG_SELECT_K2_E5, CNIG_REG_DBG_DWORD_ENABLE_K2_E5,
611
-	CNIG_REG_DBG_SHIFT_K2_E5, CNIG_REG_DBG_FORCE_VALID_K2_E5,
612
-	CNIG_REG_DBG_FORCE_FRAME_K2_E5,
613
-	true, false, DBG_RESET_REG_MISCS_PL_HV, 0
614
-};
615
-
616
-static struct block_defs block_cpmu_defs = {
617
-	"cpmu", {true, true, true}, false, 0,
618
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
619
-	0, 0, 0, 0, 0,
620
-	true, false, DBG_RESET_REG_MISCS_PL_HV, 8
621
-};
622
-
623
-static struct block_defs block_ncsi_defs = {
624
-	"ncsi",
625
-	{true, true, true}, false, 0,
626
-	{DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
627
-	NCSI_REG_DBG_SELECT, NCSI_REG_DBG_DWORD_ENABLE,
628
-	NCSI_REG_DBG_SHIFT, NCSI_REG_DBG_FORCE_VALID,
629
-	NCSI_REG_DBG_FORCE_FRAME,
630
-	true, false, DBG_RESET_REG_MISCS_PL_HV, 5
631
-};
632
-
633
-static struct block_defs block_opte_defs = {
634
-	"opte", {true, true, false}, false, 0,
635
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
636
-	0, 0, 0, 0, 0,
637
-	true, false, DBG_RESET_REG_MISCS_PL_HV, 4
638
-};
639
-
640
-static struct block_defs block_bmb_defs = {
641
-	"bmb",
642
-	{true, true, true}, false, 0,
643
-	{DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCB, DBG_BUS_CLIENT_RBCB},
644
-	BMB_REG_DBG_SELECT, BMB_REG_DBG_DWORD_ENABLE,
645
-	BMB_REG_DBG_SHIFT, BMB_REG_DBG_FORCE_VALID,
646
-	BMB_REG_DBG_FORCE_FRAME,
647
-	true, false, DBG_RESET_REG_MISCS_PL_UA, 7
648
-};
649
-
650
-static struct block_defs block_pcie_defs = {
651
-	"pcie",
652
-	{true, true, true}, false, 0,
653
-	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH,
654
-	 DBG_BUS_CLIENT_RBCH},
655
-	PCIE_REG_DBG_COMMON_SELECT_K2_E5,
656
-	PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5,
657
-	PCIE_REG_DBG_COMMON_SHIFT_K2_E5,
658
-	PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5,
659
-	PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5,
660
-	false, false, MAX_DBG_RESET_REGS, 0
661
-};
662
-
663
-static struct block_defs block_mcp_defs = {
664
-	"mcp", {true, true, true}, false, 0,
665
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
666
-	0, 0, 0, 0, 0,
667
-	false, false, MAX_DBG_RESET_REGS, 0
668
-};
669
-
670
-static struct block_defs block_mcp2_defs = {
671
-	"mcp2",
672
-	{true, true, true}, false, 0,
673
-	{DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
674
-	MCP2_REG_DBG_SELECT, MCP2_REG_DBG_DWORD_ENABLE,
675
-	MCP2_REG_DBG_SHIFT, MCP2_REG_DBG_FORCE_VALID,
676
-	MCP2_REG_DBG_FORCE_FRAME,
677
-	false, false, MAX_DBG_RESET_REGS, 0
678
-};
679
-
680
-static struct block_defs block_pswhst_defs = {
681
-	"pswhst",
682
-	{true, true, true}, false, 0,
683
-	{DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
684
-	PSWHST_REG_DBG_SELECT, PSWHST_REG_DBG_DWORD_ENABLE,
685
-	PSWHST_REG_DBG_SHIFT, PSWHST_REG_DBG_FORCE_VALID,
686
-	PSWHST_REG_DBG_FORCE_FRAME,
687
-	true, false, DBG_RESET_REG_MISC_PL_HV, 0
688
-};
689
-
690
-static struct block_defs block_pswhst2_defs = {
691
-	"pswhst2",
692
-	{true, true, true}, false, 0,
693
-	{DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
694
-	PSWHST2_REG_DBG_SELECT, PSWHST2_REG_DBG_DWORD_ENABLE,
695
-	PSWHST2_REG_DBG_SHIFT, PSWHST2_REG_DBG_FORCE_VALID,
696
-	PSWHST2_REG_DBG_FORCE_FRAME,
697
-	true, false, DBG_RESET_REG_MISC_PL_HV, 0
698
-};
699
-
700
-static struct block_defs block_pswrd_defs = {
701
-	"pswrd",
702
-	{true, true, true}, false, 0,
703
-	{DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
704
-	PSWRD_REG_DBG_SELECT, PSWRD_REG_DBG_DWORD_ENABLE,
705
-	PSWRD_REG_DBG_SHIFT, PSWRD_REG_DBG_FORCE_VALID,
706
-	PSWRD_REG_DBG_FORCE_FRAME,
707
-	true, false, DBG_RESET_REG_MISC_PL_HV, 2
708
-};
709
-
710
-static struct block_defs block_pswrd2_defs = {
711
-	"pswrd2",
712
-	{true, true, true}, false, 0,
713
-	{DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
714
-	PSWRD2_REG_DBG_SELECT, PSWRD2_REG_DBG_DWORD_ENABLE,
715
-	PSWRD2_REG_DBG_SHIFT, PSWRD2_REG_DBG_FORCE_VALID,
716
-	PSWRD2_REG_DBG_FORCE_FRAME,
717
-	true, false, DBG_RESET_REG_MISC_PL_HV, 2
718
-};
719
-
720
-static struct block_defs block_pswwr_defs = {
721
-	"pswwr",
722
-	{true, true, true}, false, 0,
723
-	{DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
724
-	PSWWR_REG_DBG_SELECT, PSWWR_REG_DBG_DWORD_ENABLE,
725
-	PSWWR_REG_DBG_SHIFT, PSWWR_REG_DBG_FORCE_VALID,
726
-	PSWWR_REG_DBG_FORCE_FRAME,
727
-	true, false, DBG_RESET_REG_MISC_PL_HV, 3
728
-};
729
-
730
-static struct block_defs block_pswwr2_defs = {
731
-	"pswwr2", {true, true, true}, false, 0,
732
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
733
-	0, 0, 0, 0, 0,
734
-	true, false, DBG_RESET_REG_MISC_PL_HV, 3
735
-};
736
-
737
-static struct block_defs block_pswrq_defs = {
738
-	"pswrq",
739
-	{true, true, true}, false, 0,
740
-	{DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
741
-	PSWRQ_REG_DBG_SELECT, PSWRQ_REG_DBG_DWORD_ENABLE,
742
-	PSWRQ_REG_DBG_SHIFT, PSWRQ_REG_DBG_FORCE_VALID,
743
-	PSWRQ_REG_DBG_FORCE_FRAME,
744
-	true, false, DBG_RESET_REG_MISC_PL_HV, 1
745
-};
746
-
747
-static struct block_defs block_pswrq2_defs = {
748
-	"pswrq2",
749
-	{true, true, true}, false, 0,
750
-	{DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
751
-	PSWRQ2_REG_DBG_SELECT, PSWRQ2_REG_DBG_DWORD_ENABLE,
752
-	PSWRQ2_REG_DBG_SHIFT, PSWRQ2_REG_DBG_FORCE_VALID,
753
-	PSWRQ2_REG_DBG_FORCE_FRAME,
754
-	true, false, DBG_RESET_REG_MISC_PL_HV, 1
755
-};
756
-
757
-static struct block_defs block_pglcs_defs = {
758
-	"pglcs",
759
-	{true, true, true}, false, 0,
760
-	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH,
761
-	 DBG_BUS_CLIENT_RBCH},
762
-	PGLCS_REG_DBG_SELECT_K2_E5, PGLCS_REG_DBG_DWORD_ENABLE_K2_E5,
763
-	PGLCS_REG_DBG_SHIFT_K2_E5, PGLCS_REG_DBG_FORCE_VALID_K2_E5,
764
-	PGLCS_REG_DBG_FORCE_FRAME_K2_E5,
765
-	true, false, DBG_RESET_REG_MISCS_PL_HV, 2
766
-};
767
-
768
-static struct block_defs block_ptu_defs = {
769
-	"ptu",
770
-	{true, true, true}, false, 0,
771
-	{DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
772
-	PTU_REG_DBG_SELECT, PTU_REG_DBG_DWORD_ENABLE,
773
-	PTU_REG_DBG_SHIFT, PTU_REG_DBG_FORCE_VALID,
774
-	PTU_REG_DBG_FORCE_FRAME,
775
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 20
776
-};
777
-
778
-static struct block_defs block_dmae_defs = {
779
-	"dmae",
780
-	{true, true, true}, false, 0,
781
-	{DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
782
-	DMAE_REG_DBG_SELECT, DMAE_REG_DBG_DWORD_ENABLE,
783
-	DMAE_REG_DBG_SHIFT, DMAE_REG_DBG_FORCE_VALID,
784
-	DMAE_REG_DBG_FORCE_FRAME,
785
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 28
786
-};
787
-
788
-static struct block_defs block_tcm_defs = {
789
-	"tcm",
790
-	{true, true, true}, true, DBG_TSTORM_ID,
791
-	{DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
792
-	TCM_REG_DBG_SELECT, TCM_REG_DBG_DWORD_ENABLE,
793
-	TCM_REG_DBG_SHIFT, TCM_REG_DBG_FORCE_VALID,
794
-	TCM_REG_DBG_FORCE_FRAME,
795
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 5
796
-};
797
-
798
-static struct block_defs block_mcm_defs = {
799
-	"mcm",
800
-	{true, true, true}, true, DBG_MSTORM_ID,
801
-	{DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
802
-	MCM_REG_DBG_SELECT, MCM_REG_DBG_DWORD_ENABLE,
803
-	MCM_REG_DBG_SHIFT, MCM_REG_DBG_FORCE_VALID,
804
-	MCM_REG_DBG_FORCE_FRAME,
805
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 3
806
-};
807
-
808
-static struct block_defs block_ucm_defs = {
809
-	"ucm",
810
-	{true, true, true}, true, DBG_USTORM_ID,
811
-	{DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
812
-	UCM_REG_DBG_SELECT, UCM_REG_DBG_DWORD_ENABLE,
813
-	UCM_REG_DBG_SHIFT, UCM_REG_DBG_FORCE_VALID,
814
-	UCM_REG_DBG_FORCE_FRAME,
815
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 8
816
-};
817
-
818
-static struct block_defs block_xcm_defs = {
819
-	"xcm",
820
-	{true, true, true}, true, DBG_XSTORM_ID,
821
-	{DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
822
-	XCM_REG_DBG_SELECT, XCM_REG_DBG_DWORD_ENABLE,
823
-	XCM_REG_DBG_SHIFT, XCM_REG_DBG_FORCE_VALID,
824
-	XCM_REG_DBG_FORCE_FRAME,
825
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 19
826
-};
827
-
828
-static struct block_defs block_ycm_defs = {
829
-	"ycm",
830
-	{true, true, true}, true, DBG_YSTORM_ID,
831
-	{DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY},
832
-	YCM_REG_DBG_SELECT, YCM_REG_DBG_DWORD_ENABLE,
833
-	YCM_REG_DBG_SHIFT, YCM_REG_DBG_FORCE_VALID,
834
-	YCM_REG_DBG_FORCE_FRAME,
835
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 5
836
-};
837
-
838
-static struct block_defs block_pcm_defs = {
839
-	"pcm",
840
-	{true, true, true}, true, DBG_PSTORM_ID,
841
-	{DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
842
-	PCM_REG_DBG_SELECT, PCM_REG_DBG_DWORD_ENABLE,
843
-	PCM_REG_DBG_SHIFT, PCM_REG_DBG_FORCE_VALID,
844
-	PCM_REG_DBG_FORCE_FRAME,
845
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 4
846
-};
847
-
848
-static struct block_defs block_qm_defs = {
849
-	"qm",
850
-	{true, true, true}, false, 0,
851
-	{DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCQ, DBG_BUS_CLIENT_RBCQ},
852
-	QM_REG_DBG_SELECT, QM_REG_DBG_DWORD_ENABLE,
853
-	QM_REG_DBG_SHIFT, QM_REG_DBG_FORCE_VALID,
854
-	QM_REG_DBG_FORCE_FRAME,
855
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 16
856
-};
857
-
858
-static struct block_defs block_tm_defs = {
859
-	"tm",
860
-	{true, true, true}, false, 0,
861
-	{DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
862
-	TM_REG_DBG_SELECT, TM_REG_DBG_DWORD_ENABLE,
863
-	TM_REG_DBG_SHIFT, TM_REG_DBG_FORCE_VALID,
864
-	TM_REG_DBG_FORCE_FRAME,
865
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 17
866
-};
867
-
868
-static struct block_defs block_dorq_defs = {
869
-	"dorq",
870
-	{true, true, true}, false, 0,
871
-	{DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY},
872
-	DORQ_REG_DBG_SELECT, DORQ_REG_DBG_DWORD_ENABLE,
873
-	DORQ_REG_DBG_SHIFT, DORQ_REG_DBG_FORCE_VALID,
874
-	DORQ_REG_DBG_FORCE_FRAME,
875
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 18
876
-};
877
-
878
-static struct block_defs block_brb_defs = {
879
-	"brb",
880
-	{true, true, true}, false, 0,
881
-	{DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR},
882
-	BRB_REG_DBG_SELECT, BRB_REG_DBG_DWORD_ENABLE,
883
-	BRB_REG_DBG_SHIFT, BRB_REG_DBG_FORCE_VALID,
884
-	BRB_REG_DBG_FORCE_FRAME,
885
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 0
886
-};
887
-
888
-static struct block_defs block_src_defs = {
889
-	"src",
890
-	{true, true, true}, false, 0,
891
-	{DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
892
-	SRC_REG_DBG_SELECT, SRC_REG_DBG_DWORD_ENABLE,
893
-	SRC_REG_DBG_SHIFT, SRC_REG_DBG_FORCE_VALID,
894
-	SRC_REG_DBG_FORCE_FRAME,
895
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 2
896
-};
897
-
898
-static struct block_defs block_prs_defs = {
899
-	"prs",
900
-	{true, true, true}, false, 0,
901
-	{DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR},
902
-	PRS_REG_DBG_SELECT, PRS_REG_DBG_DWORD_ENABLE,
903
-	PRS_REG_DBG_SHIFT, PRS_REG_DBG_FORCE_VALID,
904
-	PRS_REG_DBG_FORCE_FRAME,
905
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1
906
-};
907
-
908
-static struct block_defs block_tsdm_defs = {
909
-	"tsdm",
910
-	{true, true, true}, true, DBG_TSTORM_ID,
911
-	{DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
912
-	TSDM_REG_DBG_SELECT, TSDM_REG_DBG_DWORD_ENABLE,
913
-	TSDM_REG_DBG_SHIFT, TSDM_REG_DBG_FORCE_VALID,
914
-	TSDM_REG_DBG_FORCE_FRAME,
915
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 3
916
-};
917
-
918
-static struct block_defs block_msdm_defs = {
919
-	"msdm",
920
-	{true, true, true}, true, DBG_MSTORM_ID,
921
-	{DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
922
-	MSDM_REG_DBG_SELECT, MSDM_REG_DBG_DWORD_ENABLE,
923
-	MSDM_REG_DBG_SHIFT, MSDM_REG_DBG_FORCE_VALID,
924
-	MSDM_REG_DBG_FORCE_FRAME,
925
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 6
926
-};
927
-
928
-static struct block_defs block_usdm_defs = {
929
-	"usdm",
930
-	{true, true, true}, true, DBG_USTORM_ID,
931
-	{DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
932
-	USDM_REG_DBG_SELECT, USDM_REG_DBG_DWORD_ENABLE,
933
-	USDM_REG_DBG_SHIFT, USDM_REG_DBG_FORCE_VALID,
934
-	USDM_REG_DBG_FORCE_FRAME,
935
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 7
936
-};
937
-
938
-static struct block_defs block_xsdm_defs = {
939
-	"xsdm",
940
-	{true, true, true}, true, DBG_XSTORM_ID,
941
-	{DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
942
-	XSDM_REG_DBG_SELECT, XSDM_REG_DBG_DWORD_ENABLE,
943
-	XSDM_REG_DBG_SHIFT, XSDM_REG_DBG_FORCE_VALID,
944
-	XSDM_REG_DBG_FORCE_FRAME,
945
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 20
946
-};
947
-
948
-static struct block_defs block_ysdm_defs = {
949
-	"ysdm",
950
-	{true, true, true}, true, DBG_YSTORM_ID,
951
-	{DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY},
952
-	YSDM_REG_DBG_SELECT, YSDM_REG_DBG_DWORD_ENABLE,
953
-	YSDM_REG_DBG_SHIFT, YSDM_REG_DBG_FORCE_VALID,
954
-	YSDM_REG_DBG_FORCE_FRAME,
955
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 8
956
-};
957
-
958
-static struct block_defs block_psdm_defs = {
959
-	"psdm",
960
-	{true, true, true}, true, DBG_PSTORM_ID,
961
-	{DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
962
-	PSDM_REG_DBG_SELECT, PSDM_REG_DBG_DWORD_ENABLE,
963
-	PSDM_REG_DBG_SHIFT, PSDM_REG_DBG_FORCE_VALID,
964
-	PSDM_REG_DBG_FORCE_FRAME,
965
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 7
966
-};
967
-
968
-static struct block_defs block_tsem_defs = {
969
-	"tsem",
970
-	{true, true, true}, true, DBG_TSTORM_ID,
971
-	{DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
972
-	TSEM_REG_DBG_SELECT, TSEM_REG_DBG_DWORD_ENABLE,
973
-	TSEM_REG_DBG_SHIFT, TSEM_REG_DBG_FORCE_VALID,
974
-	TSEM_REG_DBG_FORCE_FRAME,
975
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 4
976
-};
977
-
978
-static struct block_defs block_msem_defs = {
979
-	"msem",
980
-	{true, true, true}, true, DBG_MSTORM_ID,
981
-	{DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
982
-	MSEM_REG_DBG_SELECT, MSEM_REG_DBG_DWORD_ENABLE,
983
-	MSEM_REG_DBG_SHIFT, MSEM_REG_DBG_FORCE_VALID,
984
-	MSEM_REG_DBG_FORCE_FRAME,
985
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 9
986
-};
987
-
988
-static struct block_defs block_usem_defs = {
989
-	"usem",
990
-	{true, true, true}, true, DBG_USTORM_ID,
991
-	{DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
992
-	USEM_REG_DBG_SELECT, USEM_REG_DBG_DWORD_ENABLE,
993
-	USEM_REG_DBG_SHIFT, USEM_REG_DBG_FORCE_VALID,
994
-	USEM_REG_DBG_FORCE_FRAME,
995
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 9
996
-};
997
-
998
-static struct block_defs block_xsem_defs = {
999
-	"xsem",
1000
-	{true, true, true}, true, DBG_XSTORM_ID,
1001
-	{DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
1002
-	XSEM_REG_DBG_SELECT, XSEM_REG_DBG_DWORD_ENABLE,
1003
-	XSEM_REG_DBG_SHIFT, XSEM_REG_DBG_FORCE_VALID,
1004
-	XSEM_REG_DBG_FORCE_FRAME,
1005
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 21
1006
-};
1007
-
1008
-static struct block_defs block_ysem_defs = {
1009
-	"ysem",
1010
-	{true, true, true}, true, DBG_YSTORM_ID,
1011
-	{DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY},
1012
-	YSEM_REG_DBG_SELECT, YSEM_REG_DBG_DWORD_ENABLE,
1013
-	YSEM_REG_DBG_SHIFT, YSEM_REG_DBG_FORCE_VALID,
1014
-	YSEM_REG_DBG_FORCE_FRAME,
1015
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 11
1016
-};
1017
-
1018
-static struct block_defs block_psem_defs = {
1019
-	"psem",
1020
-	{true, true, true}, true, DBG_PSTORM_ID,
1021
-	{DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
1022
-	PSEM_REG_DBG_SELECT, PSEM_REG_DBG_DWORD_ENABLE,
1023
-	PSEM_REG_DBG_SHIFT, PSEM_REG_DBG_FORCE_VALID,
1024
-	PSEM_REG_DBG_FORCE_FRAME,
1025
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 10
1026
-};
1027
-
1028
-static struct block_defs block_rss_defs = {
1029
-	"rss",
1030
-	{true, true, true}, false, 0,
1031
-	{DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT},
1032
-	RSS_REG_DBG_SELECT, RSS_REG_DBG_DWORD_ENABLE,
1033
-	RSS_REG_DBG_SHIFT, RSS_REG_DBG_FORCE_VALID,
1034
-	RSS_REG_DBG_FORCE_FRAME,
1035
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 18
1036
-};
1037
-
1038
-static struct block_defs block_tmld_defs = {
1039
-	"tmld",
1040
-	{true, true, true}, false, 0,
1041
-	{DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
1042
-	TMLD_REG_DBG_SELECT, TMLD_REG_DBG_DWORD_ENABLE,
1043
-	TMLD_REG_DBG_SHIFT, TMLD_REG_DBG_FORCE_VALID,
1044
-	TMLD_REG_DBG_FORCE_FRAME,
1045
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 13
1046
-};
1047
-
1048
-static struct block_defs block_muld_defs = {
1049
-	"muld",
1050
-	{true, true, true}, false, 0,
1051
-	{DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU},
1052
-	MULD_REG_DBG_SELECT, MULD_REG_DBG_DWORD_ENABLE,
1053
-	MULD_REG_DBG_SHIFT, MULD_REG_DBG_FORCE_VALID,
1054
-	MULD_REG_DBG_FORCE_FRAME,
1055
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 14
1056
-};
1057
-
1058
-static struct block_defs block_yuld_defs = {
1059
-	"yuld",
1060
-	{true, true, false}, false, 0,
1061
-	{DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU,
1062
-	 MAX_DBG_BUS_CLIENTS},
1063
-	YULD_REG_DBG_SELECT_BB_K2, YULD_REG_DBG_DWORD_ENABLE_BB_K2,
1064
-	YULD_REG_DBG_SHIFT_BB_K2, YULD_REG_DBG_FORCE_VALID_BB_K2,
1065
-	YULD_REG_DBG_FORCE_FRAME_BB_K2,
1066
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
1067
-	15
1068
-};
1069
-
1070
-static struct block_defs block_xyld_defs = {
1071
-	"xyld",
1072
-	{true, true, true}, false, 0,
1073
-	{DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX},
1074
-	XYLD_REG_DBG_SELECT, XYLD_REG_DBG_DWORD_ENABLE,
1075
-	XYLD_REG_DBG_SHIFT, XYLD_REG_DBG_FORCE_VALID,
1076
-	XYLD_REG_DBG_FORCE_FRAME,
1077
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 12
1078
-};
1079
-
1080
-static struct block_defs block_ptld_defs = {
1081
-	"ptld",
1082
-	{false, false, true}, false, 0,
1083
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCT},
1084
-	PTLD_REG_DBG_SELECT_E5, PTLD_REG_DBG_DWORD_ENABLE_E5,
1085
-	PTLD_REG_DBG_SHIFT_E5, PTLD_REG_DBG_FORCE_VALID_E5,
1086
-	PTLD_REG_DBG_FORCE_FRAME_E5,
1087
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
1088
-	28
1089
-};
1090
-
1091
-static struct block_defs block_ypld_defs = {
1092
-	"ypld",
1093
-	{false, false, true}, false, 0,
1094
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCS},
1095
-	YPLD_REG_DBG_SELECT_E5, YPLD_REG_DBG_DWORD_ENABLE_E5,
1096
-	YPLD_REG_DBG_SHIFT_E5, YPLD_REG_DBG_FORCE_VALID_E5,
1097
-	YPLD_REG_DBG_FORCE_FRAME_E5,
1098
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
1099
-	27
1100
-};
1101
-
1102
-static struct block_defs block_prm_defs = {
1103
-	"prm",
1104
-	{true, true, true}, false, 0,
1105
-	{DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
1106
-	PRM_REG_DBG_SELECT, PRM_REG_DBG_DWORD_ENABLE,
1107
-	PRM_REG_DBG_SHIFT, PRM_REG_DBG_FORCE_VALID,
1108
-	PRM_REG_DBG_FORCE_FRAME,
1109
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 21
1110
-};
1111
-
1112
-static struct block_defs block_pbf_pb1_defs = {
1113
-	"pbf_pb1",
1114
-	{true, true, true}, false, 0,
1115
-	{DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV},
1116
-	PBF_PB1_REG_DBG_SELECT, PBF_PB1_REG_DBG_DWORD_ENABLE,
1117
-	PBF_PB1_REG_DBG_SHIFT, PBF_PB1_REG_DBG_FORCE_VALID,
1118
-	PBF_PB1_REG_DBG_FORCE_FRAME,
1119
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
1120
-	11
1121
-};
1122
-
1123
-static struct block_defs block_pbf_pb2_defs = {
1124
-	"pbf_pb2",
1125
-	{true, true, true}, false, 0,
1126
-	{DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV},
1127
-	PBF_PB2_REG_DBG_SELECT, PBF_PB2_REG_DBG_DWORD_ENABLE,
1128
-	PBF_PB2_REG_DBG_SHIFT, PBF_PB2_REG_DBG_FORCE_VALID,
1129
-	PBF_PB2_REG_DBG_FORCE_FRAME,
1130
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
1131
-	12
1132
-};
1133
-
1134
-static struct block_defs block_rpb_defs = {
1135
-	"rpb",
1136
-	{true, true, true}, false, 0,
1137
-	{DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
1138
-	RPB_REG_DBG_SELECT, RPB_REG_DBG_DWORD_ENABLE,
1139
-	RPB_REG_DBG_SHIFT, RPB_REG_DBG_FORCE_VALID,
1140
-	RPB_REG_DBG_FORCE_FRAME,
1141
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 13
1142
-};
1143
-
1144
-static struct block_defs block_btb_defs = {
1145
-	"btb",
1146
-	{true, true, true}, false, 0,
1147
-	{DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV},
1148
-	BTB_REG_DBG_SELECT, BTB_REG_DBG_DWORD_ENABLE,
1149
-	BTB_REG_DBG_SHIFT, BTB_REG_DBG_FORCE_VALID,
1150
-	BTB_REG_DBG_FORCE_FRAME,
1151
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 10
1152
-};
1153
-
1154
-static struct block_defs block_pbf_defs = {
1155
-	"pbf",
1156
-	{true, true, true}, false, 0,
1157
-	{DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV},
1158
-	PBF_REG_DBG_SELECT, PBF_REG_DBG_DWORD_ENABLE,
1159
-	PBF_REG_DBG_SHIFT, PBF_REG_DBG_FORCE_VALID,
1160
-	PBF_REG_DBG_FORCE_FRAME,
1161
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 15
1162
-};
1163
-
1164
-static struct block_defs block_rdif_defs = {
1165
-	"rdif",
1166
-	{true, true, true}, false, 0,
1167
-	{DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM},
1168
-	RDIF_REG_DBG_SELECT, RDIF_REG_DBG_DWORD_ENABLE,
1169
-	RDIF_REG_DBG_SHIFT, RDIF_REG_DBG_FORCE_VALID,
1170
-	RDIF_REG_DBG_FORCE_FRAME,
1171
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 16
1172
-};
1173
-
1174
-static struct block_defs block_tdif_defs = {
1175
-	"tdif",
1176
-	{true, true, true}, false, 0,
1177
-	{DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS},
1178
-	TDIF_REG_DBG_SELECT, TDIF_REG_DBG_DWORD_ENABLE,
1179
-	TDIF_REG_DBG_SHIFT, TDIF_REG_DBG_FORCE_VALID,
1180
-	TDIF_REG_DBG_FORCE_FRAME,
1181
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 17
1182
-};
1183
-
1184
-static struct block_defs block_cdu_defs = {
1185
-	"cdu",
1186
-	{true, true, true}, false, 0,
1187
-	{DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
1188
-	CDU_REG_DBG_SELECT, CDU_REG_DBG_DWORD_ENABLE,
1189
-	CDU_REG_DBG_SHIFT, CDU_REG_DBG_FORCE_VALID,
1190
-	CDU_REG_DBG_FORCE_FRAME,
1191
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 23
1192
-};
1193
-
1194
-static struct block_defs block_ccfc_defs = {
1195
-	"ccfc",
1196
-	{true, true, true}, false, 0,
1197
-	{DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
1198
-	CCFC_REG_DBG_SELECT, CCFC_REG_DBG_DWORD_ENABLE,
1199
-	CCFC_REG_DBG_SHIFT, CCFC_REG_DBG_FORCE_VALID,
1200
-	CCFC_REG_DBG_FORCE_FRAME,
1201
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 24
1202
-};
1203
-
1204
-static struct block_defs block_tcfc_defs = {
1205
-	"tcfc",
1206
-	{true, true, true}, false, 0,
1207
-	{DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF},
1208
-	TCFC_REG_DBG_SELECT, TCFC_REG_DBG_DWORD_ENABLE,
1209
-	TCFC_REG_DBG_SHIFT, TCFC_REG_DBG_FORCE_VALID,
1210
-	TCFC_REG_DBG_FORCE_FRAME,
1211
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 25
1212
-};
1213
-
1214
-static struct block_defs block_igu_defs = {
1215
-	"igu",
1216
-	{true, true, true}, false, 0,
1217
-	{DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
1218
-	IGU_REG_DBG_SELECT, IGU_REG_DBG_DWORD_ENABLE,
1219
-	IGU_REG_DBG_SHIFT, IGU_REG_DBG_FORCE_VALID,
1220
-	IGU_REG_DBG_FORCE_FRAME,
1221
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 27
1222
-};
1223
-
1224
-static struct block_defs block_cau_defs = {
1225
-	"cau",
1226
-	{true, true, true}, false, 0,
1227
-	{DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP},
1228
-	CAU_REG_DBG_SELECT, CAU_REG_DBG_DWORD_ENABLE,
1229
-	CAU_REG_DBG_SHIFT, CAU_REG_DBG_FORCE_VALID,
1230
-	CAU_REG_DBG_FORCE_FRAME,
1231
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 19
1232
-};
1233
-
1234
-static struct block_defs block_rgfs_defs = {
1235
-	"rgfs", {false, false, true}, false, 0,
1236
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1237
-	0, 0, 0, 0, 0,
1238
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 29
1239
-};
1240
-
1241
-static struct block_defs block_rgsrc_defs = {
1242
-	"rgsrc",
1243
-	{false, false, true}, false, 0,
1244
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH},
1245
-	RGSRC_REG_DBG_SELECT_E5, RGSRC_REG_DBG_DWORD_ENABLE_E5,
1246
-	RGSRC_REG_DBG_SHIFT_E5, RGSRC_REG_DBG_FORCE_VALID_E5,
1247
-	RGSRC_REG_DBG_FORCE_FRAME_E5,
1248
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
1249
-	30
1250
-};
1251
-
1252
-static struct block_defs block_tgfs_defs = {
1253
-	"tgfs", {false, false, true}, false, 0,
1254
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1255
-	0, 0, 0, 0, 0,
1256
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 30
1257
-};
1258
-
1259
-static struct block_defs block_tgsrc_defs = {
1260
-	"tgsrc",
1261
-	{false, false, true}, false, 0,
1262
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCV},
1263
-	TGSRC_REG_DBG_SELECT_E5, TGSRC_REG_DBG_DWORD_ENABLE_E5,
1264
-	TGSRC_REG_DBG_SHIFT_E5, TGSRC_REG_DBG_FORCE_VALID_E5,
1265
-	TGSRC_REG_DBG_FORCE_FRAME_E5,
1266
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
1267
-	31
1268
-};
1269
-
1270
-static struct block_defs block_umac_defs = {
1271
-	"umac",
1272
-	{true, true, true}, false, 0,
1273
-	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ,
1274
-	 DBG_BUS_CLIENT_RBCZ},
1275
-	UMAC_REG_DBG_SELECT_K2_E5, UMAC_REG_DBG_DWORD_ENABLE_K2_E5,
1276
-	UMAC_REG_DBG_SHIFT_K2_E5, UMAC_REG_DBG_FORCE_VALID_K2_E5,
1277
-	UMAC_REG_DBG_FORCE_FRAME_K2_E5,
1278
-	true, false, DBG_RESET_REG_MISCS_PL_HV, 6
1279
-};
1280
-
1281
-static struct block_defs block_xmac_defs = {
1282
-	"xmac", {true, false, false}, false, 0,
1283
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1284
-	0, 0, 0, 0, 0,
1285
-	false, false, MAX_DBG_RESET_REGS, 0
1286
-};
1287
-
1288
-static struct block_defs block_dbg_defs = {
1289
-	"dbg", {true, true, true}, false, 0,
1290
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1291
-	0, 0, 0, 0, 0,
1292
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 3
1293
-};
1294
-
1295
-static struct block_defs block_nig_defs = {
1296
-	"nig",
1297
-	{true, true, true}, false, 0,
1298
-	{DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN},
1299
-	NIG_REG_DBG_SELECT, NIG_REG_DBG_DWORD_ENABLE,
1300
-	NIG_REG_DBG_SHIFT, NIG_REG_DBG_FORCE_VALID,
1301
-	NIG_REG_DBG_FORCE_FRAME,
1302
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 0
1303
-};
1304
-
1305
-static struct block_defs block_wol_defs = {
1306
-	"wol",
1307
-	{false, true, true}, false, 0,
1308
-	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
1309
-	WOL_REG_DBG_SELECT_K2_E5, WOL_REG_DBG_DWORD_ENABLE_K2_E5,
1310
-	WOL_REG_DBG_SHIFT_K2_E5, WOL_REG_DBG_FORCE_VALID_K2_E5,
1311
-	WOL_REG_DBG_FORCE_FRAME_K2_E5,
1312
-	true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 7
1313
-};
1314
-
1315
-static struct block_defs block_bmbn_defs = {
1316
-	"bmbn",
1317
-	{false, true, true}, false, 0,
1318
-	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCB,
1319
-	 DBG_BUS_CLIENT_RBCB},
1320
-	BMBN_REG_DBG_SELECT_K2_E5, BMBN_REG_DBG_DWORD_ENABLE_K2_E5,
1321
-	BMBN_REG_DBG_SHIFT_K2_E5, BMBN_REG_DBG_FORCE_VALID_K2_E5,
1322
-	BMBN_REG_DBG_FORCE_FRAME_K2_E5,
1323
-	false, false, MAX_DBG_RESET_REGS, 0
1324
-};
1325
-
1326
-static struct block_defs block_ipc_defs = {
1327
-	"ipc", {true, true, true}, false, 0,
1328
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1329
-	0, 0, 0, 0, 0,
1330
-	true, false, DBG_RESET_REG_MISCS_PL_UA, 8
1331
-};
1332
-
1333
-static struct block_defs block_nwm_defs = {
1334
-	"nwm",
1335
-	{false, true, true}, false, 0,
1336
-	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW},
1337
-	NWM_REG_DBG_SELECT_K2_E5, NWM_REG_DBG_DWORD_ENABLE_K2_E5,
1338
-	NWM_REG_DBG_SHIFT_K2_E5, NWM_REG_DBG_FORCE_VALID_K2_E5,
1339
-	NWM_REG_DBG_FORCE_FRAME_K2_E5,
1340
-	true, false, DBG_RESET_REG_MISCS_PL_HV_2, 0
1341
-};
1342
-
1343
-static struct block_defs block_nws_defs = {
1344
-	"nws",
1345
-	{false, true, true}, false, 0,
1346
-	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW},
1347
-	NWS_REG_DBG_SELECT_K2_E5, NWS_REG_DBG_DWORD_ENABLE_K2_E5,
1348
-	NWS_REG_DBG_SHIFT_K2_E5, NWS_REG_DBG_FORCE_VALID_K2_E5,
1349
-	NWS_REG_DBG_FORCE_FRAME_K2_E5,
1350
-	true, false, DBG_RESET_REG_MISCS_PL_HV, 12
1351
-};
1352
-
1353
-static struct block_defs block_ms_defs = {
1354
-	"ms",
1355
-	{false, true, true}, false, 0,
1356
-	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ},
1357
-	MS_REG_DBG_SELECT_K2_E5, MS_REG_DBG_DWORD_ENABLE_K2_E5,
1358
-	MS_REG_DBG_SHIFT_K2_E5, MS_REG_DBG_FORCE_VALID_K2_E5,
1359
-	MS_REG_DBG_FORCE_FRAME_K2_E5,
1360
-	true, false, DBG_RESET_REG_MISCS_PL_HV, 13
1361
-};
1362
-
1363
-static struct block_defs block_phy_pcie_defs = {
1364
-	"phy_pcie",
1365
-	{false, true, true}, false, 0,
1366
-	{MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH,
1367
-	 DBG_BUS_CLIENT_RBCH},
1368
-	PCIE_REG_DBG_COMMON_SELECT_K2_E5,
1369
-	PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5,
1370
-	PCIE_REG_DBG_COMMON_SHIFT_K2_E5,
1371
-	PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5,
1372
-	PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5,
1373
-	false, false, MAX_DBG_RESET_REGS, 0
1374
-};
1375
-
1376
-static struct block_defs block_led_defs = {
1377
-	"led", {false, true, true}, false, 0,
1378
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1379
-	0, 0, 0, 0, 0,
1380
-	true, false, DBG_RESET_REG_MISCS_PL_HV, 14
1381
-};
1382
-
1383
-static struct block_defs block_avs_wrap_defs = {
1384
-	"avs_wrap", {false, true, false}, false, 0,
1385
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1386
-	0, 0, 0, 0, 0,
1387
-	true, false, DBG_RESET_REG_MISCS_PL_UA, 11
1388
-};
1389
-
1390
-static struct block_defs block_pxpreqbus_defs = {
1391
-	"pxpreqbus", {false, false, false}, false, 0,
1392
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1393
-	0, 0, 0, 0, 0,
1394
-	false, false, MAX_DBG_RESET_REGS, 0
1395
-};
1396
-
1397
-static struct block_defs block_misc_aeu_defs = {
1398
-	"misc_aeu", {true, true, true}, false, 0,
1399
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1400
-	0, 0, 0, 0, 0,
1401
-	false, false, MAX_DBG_RESET_REGS, 0
1402
-};
1403
-
1404
-static struct block_defs block_bar0_map_defs = {
1405
-	"bar0_map", {true, true, true}, false, 0,
1406
-	{MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS},
1407
-	0, 0, 0, 0, 0,
1408
-	false, false, MAX_DBG_RESET_REGS, 0
1409
-};
1410
-
1411
-static struct block_defs *s_block_defs[MAX_BLOCK_ID] = {
1412
-	&block_grc_defs,
1413
-	&block_miscs_defs,
1414
-	&block_misc_defs,
1415
-	&block_dbu_defs,
1416
-	&block_pglue_b_defs,
1417
-	&block_cnig_defs,
1418
-	&block_cpmu_defs,
1419
-	&block_ncsi_defs,
1420
-	&block_opte_defs,
1421
-	&block_bmb_defs,
1422
-	&block_pcie_defs,
1423
-	&block_mcp_defs,
1424
-	&block_mcp2_defs,
1425
-	&block_pswhst_defs,
1426
-	&block_pswhst2_defs,
1427
-	&block_pswrd_defs,
1428
-	&block_pswrd2_defs,
1429
-	&block_pswwr_defs,
1430
-	&block_pswwr2_defs,
1431
-	&block_pswrq_defs,
1432
-	&block_pswrq2_defs,
1433
-	&block_pglcs_defs,
1434
-	&block_dmae_defs,
1435
-	&block_ptu_defs,
1436
-	&block_tcm_defs,
1437
-	&block_mcm_defs,
1438
-	&block_ucm_defs,
1439
-	&block_xcm_defs,
1440
-	&block_ycm_defs,
1441
-	&block_pcm_defs,
1442
-	&block_qm_defs,
1443
-	&block_tm_defs,
1444
-	&block_dorq_defs,
1445
-	&block_brb_defs,
1446
-	&block_src_defs,
1447
-	&block_prs_defs,
1448
-	&block_tsdm_defs,
1449
-	&block_msdm_defs,
1450
-	&block_usdm_defs,
1451
-	&block_xsdm_defs,
1452
-	&block_ysdm_defs,
1453
-	&block_psdm_defs,
1454
-	&block_tsem_defs,
1455
-	&block_msem_defs,
1456
-	&block_usem_defs,
1457
-	&block_xsem_defs,
1458
-	&block_ysem_defs,
1459
-	&block_psem_defs,
1460
-	&block_rss_defs,
1461
-	&block_tmld_defs,
1462
-	&block_muld_defs,
1463
-	&block_yuld_defs,
1464
-	&block_xyld_defs,
1465
-	&block_ptld_defs,
1466
-	&block_ypld_defs,
1467
-	&block_prm_defs,
1468
-	&block_pbf_pb1_defs,
1469
-	&block_pbf_pb2_defs,
1470
-	&block_rpb_defs,
1471
-	&block_btb_defs,
1472
-	&block_pbf_defs,
1473
-	&block_rdif_defs,
1474
-	&block_tdif_defs,
1475
-	&block_cdu_defs,
1476
-	&block_ccfc_defs,
1477
-	&block_tcfc_defs,
1478
-	&block_igu_defs,
1479
-	&block_cau_defs,
1480
-	&block_rgfs_defs,
1481
-	&block_rgsrc_defs,
1482
-	&block_tgfs_defs,
1483
-	&block_tgsrc_defs,
1484
-	&block_umac_defs,
1485
-	&block_xmac_defs,
1486
-	&block_dbg_defs,
1487
-	&block_nig_defs,
1488
-	&block_wol_defs,
1489
-	&block_bmbn_defs,
1490
-	&block_ipc_defs,
1491
-	&block_nwm_defs,
1492
-	&block_nws_defs,
1493
-	&block_ms_defs,
1494
-	&block_phy_pcie_defs,
1495
-	&block_led_defs,
1496
-	&block_avs_wrap_defs,
1497
-	&block_pxpreqbus_defs,
1498
-	&block_misc_aeu_defs,
1499
-	&block_bar0_map_defs,
1500
-};
1501
-
1502
-static struct platform_defs s_platform_defs[] = {
573
+static struct hw_type_defs s_hw_type_defs[] = {
574
+	/* HW_TYPE_ASIC */
1503575 	{"asic", 1, 256, 32768},
1504576 	{"reserved", 0, 0, 0},
1505577 	{"reserved2", 0, 0, 0},
....@@ -1508,146 +580,159 @@
1508580 
1509581 static struct grc_param_defs s_grc_param_defs[] = {
1510582 	/* DBG_GRC_PARAM_DUMP_TSTORM */
1511
-	{{1, 1, 1}, 0, 1, false, false, 1, 1},
583
+	{{1, 1}, 0, 1, false, false, 1, {1, 1}},
1512584 
1513585 	/* DBG_GRC_PARAM_DUMP_MSTORM */
1514
-	{{1, 1, 1}, 0, 1, false, false, 1, 1},
586
+	{{1, 1}, 0, 1, false, false, 1, {1, 1}},
1515587 
1516588 	/* DBG_GRC_PARAM_DUMP_USTORM */
1517
-	{{1, 1, 1}, 0, 1, false, false, 1, 1},
589
+	{{1, 1}, 0, 1, false, false, 1, {1, 1}},
1518590 
1519591 	/* DBG_GRC_PARAM_DUMP_XSTORM */
1520
-	{{1, 1, 1}, 0, 1, false, false, 1, 1},
592
+	{{1, 1}, 0, 1, false, false, 1, {1, 1}},
1521593 
1522594 	/* DBG_GRC_PARAM_DUMP_YSTORM */
1523
-	{{1, 1, 1}, 0, 1, false, false, 1, 1},
595
+	{{1, 1}, 0, 1, false, false, 1, {1, 1}},
1524596 
1525597 	/* DBG_GRC_PARAM_DUMP_PSTORM */
1526
-	{{1, 1, 1}, 0, 1, false, false, 1, 1},
598
+	{{1, 1}, 0, 1, false, false, 1, {1, 1}},
1527599 
1528600 	/* DBG_GRC_PARAM_DUMP_REGS */
1529
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
601
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1530602 
1531603 	/* DBG_GRC_PARAM_DUMP_RAM */
1532
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
604
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1533605 
1534606 	/* DBG_GRC_PARAM_DUMP_PBUF */
1535
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
607
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1536608 
1537609 	/* DBG_GRC_PARAM_DUMP_IOR */
1538
-	{{0, 0, 0}, 0, 1, false, false, 0, 1},
610
+	{{0, 0}, 0, 1, false, false, 0, {1, 1}},
1539611 
1540612 	/* DBG_GRC_PARAM_DUMP_VFC */
1541
-	{{0, 0, 0}, 0, 1, false, false, 0, 1},
613
+	{{0, 0}, 0, 1, false, false, 0, {1, 1}},
1542614 
1543615 	/* DBG_GRC_PARAM_DUMP_CM_CTX */
1544
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
616
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1545617 
1546618 	/* DBG_GRC_PARAM_DUMP_ILT */
1547
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
619
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1548620 
1549621 	/* DBG_GRC_PARAM_DUMP_RSS */
1550
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
622
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1551623 
1552624 	/* DBG_GRC_PARAM_DUMP_CAU */
1553
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
625
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1554626 
1555627 	/* DBG_GRC_PARAM_DUMP_QM */
1556
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
628
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1557629 
1558630 	/* DBG_GRC_PARAM_DUMP_MCP */
1559
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
631
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1560632 
1561
-	/* DBG_GRC_PARAM_MCP_TRACE_META_SIZE */
1562
-	{{1, 1, 1}, 1, 0xffffffff, false, true, 0, 1},
633
+	/* DBG_GRC_PARAM_DUMP_DORQ */
634
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1563635 
1564636 	/* DBG_GRC_PARAM_DUMP_CFC */
1565
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
637
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1566638 
1567639 	/* DBG_GRC_PARAM_DUMP_IGU */
1568
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
640
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1569641 
1570642 	/* DBG_GRC_PARAM_DUMP_BRB */
1571
-	{{0, 0, 0}, 0, 1, false, false, 0, 1},
643
+	{{0, 0}, 0, 1, false, false, 0, {1, 1}},
1572644 
1573645 	/* DBG_GRC_PARAM_DUMP_BTB */
1574
-	{{0, 0, 0}, 0, 1, false, false, 0, 1},
646
+	{{0, 0}, 0, 1, false, false, 0, {1, 1}},
1575647 
1576648 	/* DBG_GRC_PARAM_DUMP_BMB */
1577
-	{{0, 0, 0}, 0, 1, false, false, 0, 0},
649
+	{{0, 0}, 0, 1, false, false, 0, {0, 0}},
1578650 
1579
-	/* DBG_GRC_PARAM_DUMP_NIG */
1580
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
651
+	/* DBG_GRC_PARAM_RESERVED1 */
652
+	{{0, 0}, 0, 1, false, false, 0, {0, 0}},
1581653 
1582654 	/* DBG_GRC_PARAM_DUMP_MULD */
1583
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
655
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1584656 
1585657 	/* DBG_GRC_PARAM_DUMP_PRS */
1586
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
658
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1587659 
1588660 	/* DBG_GRC_PARAM_DUMP_DMAE */
1589
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
661
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1590662 
1591663 	/* DBG_GRC_PARAM_DUMP_TM */
1592
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
664
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1593665 
1594666 	/* DBG_GRC_PARAM_DUMP_SDM */
1595
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
667
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1596668 
1597669 	/* DBG_GRC_PARAM_DUMP_DIF */
1598
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
670
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1599671 
1600672 	/* DBG_GRC_PARAM_DUMP_STATIC */
1601
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
673
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1602674 
1603675 	/* DBG_GRC_PARAM_UNSTALL */
1604
-	{{0, 0, 0}, 0, 1, false, false, 0, 0},
676
+	{{0, 0}, 0, 1, false, false, 0, {0, 0}},
1605677 
1606
-	/* DBG_GRC_PARAM_NUM_LCIDS */
1607
-	{{MAX_LCIDS, MAX_LCIDS, MAX_LCIDS}, 1, MAX_LCIDS, false, false,
1608
-	 MAX_LCIDS, MAX_LCIDS},
678
+	/* DBG_GRC_PARAM_RESERVED2 */
679
+	{{0, 0}, 0, 1, false, false, 0, {0, 0}},
1609680 
1610
-	/* DBG_GRC_PARAM_NUM_LTIDS */
1611
-	{{MAX_LTIDS, MAX_LTIDS, MAX_LTIDS}, 1, MAX_LTIDS, false, false,
1612
-	 MAX_LTIDS, MAX_LTIDS},
681
+	/* DBG_GRC_PARAM_MCP_TRACE_META_SIZE */
682
+	{{0, 0}, 1, 0xffffffff, false, true, 0, {0, 0}},
1613683 
1614684 	/* DBG_GRC_PARAM_EXCLUDE_ALL */
1615
-	{{0, 0, 0}, 0, 1, true, false, 0, 0},
685
+	{{0, 0}, 0, 1, true, false, 0, {0, 0}},
1616686 
1617687 	/* DBG_GRC_PARAM_CRASH */
1618
-	{{0, 0, 0}, 0, 1, true, false, 0, 0},
688
+	{{0, 0}, 0, 1, true, false, 0, {0, 0}},
1619689 
1620690 	/* DBG_GRC_PARAM_PARITY_SAFE */
1621
-	{{0, 0, 0}, 0, 1, false, false, 1, 0},
691
+	{{0, 0}, 0, 1, false, false, 0, {0, 0}},
1622692 
1623693 	/* DBG_GRC_PARAM_DUMP_CM */
1624
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
694
+	{{1, 1}, 0, 1, false, false, 0, {1, 1}},
1625695 
1626696 	/* DBG_GRC_PARAM_DUMP_PHY */
1627
-	{{1, 1, 1}, 0, 1, false, false, 0, 1},
697
+	{{0, 0}, 0, 1, false, false, 0, {0, 0}},
1628698 
1629699 	/* DBG_GRC_PARAM_NO_MCP */
1630
-	{{0, 0, 0}, 0, 1, false, false, 0, 0},
700
+	{{0, 0}, 0, 1, false, false, 0, {0, 0}},
1631701 
1632702 	/* DBG_GRC_PARAM_NO_FW_VER */
1633
-	{{0, 0, 0}, 0, 1, false, false, 0, 0}
703
+	{{0, 0}, 0, 1, false, false, 0, {0, 0}},
704
+
705
+	/* DBG_GRC_PARAM_RESERVED3 */
706
+	{{0, 0}, 0, 1, false, false, 0, {0, 0}},
707
+
708
+	/* DBG_GRC_PARAM_DUMP_MCP_HW_DUMP */
709
+	{{0, 1}, 0, 1, false, false, 0, {0, 1}},
710
+
711
+	/* DBG_GRC_PARAM_DUMP_ILT_CDUC */
712
+	{{1, 1}, 0, 1, false, false, 0, {0, 0}},
713
+
714
+	/* DBG_GRC_PARAM_DUMP_ILT_CDUT */
715
+	{{1, 1}, 0, 1, false, false, 0, {0, 0}},
716
+
717
+	/* DBG_GRC_PARAM_DUMP_CAU_EXT */
718
+	{{0, 0}, 0, 1, false, false, 0, {1, 1}}
1634719 };
1635720 
1636721 static struct rss_mem_defs s_rss_mem_defs[] = {
1637
-	{ "rss_mem_cid", "rss_cid", 0, 32,
1638
-	  {256, 320, 512} },
722
+	{"rss_mem_cid", "rss_cid", 0, 32,
723
+	 {256, 320}},
1639724 
1640
-	{ "rss_mem_key_msb", "rss_key", 1024, 256,
1641
-	  {128, 208, 257} },
725
+	{"rss_mem_key_msb", "rss_key", 1024, 256,
726
+	 {128, 208}},
1642727 
1643
-	{ "rss_mem_key_lsb", "rss_key", 2048, 64,
1644
-	  {128, 208, 257} },
728
+	{"rss_mem_key_lsb", "rss_key", 2048, 64,
729
+	 {128, 208}},
1645730 
1646
-	{ "rss_mem_info", "rss_info", 3072, 16,
1647
-	  {128, 208, 256} },
731
+	{"rss_mem_info", "rss_info", 3072, 16,
732
+	 {128, 208}},
1648733 
1649
-	{ "rss_mem_ind", "rss_ind", 4096, 16,
1650
-	  {16384, 26624, 32768} }
734
+	{"rss_mem_ind", "rss_ind", 4096, 16,
735
+	 {16384, 26624}}
1651736 };
1652737 
1653738 static struct vfc_ram_defs s_vfc_ram_defs[] = {
....@@ -1658,54 +743,31 @@
1658743 };
1659744 
1660745 static struct big_ram_defs s_big_ram_defs[] = {
1661
-	{ "BRB", MEM_GROUP_BRB_MEM, MEM_GROUP_BRB_RAM, DBG_GRC_PARAM_DUMP_BRB,
1662
-	  BRB_REG_BIG_RAM_ADDRESS, BRB_REG_BIG_RAM_DATA,
1663
-	  MISC_REG_BLOCK_256B_EN, {0, 0, 0},
1664
-	  {153600, 180224, 282624} },
746
+	{"BRB", MEM_GROUP_BRB_MEM, MEM_GROUP_BRB_RAM, DBG_GRC_PARAM_DUMP_BRB,
747
+	 BRB_REG_BIG_RAM_ADDRESS, BRB_REG_BIG_RAM_DATA,
748
+	 MISC_REG_BLOCK_256B_EN, {0, 0},
749
+	 {153600, 180224}},
1665750 
1666
-	{ "BTB", MEM_GROUP_BTB_MEM, MEM_GROUP_BTB_RAM, DBG_GRC_PARAM_DUMP_BTB,
1667
-	  BTB_REG_BIG_RAM_ADDRESS, BTB_REG_BIG_RAM_DATA,
1668
-	  MISC_REG_BLOCK_256B_EN, {0, 1, 1},
1669
-	  {92160, 117760, 168960} },
751
+	{"BTB", MEM_GROUP_BTB_MEM, MEM_GROUP_BTB_RAM, DBG_GRC_PARAM_DUMP_BTB,
752
+	 BTB_REG_BIG_RAM_ADDRESS, BTB_REG_BIG_RAM_DATA,
753
+	 MISC_REG_BLOCK_256B_EN, {0, 1},
754
+	 {92160, 117760}},
1670755 
1671
-	{ "BMB", MEM_GROUP_BMB_MEM, MEM_GROUP_BMB_RAM, DBG_GRC_PARAM_DUMP_BMB,
1672
-	  BMB_REG_BIG_RAM_ADDRESS, BMB_REG_BIG_RAM_DATA,
1673
-	  MISCS_REG_BLOCK_256B_EN, {0, 0, 0},
1674
-	  {36864, 36864, 36864} }
756
+	{"BMB", MEM_GROUP_BMB_MEM, MEM_GROUP_BMB_RAM, DBG_GRC_PARAM_DUMP_BMB,
757
+	 BMB_REG_BIG_RAM_ADDRESS, BMB_REG_BIG_RAM_DATA,
758
+	 MISCS_REG_BLOCK_256B_EN, {0, 0},
759
+	 {36864, 36864}}
1675760 };
1676761 
1677
-static struct reset_reg_defs s_reset_regs_defs[] = {
1678
-	/* DBG_RESET_REG_MISCS_PL_UA */
1679
-	{ MISCS_REG_RESET_PL_UA,
1680
-	  {true, true, true}, {0x0, 0x0, 0x0} },
1681
-
1682
-	/* DBG_RESET_REG_MISCS_PL_HV */
1683
-	{ MISCS_REG_RESET_PL_HV,
1684
-	  {true, true, true}, {0x0, 0x400, 0x600} },
1685
-
1686
-	/* DBG_RESET_REG_MISCS_PL_HV_2 */
1687
-	{ MISCS_REG_RESET_PL_HV_2_K2_E5,
1688
-	  {false, true, true}, {0x0, 0x0, 0x0} },
1689
-
1690
-	/* DBG_RESET_REG_MISC_PL_UA */
1691
-	{ MISC_REG_RESET_PL_UA,
1692
-	  {true, true, true}, {0x0, 0x0, 0x0} },
1693
-
1694
-	/* DBG_RESET_REG_MISC_PL_HV */
1695
-	{ MISC_REG_RESET_PL_HV,
1696
-	  {true, true, true}, {0x0, 0x0, 0x0} },
1697
-
1698
-	/* DBG_RESET_REG_MISC_PL_PDA_VMAIN_1 */
1699
-	{ MISC_REG_RESET_PL_PDA_VMAIN_1,
1700
-	  {true, true, true}, {0x4404040, 0x4404040, 0x404040} },
1701
-
1702
-	/* DBG_RESET_REG_MISC_PL_PDA_VMAIN_2 */
1703
-	{ MISC_REG_RESET_PL_PDA_VMAIN_2,
1704
-	  {true, true, true}, {0x7, 0x7c00007, 0x5c08007} },
1705
-
1706
-	/* DBG_RESET_REG_MISC_PL_PDA_VAUX */
1707
-	{ MISC_REG_RESET_PL_PDA_VAUX,
1708
-	  {true, true, true}, {0x2, 0x2, 0x2} },
762
+static struct rbc_reset_defs s_rbc_reset_defs[] = {
763
+	{MISCS_REG_RESET_PL_HV,
764
+	 {0x0, 0x400}},
765
+	{MISC_REG_RESET_PL_PDA_VMAIN_1,
766
+	 {0x4404040, 0x4404040}},
767
+	{MISC_REG_RESET_PL_PDA_VMAIN_2,
768
+	 {0x7, 0x7c00007}},
769
+	{MISC_REG_RESET_PL_PDA_VAUX,
770
+	 {0x2, 0x2}},
1709771 };
1710772 
1711773 static struct phy_defs s_phy_defs[] = {
....@@ -1759,6 +821,15 @@
1759821 	return dword;
1760822 }
1761823 
824
+/* Sets the value of the specified GRC param */
825
+static void qed_grc_set_param(struct qed_hwfn *p_hwfn,
826
+			      enum dbg_grc_params grc_param, u32 val)
827
+{
828
+	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
829
+
830
+	dev_data->grc.param_val[grc_param] = val;
831
+}
832
+
1762833 /* Returns the value of the specified GRC param */
1763834 static u32 qed_grc_get_param(struct qed_hwfn *p_hwfn,
1764835 			     enum dbg_grc_params grc_param)
....@@ -1779,9 +850,19 @@
1779850 	}
1780851 }
1781852 
853
+/* Sets pointer and size for the specified binary buffer type */
854
+static void qed_set_dbg_bin_buf(struct qed_hwfn *p_hwfn,
855
+				enum bin_dbg_buffer_type buf_type,
856
+				const u32 *ptr, u32 size)
857
+{
858
+	struct virt_mem_desc *buf = &p_hwfn->dbg_arrays[buf_type];
859
+
860
+	buf->ptr = (void *)ptr;
861
+	buf->size = size;
862
+}
863
+
1782864 /* Initializes debug data for the specified device */
1783
-static enum dbg_status qed_dbg_dev_init(struct qed_hwfn *p_hwfn,
1784
-					struct qed_ptt *p_ptt)
865
+static enum dbg_status qed_dbg_dev_init(struct qed_hwfn *p_hwfn)
1785866 {
1786867 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
1787868 	u8 num_pfs = 0, max_pfs_per_port = 0;
....@@ -1806,26 +887,25 @@
1806887 		return DBG_STATUS_UNKNOWN_CHIP;
1807888 	}
1808889 
1809
-	/* Set platofrm */
1810
-	dev_data->platform_id = PLATFORM_ASIC;
890
+	/* Set HW type */
891
+	dev_data->hw_type = HW_TYPE_ASIC;
1811892 	dev_data->mode_enable[MODE_ASIC] = 1;
1812893 
1813894 	/* Set port mode */
1814
-	switch (qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE)) {
1815
-	case 0:
895
+	switch (p_hwfn->cdev->num_ports_in_engine) {
896
+	case 1:
1816897 		dev_data->mode_enable[MODE_PORTS_PER_ENG_1] = 1;
1817898 		break;
1818
-	case 1:
899
+	case 2:
1819900 		dev_data->mode_enable[MODE_PORTS_PER_ENG_2] = 1;
1820901 		break;
1821
-	case 2:
902
+	case 4:
1822903 		dev_data->mode_enable[MODE_PORTS_PER_ENG_4] = 1;
1823904 		break;
1824905 	}
1825906 
1826907 	/* Set 100G mode */
1827
-	if (dev_data->chip_id == CHIP_BB &&
1828
-	    qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB) == 2)
908
+	if (QED_IS_CMT(p_hwfn->cdev))
1829909 		dev_data->mode_enable[MODE_100G] = 1;
1830910 
1831911 	/* Set number of ports */
....@@ -1851,14 +931,36 @@
1851931 	return DBG_STATUS_OK;
1852932 }
1853933 
1854
-static struct dbg_bus_block *get_dbg_bus_block_desc(struct qed_hwfn *p_hwfn,
1855
-						    enum block_id block_id)
934
+static const struct dbg_block *get_dbg_block(struct qed_hwfn *p_hwfn,
935
+					     enum block_id block_id)
936
+{
937
+	const struct dbg_block *dbg_block;
938
+
939
+	dbg_block = p_hwfn->dbg_arrays[BIN_BUF_DBG_BLOCKS].ptr;
940
+	return dbg_block + block_id;
941
+}
942
+
943
+static const struct dbg_block_chip *qed_get_dbg_block_per_chip(struct qed_hwfn
944
+							       *p_hwfn,
945
+							       enum block_id
946
+							       block_id)
1856947 {
1857948 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
1858949 
1859
-	return (struct dbg_bus_block *)&dbg_bus_blocks[block_id *
1860
-						       MAX_CHIP_IDS +
1861
-						       dev_data->chip_id];
950
+	return (const struct dbg_block_chip *)
951
+	    p_hwfn->dbg_arrays[BIN_BUF_DBG_BLOCKS_CHIP_DATA].ptr +
952
+	    block_id * MAX_CHIP_IDS + dev_data->chip_id;
953
+}
954
+
955
+static const struct dbg_reset_reg *qed_get_dbg_reset_reg(struct qed_hwfn
956
+							 *p_hwfn,
957
+							 u8 reset_reg_id)
958
+{
959
+	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
960
+
961
+	return (const struct dbg_reset_reg *)
962
+	    p_hwfn->dbg_arrays[BIN_BUF_DBG_RESET_REGS].ptr +
963
+	    reset_reg_id * MAX_CHIP_IDS + dev_data->chip_id;
1862964 }
1863965 
1864966 /* Reads the FW info structure for the specified Storm from the chip,
....@@ -1870,7 +972,7 @@
1870972 {
1871973 	struct storm_defs *storm = &s_storm_defs[storm_id];
1872974 	struct fw_info_location fw_info_location;
1873
-	u32 addr, i, *dest;
975
+	u32 addr, i, size, *dest;
1874976 
1875977 	memset(&fw_info_location, 0, sizeof(fw_info_location));
1876978 	memset(fw_info, 0, sizeof(*fw_info));
....@@ -1879,23 +981,33 @@
1879981 	 * The address is located in the last line of the Storm RAM.
1880982 	 */
1881983 	addr = storm->sem_fast_mem_addr + SEM_FAST_REG_INT_RAM +
1882
-	       DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE_BB_K2) -
1883
-	       sizeof(fw_info_location);
1884
-	dest = (u32 *)&fw_info_location;
984
+	    DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE) -
985
+	    sizeof(fw_info_location);
1885986 
1886
-	for (i = 0; i < BYTES_TO_DWORDS(sizeof(fw_info_location));
1887
-	     i++, addr += BYTES_IN_DWORD)
987
+	dest = (u32 *)&fw_info_location;
988
+	size = BYTES_TO_DWORDS(sizeof(fw_info_location));
989
+
990
+	for (i = 0; i < size; i++, addr += BYTES_IN_DWORD)
1888991 		dest[i] = qed_rd(p_hwfn, p_ptt, addr);
1889992 
993
+	/* qed_rq() fetches data in CPU byteorder. Swap it back to
994
+	 * the device's to get right structure layout.
995
+	 */
996
+	cpu_to_le32_array(dest, size);
997
+
1890998 	/* Read FW version info from Storm RAM */
1891
-	if (fw_info_location.size > 0 && fw_info_location.size <=
1892
-	    sizeof(*fw_info)) {
1893
-		addr = fw_info_location.grc_addr;
1894
-		dest = (u32 *)fw_info;
1895
-		for (i = 0; i < BYTES_TO_DWORDS(fw_info_location.size);
1896
-		     i++, addr += BYTES_IN_DWORD)
1897
-			dest[i] = qed_rd(p_hwfn, p_ptt, addr);
1898
-	}
999
+	size = le32_to_cpu(fw_info_location.size);
1000
+	if (!size || size > sizeof(*fw_info))
1001
+		return;
1002
+
1003
+	addr = le32_to_cpu(fw_info_location.grc_addr);
1004
+	dest = (u32 *)fw_info;
1005
+	size = BYTES_TO_DWORDS(size);
1006
+
1007
+	for (i = 0; i < size; i++, addr += BYTES_IN_DWORD)
1008
+		dest[i] = qed_rd(p_hwfn, p_ptt, addr);
1009
+
1010
+	cpu_to_le32_array(dest, size);
18991011 }
19001012 
19011013 /* Dumps the specified string to the specified buffer.
....@@ -2019,9 +1131,8 @@
20191131 				     dump, "fw-version", fw_ver_str);
20201132 	offset += qed_dump_str_param(dump_buf + offset,
20211133 				     dump, "fw-image", fw_img_str);
2022
-	offset += qed_dump_num_param(dump_buf + offset,
2023
-				     dump,
2024
-				     "fw-timestamp", fw_info.ver.timestamp);
1134
+	offset += qed_dump_num_param(dump_buf + offset, dump, "fw-timestamp",
1135
+				     le32_to_cpu(fw_info.ver.timestamp));
20251136 
20261137 	return offset;
20271138 }
....@@ -2075,6 +1186,29 @@
20751186 	return qed_dump_str_param(dump_buf, dump, "mfw-version", mfw_ver_str);
20761187 }
20771188 
1189
+/* Reads the chip revision from the chip and writes it as a param to the
1190
+ * specified buffer. Returns the dumped size in dwords.
1191
+ */
1192
+static u32 qed_dump_chip_revision_param(struct qed_hwfn *p_hwfn,
1193
+					struct qed_ptt *p_ptt,
1194
+					u32 *dump_buf, bool dump)
1195
+{
1196
+	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
1197
+	char param_str[3] = "??";
1198
+
1199
+	if (dev_data->hw_type == HW_TYPE_ASIC) {
1200
+		u32 chip_rev, chip_metal;
1201
+
1202
+		chip_rev = qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
1203
+		chip_metal = qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
1204
+
1205
+		param_str[0] = 'a' + (u8)chip_rev;
1206
+		param_str[1] = '0' + (u8)chip_metal;
1207
+	}
1208
+
1209
+	return qed_dump_str_param(dump_buf, dump, "chip-revision", param_str);
1210
+}
1211
+
20781212 /* Writes a section header to the specified buffer.
20791213  * Returns the dumped size in dwords.
20801214  */
....@@ -2098,7 +1232,8 @@
20981232 	u8 num_params;
20991233 
21001234 	/* Dump global params section header */
2101
-	num_params = NUM_COMMON_GLOBAL_PARAMS + num_specific_global_params;
1235
+	num_params = NUM_COMMON_GLOBAL_PARAMS + num_specific_global_params +
1236
+		(dev_data->chip_id == CHIP_BB ? 1 : 0);
21021237 	offset += qed_dump_section_hdr(dump_buf + offset,
21031238 				       dump, "global_params", num_params);
21041239 
....@@ -2106,6 +1241,8 @@
21061241 	offset += qed_dump_fw_ver_param(p_hwfn, p_ptt, dump_buf + offset, dump);
21071242 	offset += qed_dump_mfw_ver_param(p_hwfn,
21081243 					 p_ptt, dump_buf + offset, dump);
1244
+	offset += qed_dump_chip_revision_param(p_hwfn,
1245
+					       p_ptt, dump_buf + offset, dump);
21091246 	offset += qed_dump_num_param(dump_buf + offset,
21101247 				     dump, "tools-version", TOOLS_VERSION);
21111248 	offset += qed_dump_str_param(dump_buf + offset,
....@@ -2115,11 +1252,12 @@
21151252 	offset += qed_dump_str_param(dump_buf + offset,
21161253 				     dump,
21171254 				     "platform",
2118
-				     s_platform_defs[dev_data->platform_id].
2119
-				     name);
2120
-	offset +=
2121
-	    qed_dump_num_param(dump_buf + offset, dump, "pci-func",
2122
-			       p_hwfn->abs_pf_id);
1255
+				     s_hw_type_defs[dev_data->hw_type].name);
1256
+	offset += qed_dump_num_param(dump_buf + offset,
1257
+				     dump, "pci-func", p_hwfn->abs_pf_id);
1258
+	if (dev_data->chip_id == CHIP_BB)
1259
+		offset += qed_dump_num_param(dump_buf + offset,
1260
+					     dump, "path", QED_PATH_ID(p_hwfn));
21231261 
21241262 	return offset;
21251263 }
....@@ -2150,22 +1288,85 @@
21501288 					  struct qed_ptt *p_ptt)
21511289 {
21521290 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2153
-	u32 reg_val[MAX_DBG_RESET_REGS] = { 0 };
2154
-	u32 i;
1291
+	u32 reg_val[NUM_DBG_RESET_REGS] = { 0 };
1292
+	u8 rst_reg_id;
1293
+	u32 blk_id;
21551294 
21561295 	/* Read reset registers */
2157
-	for (i = 0; i < MAX_DBG_RESET_REGS; i++)
2158
-		if (s_reset_regs_defs[i].exists[dev_data->chip_id])
2159
-			reg_val[i] = qed_rd(p_hwfn,
2160
-					    p_ptt, s_reset_regs_defs[i].addr);
1296
+	for (rst_reg_id = 0; rst_reg_id < NUM_DBG_RESET_REGS; rst_reg_id++) {
1297
+		const struct dbg_reset_reg *rst_reg;
1298
+		bool rst_reg_removed;
1299
+		u32 rst_reg_addr;
1300
+
1301
+		rst_reg = qed_get_dbg_reset_reg(p_hwfn, rst_reg_id);
1302
+		rst_reg_removed = GET_FIELD(rst_reg->data,
1303
+					    DBG_RESET_REG_IS_REMOVED);
1304
+		rst_reg_addr = DWORDS_TO_BYTES(GET_FIELD(rst_reg->data,
1305
+							 DBG_RESET_REG_ADDR));
1306
+
1307
+		if (!rst_reg_removed)
1308
+			reg_val[rst_reg_id] = qed_rd(p_hwfn, p_ptt,
1309
+						     rst_reg_addr);
1310
+	}
21611311 
21621312 	/* Check if blocks are in reset */
2163
-	for (i = 0; i < MAX_BLOCK_ID; i++) {
2164
-		struct block_defs *block = s_block_defs[i];
1313
+	for (blk_id = 0; blk_id < NUM_PHYS_BLOCKS; blk_id++) {
1314
+		const struct dbg_block_chip *blk;
1315
+		bool has_rst_reg;
1316
+		bool is_removed;
21651317 
2166
-		dev_data->block_in_reset[i] = block->has_reset_bit &&
2167
-		    !(reg_val[block->reset_reg] & BIT(block->reset_bit_offset));
1318
+		blk = qed_get_dbg_block_per_chip(p_hwfn, (enum block_id)blk_id);
1319
+		is_removed = GET_FIELD(blk->flags, DBG_BLOCK_CHIP_IS_REMOVED);
1320
+		has_rst_reg = GET_FIELD(blk->flags,
1321
+					DBG_BLOCK_CHIP_HAS_RESET_REG);
1322
+
1323
+		if (!is_removed && has_rst_reg)
1324
+			dev_data->block_in_reset[blk_id] =
1325
+			    !(reg_val[blk->reset_reg_id] &
1326
+			      BIT(blk->reset_reg_bit_offset));
21681327 	}
1328
+}
1329
+
1330
+/* is_mode_match recursive function */
1331
+static bool qed_is_mode_match_rec(struct qed_hwfn *p_hwfn,
1332
+				  u16 *modes_buf_offset, u8 rec_depth)
1333
+{
1334
+	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
1335
+	u8 *dbg_array;
1336
+	bool arg1, arg2;
1337
+	u8 tree_val;
1338
+
1339
+	if (rec_depth > MAX_RECURSION_DEPTH) {
1340
+		DP_NOTICE(p_hwfn,
1341
+			  "Unexpected error: is_mode_match_rec exceeded the max recursion depth. This is probably due to a corrupt init/debug buffer.\n");
1342
+		return false;
1343
+	}
1344
+
1345
+	/* Get next element from modes tree buffer */
1346
+	dbg_array = p_hwfn->dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr;
1347
+	tree_val = dbg_array[(*modes_buf_offset)++];
1348
+
1349
+	switch (tree_val) {
1350
+	case INIT_MODE_OP_NOT:
1351
+		return !qed_is_mode_match_rec(p_hwfn,
1352
+					      modes_buf_offset, rec_depth + 1);
1353
+	case INIT_MODE_OP_OR:
1354
+	case INIT_MODE_OP_AND:
1355
+		arg1 = qed_is_mode_match_rec(p_hwfn,
1356
+					     modes_buf_offset, rec_depth + 1);
1357
+		arg2 = qed_is_mode_match_rec(p_hwfn,
1358
+					     modes_buf_offset, rec_depth + 1);
1359
+		return (tree_val == INIT_MODE_OP_OR) ? (arg1 ||
1360
+							arg2) : (arg1 && arg2);
1361
+	default:
1362
+		return dev_data->mode_enable[tree_val - MAX_INIT_MODE_OPS] > 0;
1363
+	}
1364
+}
1365
+
1366
+/* Returns true if the mode (specified using modes_buf_offset) is enabled */
1367
+static bool qed_is_mode_match(struct qed_hwfn *p_hwfn, u16 *modes_buf_offset)
1368
+{
1369
+	return qed_is_mode_match_rec(p_hwfn, modes_buf_offset, 0);
21691370 }
21701371 
21711372 /* Enable / disable the Debug block */
....@@ -2179,23 +1380,21 @@
21791380 static void qed_bus_reset_dbg_block(struct qed_hwfn *p_hwfn,
21801381 				    struct qed_ptt *p_ptt)
21811382 {
2182
-	u32 dbg_reset_reg_addr, old_reset_reg_val, new_reset_reg_val;
2183
-	struct block_defs *dbg_block = s_block_defs[BLOCK_DBG];
1383
+	u32 reset_reg_addr, old_reset_reg_val, new_reset_reg_val;
1384
+	const struct dbg_reset_reg *reset_reg;
1385
+	const struct dbg_block_chip *block;
21841386 
2185
-	dbg_reset_reg_addr = s_reset_regs_defs[dbg_block->reset_reg].addr;
2186
-	old_reset_reg_val = qed_rd(p_hwfn, p_ptt, dbg_reset_reg_addr);
1387
+	block = qed_get_dbg_block_per_chip(p_hwfn, BLOCK_DBG);
1388
+	reset_reg = qed_get_dbg_reset_reg(p_hwfn, block->reset_reg_id);
1389
+	reset_reg_addr =
1390
+	    DWORDS_TO_BYTES(GET_FIELD(reset_reg->data, DBG_RESET_REG_ADDR));
1391
+
1392
+	old_reset_reg_val = qed_rd(p_hwfn, p_ptt, reset_reg_addr);
21871393 	new_reset_reg_val =
2188
-	    old_reset_reg_val & ~BIT(dbg_block->reset_bit_offset);
1394
+	    old_reset_reg_val & ~BIT(block->reset_reg_bit_offset);
21891395 
2190
-	qed_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, new_reset_reg_val);
2191
-	qed_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, old_reset_reg_val);
2192
-}
2193
-
2194
-static void qed_bus_set_framing_mode(struct qed_hwfn *p_hwfn,
2195
-				     struct qed_ptt *p_ptt,
2196
-				     enum dbg_bus_frame_modes mode)
2197
-{
2198
-	qed_wr(p_hwfn, p_ptt, DBG_REG_FRAMING_MODE, (u8)mode);
1396
+	qed_wr(p_hwfn, p_ptt, reset_reg_addr, new_reset_reg_val);
1397
+	qed_wr(p_hwfn, p_ptt, reset_reg_addr, old_reset_reg_val);
21991398 }
22001399 
22011400 /* Enable / disable Debug Bus clients according to the specified mask
....@@ -2207,28 +1406,65 @@
22071406 	qed_wr(p_hwfn, p_ptt, DBG_REG_CLIENT_ENABLE, client_mask);
22081407 }
22091408 
2210
-static bool qed_is_mode_match(struct qed_hwfn *p_hwfn, u16 *modes_buf_offset)
1409
+static void qed_bus_config_dbg_line(struct qed_hwfn *p_hwfn,
1410
+				    struct qed_ptt *p_ptt,
1411
+				    enum block_id block_id,
1412
+				    u8 line_id,
1413
+				    u8 enable_mask,
1414
+				    u8 right_shift,
1415
+				    u8 force_valid_mask, u8 force_frame_mask)
1416
+{
1417
+	const struct dbg_block_chip *block =
1418
+		qed_get_dbg_block_per_chip(p_hwfn, block_id);
1419
+
1420
+	qed_wr(p_hwfn, p_ptt, DWORDS_TO_BYTES(block->dbg_select_reg_addr),
1421
+	       line_id);
1422
+	qed_wr(p_hwfn, p_ptt, DWORDS_TO_BYTES(block->dbg_dword_enable_reg_addr),
1423
+	       enable_mask);
1424
+	qed_wr(p_hwfn, p_ptt, DWORDS_TO_BYTES(block->dbg_shift_reg_addr),
1425
+	       right_shift);
1426
+	qed_wr(p_hwfn, p_ptt, DWORDS_TO_BYTES(block->dbg_force_valid_reg_addr),
1427
+	       force_valid_mask);
1428
+	qed_wr(p_hwfn, p_ptt, DWORDS_TO_BYTES(block->dbg_force_frame_reg_addr),
1429
+	       force_frame_mask);
1430
+}
1431
+
1432
+/* Disable debug bus in all blocks */
1433
+static void qed_bus_disable_blocks(struct qed_hwfn *p_hwfn,
1434
+				   struct qed_ptt *p_ptt)
22111435 {
22121436 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2213
-	bool arg1, arg2;
2214
-	const u32 *ptr;
2215
-	u8 tree_val;
1437
+	u32 block_id;
22161438 
2217
-	/* Get next element from modes tree buffer */
2218
-	ptr = s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr;
2219
-	tree_val = ((u8 *)ptr)[(*modes_buf_offset)++];
1439
+	/* Disable all blocks */
1440
+	for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
1441
+		const struct dbg_block_chip *block_per_chip =
1442
+		    qed_get_dbg_block_per_chip(p_hwfn,
1443
+					       (enum block_id)block_id);
22201444 
2221
-	switch (tree_val) {
2222
-	case INIT_MODE_OP_NOT:
2223
-		return !qed_is_mode_match(p_hwfn, modes_buf_offset);
2224
-	case INIT_MODE_OP_OR:
2225
-	case INIT_MODE_OP_AND:
2226
-		arg1 = qed_is_mode_match(p_hwfn, modes_buf_offset);
2227
-		arg2 = qed_is_mode_match(p_hwfn, modes_buf_offset);
2228
-		return (tree_val == INIT_MODE_OP_OR) ? (arg1 ||
2229
-							arg2) : (arg1 && arg2);
2230
-	default:
2231
-		return dev_data->mode_enable[tree_val - MAX_INIT_MODE_OPS] > 0;
1445
+		if (GET_FIELD(block_per_chip->flags,
1446
+			      DBG_BLOCK_CHIP_IS_REMOVED) ||
1447
+		    dev_data->block_in_reset[block_id])
1448
+			continue;
1449
+
1450
+		/* Disable debug bus */
1451
+		if (GET_FIELD(block_per_chip->flags,
1452
+			      DBG_BLOCK_CHIP_HAS_DBG_BUS)) {
1453
+			u32 dbg_en_addr =
1454
+				block_per_chip->dbg_dword_enable_reg_addr;
1455
+			u16 modes_buf_offset =
1456
+			    GET_FIELD(block_per_chip->dbg_bus_mode.data,
1457
+				      DBG_MODE_HDR_MODES_BUF_OFFSET);
1458
+			bool eval_mode =
1459
+			    GET_FIELD(block_per_chip->dbg_bus_mode.data,
1460
+				      DBG_MODE_HDR_EVAL_MODE) > 0;
1461
+
1462
+			if (!eval_mode ||
1463
+			    qed_is_mode_match(p_hwfn, &modes_buf_offset))
1464
+				qed_wr(p_hwfn, p_ptt,
1465
+				       DWORDS_TO_BYTES(dbg_en_addr),
1466
+				       0);
1467
+		}
22321468 	}
22331469 }
22341470 
....@@ -2239,6 +1475,20 @@
22391475 				enum dbg_grc_params grc_param)
22401476 {
22411477 	return qed_grc_get_param(p_hwfn, grc_param) > 0;
1478
+}
1479
+
1480
+/* Returns the storm_id that matches the specified Storm letter,
1481
+ * or MAX_DBG_STORMS if invalid storm letter.
1482
+ */
1483
+static enum dbg_storms qed_get_id_from_letter(char storm_letter)
1484
+{
1485
+	u8 storm_id;
1486
+
1487
+	for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++)
1488
+		if (s_storm_defs[storm_id].letter == storm_letter)
1489
+			return (enum dbg_storms)storm_id;
1490
+
1491
+	return MAX_DBG_STORMS;
22421492 }
22431493 
22441494 /* Returns true of the specified Storm should be included in the dump, false
....@@ -2256,14 +1506,20 @@
22561506 static bool qed_grc_is_mem_included(struct qed_hwfn *p_hwfn,
22571507 				    enum block_id block_id, u8 mem_group_id)
22581508 {
2259
-	struct block_defs *block = s_block_defs[block_id];
1509
+	const struct dbg_block *block;
22601510 	u8 i;
22611511 
2262
-	/* Check Storm match */
2263
-	if (block->associated_to_storm &&
2264
-	    !qed_grc_is_storm_included(p_hwfn,
2265
-				       (enum dbg_storms)block->storm_id))
2266
-		return false;
1512
+	block = get_dbg_block(p_hwfn, block_id);
1513
+
1514
+	/* If the block is associated with a Storm, check Storm match */
1515
+	if (block->associated_storm_letter) {
1516
+		enum dbg_storms associated_storm_id =
1517
+		    qed_get_id_from_letter(block->associated_storm_letter);
1518
+
1519
+		if (associated_storm_id == MAX_DBG_STORMS ||
1520
+		    !qed_grc_is_storm_included(p_hwfn, associated_storm_id))
1521
+			return false;
1522
+	}
22671523 
22681524 	for (i = 0; i < NUM_BIG_RAM_TYPES; i++) {
22691525 		struct big_ram_defs *big_ram = &s_big_ram_defs[i];
....@@ -2285,6 +1541,8 @@
22851541 	case MEM_GROUP_CAU_SB:
22861542 	case MEM_GROUP_CAU_PI:
22871543 		return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CAU);
1544
+	case MEM_GROUP_CAU_MEM_EXT:
1545
+		return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CAU_EXT);
22881546 	case MEM_GROUP_QM_MEM:
22891547 		return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_QM);
22901548 	case MEM_GROUP_CFC_MEM:
....@@ -2292,6 +1550,8 @@
22921550 	case MEM_GROUP_TASK_CFC_MEM:
22931551 		return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CFC) ||
22941552 		       qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM_CTX);
1553
+	case MEM_GROUP_DORQ_MEM:
1554
+		return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_DORQ);
22951555 	case MEM_GROUP_IGU_MEM:
22961556 	case MEM_GROUP_IGU_MSIX:
22971557 		return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IGU);
....@@ -2337,64 +1597,104 @@
23371597 	msleep(STALL_DELAY_MS);
23381598 }
23391599 
2340
-/* Takes all blocks out of reset */
1600
+/* Takes all blocks out of reset. If rbc_only is true, only RBC clients are
1601
+ * taken out of reset.
1602
+ */
23411603 static void qed_grc_unreset_blocks(struct qed_hwfn *p_hwfn,
2342
-				   struct qed_ptt *p_ptt)
1604
+				   struct qed_ptt *p_ptt, bool rbc_only)
23431605 {
23441606 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2345
-	u32 reg_val[MAX_DBG_RESET_REGS] = { 0 };
2346
-	u32 block_id, i;
1607
+	u8 chip_id = dev_data->chip_id;
1608
+	u32 i;
23471609 
2348
-	/* Fill reset regs values */
2349
-	for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
2350
-		struct block_defs *block = s_block_defs[block_id];
2351
-
2352
-		if (block->exists[dev_data->chip_id] && block->has_reset_bit &&
2353
-		    block->unreset)
2354
-			reg_val[block->reset_reg] |=
2355
-			    BIT(block->reset_bit_offset);
2356
-	}
2357
-
2358
-	/* Write reset registers */
2359
-	for (i = 0; i < MAX_DBG_RESET_REGS; i++) {
2360
-		if (!s_reset_regs_defs[i].exists[dev_data->chip_id])
2361
-			continue;
2362
-
2363
-		reg_val[i] |=
2364
-			s_reset_regs_defs[i].unreset_val[dev_data->chip_id];
2365
-
2366
-		if (reg_val[i])
1610
+	/* Take RBCs out of reset */
1611
+	for (i = 0; i < ARRAY_SIZE(s_rbc_reset_defs); i++)
1612
+		if (s_rbc_reset_defs[i].reset_val[dev_data->chip_id])
23671613 			qed_wr(p_hwfn,
23681614 			       p_ptt,
2369
-			       s_reset_regs_defs[i].addr +
2370
-			       RESET_REG_UNRESET_OFFSET, reg_val[i]);
1615
+			       s_rbc_reset_defs[i].reset_reg_addr +
1616
+			       RESET_REG_UNRESET_OFFSET,
1617
+			       s_rbc_reset_defs[i].reset_val[chip_id]);
1618
+
1619
+	if (!rbc_only) {
1620
+		u32 reg_val[NUM_DBG_RESET_REGS] = { 0 };
1621
+		u8 reset_reg_id;
1622
+		u32 block_id;
1623
+
1624
+		/* Fill reset regs values */
1625
+		for (block_id = 0; block_id < NUM_PHYS_BLOCKS; block_id++) {
1626
+			bool is_removed, has_reset_reg, unreset_before_dump;
1627
+			const struct dbg_block_chip *block;
1628
+
1629
+			block = qed_get_dbg_block_per_chip(p_hwfn,
1630
+							   (enum block_id)
1631
+							   block_id);
1632
+			is_removed =
1633
+			    GET_FIELD(block->flags, DBG_BLOCK_CHIP_IS_REMOVED);
1634
+			has_reset_reg =
1635
+			    GET_FIELD(block->flags,
1636
+				      DBG_BLOCK_CHIP_HAS_RESET_REG);
1637
+			unreset_before_dump =
1638
+			    GET_FIELD(block->flags,
1639
+				      DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP);
1640
+
1641
+			if (!is_removed && has_reset_reg && unreset_before_dump)
1642
+				reg_val[block->reset_reg_id] |=
1643
+				    BIT(block->reset_reg_bit_offset);
1644
+		}
1645
+
1646
+		/* Write reset registers */
1647
+		for (reset_reg_id = 0; reset_reg_id < NUM_DBG_RESET_REGS;
1648
+		     reset_reg_id++) {
1649
+			const struct dbg_reset_reg *reset_reg;
1650
+			u32 reset_reg_addr;
1651
+
1652
+			reset_reg = qed_get_dbg_reset_reg(p_hwfn, reset_reg_id);
1653
+
1654
+			if (GET_FIELD
1655
+			    (reset_reg->data, DBG_RESET_REG_IS_REMOVED))
1656
+				continue;
1657
+
1658
+			if (reg_val[reset_reg_id]) {
1659
+				reset_reg_addr =
1660
+				    GET_FIELD(reset_reg->data,
1661
+					      DBG_RESET_REG_ADDR);
1662
+				qed_wr(p_hwfn,
1663
+				       p_ptt,
1664
+				       DWORDS_TO_BYTES(reset_reg_addr) +
1665
+				       RESET_REG_UNRESET_OFFSET,
1666
+				       reg_val[reset_reg_id]);
1667
+			}
1668
+		}
23711669 	}
23721670 }
23731671 
23741672 /* Returns the attention block data of the specified block */
23751673 static const struct dbg_attn_block_type_data *
2376
-qed_get_block_attn_data(enum block_id block_id, enum dbg_attn_type attn_type)
1674
+qed_get_block_attn_data(struct qed_hwfn *p_hwfn,
1675
+			enum block_id block_id, enum dbg_attn_type attn_type)
23771676 {
23781677 	const struct dbg_attn_block *base_attn_block_arr =
2379
-		(const struct dbg_attn_block *)
2380
-		s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr;
1678
+	    (const struct dbg_attn_block *)
1679
+	    p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr;
23811680 
23821681 	return &base_attn_block_arr[block_id].per_type_data[attn_type];
23831682 }
23841683 
23851684 /* Returns the attention registers of the specified block */
23861685 static const struct dbg_attn_reg *
2387
-qed_get_block_attn_regs(enum block_id block_id, enum dbg_attn_type attn_type,
1686
+qed_get_block_attn_regs(struct qed_hwfn *p_hwfn,
1687
+			enum block_id block_id, enum dbg_attn_type attn_type,
23881688 			u8 *num_attn_regs)
23891689 {
23901690 	const struct dbg_attn_block_type_data *block_type_data =
2391
-		qed_get_block_attn_data(block_id, attn_type);
1691
+	    qed_get_block_attn_data(p_hwfn, block_id, attn_type);
23921692 
23931693 	*num_attn_regs = block_type_data->num_regs;
23941694 
2395
-	return &((const struct dbg_attn_reg *)
2396
-		 s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr)[block_type_data->
2397
-							  regs_offset];
1695
+	return (const struct dbg_attn_reg *)
1696
+		p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr +
1697
+		block_type_data->regs_offset;
23981698 }
23991699 
24001700 /* For each block, clear the status of all parities */
....@@ -2406,11 +1706,12 @@
24061706 	u8 reg_idx, num_attn_regs;
24071707 	u32 block_id;
24081708 
2409
-	for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
1709
+	for (block_id = 0; block_id < NUM_PHYS_BLOCKS; block_id++) {
24101710 		if (dev_data->block_in_reset[block_id])
24111711 			continue;
24121712 
2413
-		attn_reg_arr = qed_get_block_attn_regs((enum block_id)block_id,
1713
+		attn_reg_arr = qed_get_block_attn_regs(p_hwfn,
1714
+						       (enum block_id)block_id,
24141715 						       ATTN_TYPE_PARITY,
24151716 						       &num_attn_regs);
24161717 
....@@ -2438,22 +1739,20 @@
24381739 }
24391740 
24401741 /* Dumps GRC registers section header. Returns the dumped size in dwords.
2441
- * The following parameters are dumped:
1742
+ * the following parameters are dumped:
24421743  * - count: no. of dumped entries
24431744  * - split_type: split type
24441745  * - split_id: split ID (dumped only if split_id != SPLIT_TYPE_NONE)
2445
- * - param_name: user parameter value (dumped only if param_name != NULL
2446
- *		 and param_val != NULL).
1746
+ * - reg_type_name: register type name (dumped only if reg_type_name != NULL)
24471747  */
24481748 static u32 qed_grc_dump_regs_hdr(u32 *dump_buf,
24491749 				 bool dump,
24501750 				 u32 num_reg_entries,
24511751 				 enum init_split_types split_type,
2452
-				 u8 split_id,
2453
-				 const char *param_name, const char *param_val)
1752
+				 u8 split_id, const char *reg_type_name)
24541753 {
24551754 	u8 num_params = 2 +
2456
-	    (split_type != SPLIT_TYPE_NONE ? 1 : 0) + (param_name ? 1 : 0);
1755
+	    (split_type != SPLIT_TYPE_NONE ? 1 : 0) + (reg_type_name ? 1 : 0);
24571756 	u32 offset = 0;
24581757 
24591758 	offset += qed_dump_section_hdr(dump_buf + offset,
....@@ -2466,9 +1765,9 @@
24661765 	if (split_type != SPLIT_TYPE_NONE)
24671766 		offset += qed_dump_num_param(dump_buf + offset,
24681767 					     dump, "id", split_id);
2469
-	if (param_name && param_val)
1768
+	if (reg_type_name)
24701769 		offset += qed_dump_str_param(dump_buf + offset,
2471
-					     dump, param_name, param_val);
1770
+					     dump, "type", reg_type_name);
24721771 
24731772 	return offset;
24741773 }
....@@ -2497,21 +1796,13 @@
24971796 				   u8 split_id)
24981797 {
24991798 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2500
-	u8 port_id = 0, pf_id = 0, vf_id = 0, fid = 0;
1799
+	u8 port_id = 0, pf_id = 0, vf_id = 0;
1800
+	bool read_using_dmae = false;
1801
+	u32 thresh;
1802
+	u16 fid;
25011803 
25021804 	if (!dump)
25031805 		return len;
2504
-
2505
-	/* Print log if needed */
2506
-	dev_data->num_regs_read += len;
2507
-	if (dev_data->num_regs_read >=
2508
-	    s_platform_defs[dev_data->platform_id].log_thresh) {
2509
-		DP_VERBOSE(p_hwfn,
2510
-			   QED_MSG_DEBUG,
2511
-			   "Dumping %d registers...\n",
2512
-			   dev_data->num_regs_read);
2513
-		dev_data->num_regs_read = 0;
2514
-	}
25151806 
25161807 	switch (split_type) {
25171808 	case SPLIT_TYPE_PORT:
....@@ -2533,38 +1824,77 @@
25331824 	}
25341825 
25351826 	/* Try reading using DMAE */
2536
-	if (dev_data->use_dmae && split_type == SPLIT_TYPE_NONE &&
2537
-	    (len >= s_platform_defs[dev_data->platform_id].dmae_thresh ||
2538
-	     wide_bus)) {
2539
-		if (!qed_dmae_grc2host(p_hwfn, p_ptt, DWORDS_TO_BYTES(addr),
2540
-				       (u64)(uintptr_t)(dump_buf), len, 0))
2541
-			return len;
2542
-		dev_data->use_dmae = 0;
2543
-		DP_VERBOSE(p_hwfn,
2544
-			   QED_MSG_DEBUG,
2545
-			   "Failed reading from chip using DMAE, using GRC instead\n");
1827
+	if (dev_data->use_dmae && split_type != SPLIT_TYPE_VF &&
1828
+	    (len >= s_hw_type_defs[dev_data->hw_type].dmae_thresh ||
1829
+	     (PROTECT_WIDE_BUS && wide_bus))) {
1830
+		struct qed_dmae_params dmae_params;
1831
+
1832
+		/* Set DMAE params */
1833
+		memset(&dmae_params, 0, sizeof(dmae_params));
1834
+		SET_FIELD(dmae_params.flags, QED_DMAE_PARAMS_COMPLETION_DST, 1);
1835
+		switch (split_type) {
1836
+		case SPLIT_TYPE_PORT:
1837
+			SET_FIELD(dmae_params.flags, QED_DMAE_PARAMS_PORT_VALID,
1838
+				  1);
1839
+			dmae_params.port_id = port_id;
1840
+			break;
1841
+		case SPLIT_TYPE_PF:
1842
+			SET_FIELD(dmae_params.flags,
1843
+				  QED_DMAE_PARAMS_SRC_PF_VALID, 1);
1844
+			dmae_params.src_pfid = pf_id;
1845
+			break;
1846
+		case SPLIT_TYPE_PORT_PF:
1847
+			SET_FIELD(dmae_params.flags, QED_DMAE_PARAMS_PORT_VALID,
1848
+				  1);
1849
+			SET_FIELD(dmae_params.flags,
1850
+				  QED_DMAE_PARAMS_SRC_PF_VALID, 1);
1851
+			dmae_params.port_id = port_id;
1852
+			dmae_params.src_pfid = pf_id;
1853
+			break;
1854
+		default:
1855
+			break;
1856
+		}
1857
+
1858
+		/* Execute DMAE command */
1859
+		read_using_dmae = !qed_dmae_grc2host(p_hwfn,
1860
+						     p_ptt,
1861
+						     DWORDS_TO_BYTES(addr),
1862
+						     (u64)(uintptr_t)(dump_buf),
1863
+						     len, &dmae_params);
1864
+		if (!read_using_dmae) {
1865
+			dev_data->use_dmae = 0;
1866
+			DP_VERBOSE(p_hwfn,
1867
+				   QED_MSG_DEBUG,
1868
+				   "Failed reading from chip using DMAE, using GRC instead\n");
1869
+		}
25461870 	}
1871
+
1872
+	if (read_using_dmae)
1873
+		goto print_log;
25471874 
25481875 	/* If not read using DMAE, read using GRC */
25491876 
25501877 	/* Set pretend */
2551
-	if (split_type != dev_data->pretend.split_type || split_id !=
2552
-	    dev_data->pretend.split_id) {
1878
+	if (split_type != dev_data->pretend.split_type ||
1879
+	    split_id != dev_data->pretend.split_id) {
25531880 		switch (split_type) {
25541881 		case SPLIT_TYPE_PORT:
25551882 			qed_port_pretend(p_hwfn, p_ptt, port_id);
25561883 			break;
25571884 		case SPLIT_TYPE_PF:
2558
-			fid = pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT;
1885
+			fid = FIELD_VALUE(PXP_PRETEND_CONCRETE_FID_PFID,
1886
+					  pf_id);
25591887 			qed_fid_pretend(p_hwfn, p_ptt, fid);
25601888 			break;
25611889 		case SPLIT_TYPE_PORT_PF:
2562
-			fid = pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT;
1890
+			fid = FIELD_VALUE(PXP_PRETEND_CONCRETE_FID_PFID,
1891
+					  pf_id);
25631892 			qed_port_fid_pretend(p_hwfn, p_ptt, port_id, fid);
25641893 			break;
25651894 		case SPLIT_TYPE_VF:
2566
-			fid = BIT(PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT) |
2567
-			      (vf_id << PXP_PRETEND_CONCRETE_FID_VFID_SHIFT);
1895
+			fid = FIELD_VALUE(PXP_PRETEND_CONCRETE_FID_VFVALID, 1)
1896
+			      | FIELD_VALUE(PXP_PRETEND_CONCRETE_FID_VFID,
1897
+					  vf_id);
25681898 			qed_fid_pretend(p_hwfn, p_ptt, fid);
25691899 			break;
25701900 		default:
....@@ -2577,6 +1907,16 @@
25771907 
25781908 	/* Read registers using GRC */
25791909 	qed_read_regs(p_hwfn, p_ptt, dump_buf, addr, len);
1910
+
1911
+print_log:
1912
+	/* Print log */
1913
+	dev_data->num_regs_read += len;
1914
+	thresh = s_hw_type_defs[dev_data->hw_type].log_thresh;
1915
+	if ((dev_data->num_regs_read / thresh) >
1916
+	    ((dev_data->num_regs_read - len) / thresh))
1917
+		DP_VERBOSE(p_hwfn,
1918
+			   QED_MSG_DEBUG,
1919
+			   "Dumped %d registers...\n", dev_data->num_regs_read);
25801920 
25811921 	return len;
25821922 }
....@@ -2662,7 +2002,7 @@
26622002 /* Dumps GRC registers entries. Returns the dumped size in dwords. */
26632003 static u32 qed_grc_dump_regs_entries(struct qed_hwfn *p_hwfn,
26642004 				     struct qed_ptt *p_ptt,
2665
-				     struct dbg_array input_regs_arr,
2005
+				     struct virt_mem_desc input_regs_arr,
26662006 				     u32 *dump_buf,
26672007 				     bool dump,
26682008 				     enum init_split_types split_type,
....@@ -2675,10 +2015,10 @@
26752015 
26762016 	*num_dumped_reg_entries = 0;
26772017 
2678
-	while (input_offset < input_regs_arr.size_in_dwords) {
2018
+	while (input_offset < BYTES_TO_DWORDS(input_regs_arr.size)) {
26792019 		const struct dbg_dump_cond_hdr *cond_hdr =
26802020 		    (const struct dbg_dump_cond_hdr *)
2681
-		    &input_regs_arr.ptr[input_offset++];
2021
+		    input_regs_arr.ptr + input_offset++;
26822022 		u16 modes_buf_offset;
26832023 		bool eval_mode;
26842024 
....@@ -2701,7 +2041,7 @@
27012041 		for (i = 0; i < cond_hdr->data_size; i++, input_offset++) {
27022042 			const struct dbg_dump_reg *reg =
27032043 			    (const struct dbg_dump_reg *)
2704
-			    &input_regs_arr.ptr[input_offset];
2044
+			    input_regs_arr.ptr + input_offset;
27052045 			u32 addr, len;
27062046 			bool wide_bus;
27072047 
....@@ -2726,14 +2066,12 @@
27262066 /* Dumps GRC registers entries. Returns the dumped size in dwords. */
27272067 static u32 qed_grc_dump_split_data(struct qed_hwfn *p_hwfn,
27282068 				   struct qed_ptt *p_ptt,
2729
-				   struct dbg_array input_regs_arr,
2069
+				   struct virt_mem_desc input_regs_arr,
27302070 				   u32 *dump_buf,
27312071 				   bool dump,
27322072 				   bool block_enable[MAX_BLOCK_ID],
27332073 				   enum init_split_types split_type,
2734
-				   u8 split_id,
2735
-				   const char *param_name,
2736
-				   const char *param_val)
2074
+				   u8 split_id, const char *reg_type_name)
27372075 {
27382076 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
27392077 	enum init_split_types hdr_split_type = split_type;
....@@ -2751,7 +2089,7 @@
27512089 				       false,
27522090 				       0,
27532091 				       hdr_split_type,
2754
-				       hdr_split_id, param_name, param_val);
2092
+				       hdr_split_id, reg_type_name);
27552093 
27562094 	/* Dump registers */
27572095 	offset += qed_grc_dump_regs_entries(p_hwfn,
....@@ -2770,7 +2108,7 @@
27702108 				      dump,
27712109 				      num_dumped_reg_entries,
27722110 				      hdr_split_type,
2773
-				      hdr_split_id, param_name, param_val);
2111
+				      hdr_split_id, reg_type_name);
27742112 
27752113 	return num_dumped_reg_entries > 0 ? offset : 0;
27762114 }
....@@ -2783,32 +2121,33 @@
27832121 				  u32 *dump_buf,
27842122 				  bool dump,
27852123 				  bool block_enable[MAX_BLOCK_ID],
2786
-				  const char *param_name, const char *param_val)
2124
+				  const char *reg_type_name)
27872125 {
2126
+	struct virt_mem_desc *dbg_buf =
2127
+	    &p_hwfn->dbg_arrays[BIN_BUF_DBG_DUMP_REG];
27882128 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
27892129 	u32 offset = 0, input_offset = 0;
2790
-	u16 fid;
2791
-	while (input_offset <
2792
-	       s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].size_in_dwords) {
2130
+
2131
+	while (input_offset < BYTES_TO_DWORDS(dbg_buf->size)) {
27932132 		const struct dbg_dump_split_hdr *split_hdr;
2794
-		struct dbg_array curr_input_regs_arr;
2133
+		struct virt_mem_desc curr_input_regs_arr;
27952134 		enum init_split_types split_type;
27962135 		u16 split_count = 0;
27972136 		u32 split_data_size;
27982137 		u8 split_id;
27992138 
28002139 		split_hdr =
2801
-			(const struct dbg_dump_split_hdr *)
2802
-			&s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr[input_offset++];
2140
+		    (const struct dbg_dump_split_hdr *)
2141
+		    dbg_buf->ptr + input_offset++;
28032142 		split_type =
2804
-			GET_FIELD(split_hdr->hdr,
2805
-				  DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID);
2806
-		split_data_size =
2807
-			GET_FIELD(split_hdr->hdr,
2808
-				  DBG_DUMP_SPLIT_HDR_DATA_SIZE);
2143
+		    GET_FIELD(split_hdr->hdr,
2144
+			      DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID);
2145
+		split_data_size = GET_FIELD(split_hdr->hdr,
2146
+					    DBG_DUMP_SPLIT_HDR_DATA_SIZE);
28092147 		curr_input_regs_arr.ptr =
2810
-			&s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr[input_offset];
2811
-		curr_input_regs_arr.size_in_dwords = split_data_size;
2148
+		    (u32 *)p_hwfn->dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr +
2149
+		    input_offset;
2150
+		curr_input_regs_arr.size = DWORDS_TO_BYTES(split_data_size);
28122151 
28132152 		switch (split_type) {
28142153 		case SPLIT_TYPE_NONE:
....@@ -2836,16 +2175,16 @@
28362175 							  dump, block_enable,
28372176 							  split_type,
28382177 							  split_id,
2839
-							  param_name,
2840
-							  param_val);
2178
+							  reg_type_name);
28412179 
28422180 		input_offset += split_data_size;
28432181 	}
28442182 
28452183 	/* Cancel pretends (pretend to original PF) */
28462184 	if (dump) {
2847
-		fid = p_hwfn->rel_pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT;
2848
-		qed_fid_pretend(p_hwfn, p_ptt, fid);
2185
+		qed_fid_pretend(p_hwfn, p_ptt,
2186
+				FIELD_VALUE(PXP_PRETEND_CONCRETE_FID_PFID,
2187
+					    p_hwfn->rel_pf_id));
28492188 		dev_data->pretend.split_type = SPLIT_TYPE_NONE;
28502189 		dev_data->pretend.split_id = 0;
28512190 	}
....@@ -2858,26 +2197,32 @@
28582197 				   struct qed_ptt *p_ptt,
28592198 				   u32 *dump_buf, bool dump)
28602199 {
2861
-	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2862
-	u32 i, offset = 0, num_regs = 0;
2200
+	u32 offset = 0, num_regs = 0;
2201
+	u8 reset_reg_id;
28632202 
28642203 	/* Calculate header size */
28652204 	offset += qed_grc_dump_regs_hdr(dump_buf,
2866
-					false, 0,
2867
-					SPLIT_TYPE_NONE, 0, NULL, NULL);
2205
+					false,
2206
+					0, SPLIT_TYPE_NONE, 0, "RESET_REGS");
28682207 
28692208 	/* Write reset registers */
2870
-	for (i = 0; i < MAX_DBG_RESET_REGS; i++) {
2871
-		if (!s_reset_regs_defs[i].exists[dev_data->chip_id])
2209
+	for (reset_reg_id = 0; reset_reg_id < NUM_DBG_RESET_REGS;
2210
+	     reset_reg_id++) {
2211
+		const struct dbg_reset_reg *reset_reg;
2212
+		u32 reset_reg_addr;
2213
+
2214
+		reset_reg = qed_get_dbg_reset_reg(p_hwfn, reset_reg_id);
2215
+
2216
+		if (GET_FIELD(reset_reg->data, DBG_RESET_REG_IS_REMOVED))
28722217 			continue;
28732218 
2219
+		reset_reg_addr = GET_FIELD(reset_reg->data, DBG_RESET_REG_ADDR);
28742220 		offset += qed_grc_dump_reg_entry(p_hwfn,
28752221 						 p_ptt,
28762222 						 dump_buf + offset,
28772223 						 dump,
2878
-						 BYTES_TO_DWORDS
2879
-						 (s_reset_regs_defs[i].addr), 1,
2880
-						 false, SPLIT_TYPE_NONE, 0);
2224
+						 reset_reg_addr,
2225
+						 1, false, SPLIT_TYPE_NONE, 0);
28812226 		num_regs++;
28822227 	}
28832228 
....@@ -2885,7 +2230,7 @@
28852230 	if (dump)
28862231 		qed_grc_dump_regs_hdr(dump_buf,
28872232 				      true, num_regs, SPLIT_TYPE_NONE,
2888
-				      0, NULL, NULL);
2233
+				      0, "RESET_REGS");
28892234 
28902235 	return offset;
28912236 }
....@@ -2898,21 +2243,23 @@
28982243 				      u32 *dump_buf, bool dump)
28992244 {
29002245 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2901
-	u32 block_id, offset = 0, num_reg_entries = 0;
2246
+	u32 block_id, offset = 0, stall_regs_offset;
29022247 	const struct dbg_attn_reg *attn_reg_arr;
29032248 	u8 storm_id, reg_idx, num_attn_regs;
2249
+	u32 num_reg_entries = 0;
29042250 
2905
-	/* Calculate header size */
2251
+	/* Write empty header for attention registers */
29062252 	offset += qed_grc_dump_regs_hdr(dump_buf,
2907
-					false, 0, SPLIT_TYPE_NONE,
2908
-					0, NULL, NULL);
2253
+					false,
2254
+					0, SPLIT_TYPE_NONE, 0, "ATTN_REGS");
29092255 
29102256 	/* Write parity registers */
2911
-	for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
2257
+	for (block_id = 0; block_id < NUM_PHYS_BLOCKS; block_id++) {
29122258 		if (dev_data->block_in_reset[block_id] && dump)
29132259 			continue;
29142260 
2915
-		attn_reg_arr = qed_get_block_attn_regs((enum block_id)block_id,
2261
+		attn_reg_arr = qed_get_block_attn_regs(p_hwfn,
2262
+						       (enum block_id)block_id,
29162263 						       ATTN_TYPE_PARITY,
29172264 						       &num_attn_regs);
29182265 
....@@ -2955,16 +2302,29 @@
29552302 		}
29562303 	}
29572304 
2305
+	/* Overwrite header for attention registers */
2306
+	if (dump)
2307
+		qed_grc_dump_regs_hdr(dump_buf,
2308
+				      true,
2309
+				      num_reg_entries,
2310
+				      SPLIT_TYPE_NONE, 0, "ATTN_REGS");
2311
+
2312
+	/* Write empty header for stall registers */
2313
+	stall_regs_offset = offset;
2314
+	offset += qed_grc_dump_regs_hdr(dump_buf,
2315
+					false, 0, SPLIT_TYPE_NONE, 0, "REGS");
2316
+
29582317 	/* Write Storm stall status registers */
2959
-	for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
2318
+	for (storm_id = 0, num_reg_entries = 0; storm_id < MAX_DBG_STORMS;
2319
+	     storm_id++) {
29602320 		struct storm_defs *storm = &s_storm_defs[storm_id];
29612321 		u32 addr;
29622322 
2963
-		if (dev_data->block_in_reset[storm->block_id] && dump)
2323
+		if (dev_data->block_in_reset[storm->sem_block_id] && dump)
29642324 			continue;
29652325 
29662326 		addr =
2967
-		    BYTES_TO_DWORDS(s_storm_defs[storm_id].sem_fast_mem_addr +
2327
+		    BYTES_TO_DWORDS(storm->sem_fast_mem_addr +
29682328 				    SEM_FAST_REG_STALLED);
29692329 		offset += qed_grc_dump_reg_entry(p_hwfn,
29702330 						 p_ptt,
....@@ -2976,12 +2336,12 @@
29762336 		num_reg_entries++;
29772337 	}
29782338 
2979
-	/* Write header */
2339
+	/* Overwrite header for stall registers */
29802340 	if (dump)
2981
-		qed_grc_dump_regs_hdr(dump_buf,
2341
+		qed_grc_dump_regs_hdr(dump_buf + stall_regs_offset,
29822342 				      true,
2983
-				      num_reg_entries, SPLIT_TYPE_NONE,
2984
-				      0, NULL, NULL);
2343
+				      num_reg_entries,
2344
+				      SPLIT_TYPE_NONE, 0, "REGS");
29852345 
29862346 	return offset;
29872347 }
....@@ -2994,8 +2354,7 @@
29942354 	u32 offset = 0, addr;
29952355 
29962356 	offset += qed_grc_dump_regs_hdr(dump_buf,
2997
-					dump, 2, SPLIT_TYPE_NONE, 0,
2998
-					NULL, NULL);
2357
+					dump, 2, SPLIT_TYPE_NONE, 0, "REGS");
29992358 
30002359 	/* Dump R/TDIF_REG_DEBUG_ERROR_INFO_SIZE (every 8'th register should be
30012360 	 * skipped).
....@@ -3043,8 +2402,7 @@
30432402 				u32 len,
30442403 				u32 bit_width,
30452404 				bool packed,
3046
-				const char *mem_group,
3047
-				bool is_storm, char storm_letter)
2405
+				const char *mem_group, char storm_letter)
30482406 {
30492407 	u8 num_params = 3;
30502408 	u32 offset = 0;
....@@ -3065,7 +2423,7 @@
30652423 
30662424 	if (name) {
30672425 		/* Dump name */
3068
-		if (is_storm) {
2426
+		if (storm_letter) {
30692427 			strcpy(buf, "?STORM_");
30702428 			buf[0] = storm_letter;
30712429 			strcpy(buf + strlen(buf), name);
....@@ -3097,7 +2455,7 @@
30972455 					     dump, "packed", 1);
30982456 
30992457 	/* Dump reg type */
3100
-	if (is_storm) {
2458
+	if (storm_letter) {
31012459 		strcpy(buf, "?STORM_");
31022460 		buf[0] = storm_letter;
31032461 		strcpy(buf + strlen(buf), mem_group);
....@@ -3124,8 +2482,7 @@
31242482 			    bool wide_bus,
31252483 			    u32 bit_width,
31262484 			    bool packed,
3127
-			    const char *mem_group,
3128
-			    bool is_storm, char storm_letter)
2485
+			    const char *mem_group, char storm_letter)
31292486 {
31302487 	u32 offset = 0;
31312488 
....@@ -3136,8 +2493,7 @@
31362493 				       addr,
31372494 				       len,
31382495 				       bit_width,
3139
-				       packed,
3140
-				       mem_group, is_storm, storm_letter);
2496
+				       packed, mem_group, storm_letter);
31412497 	offset += qed_grc_dump_addr_range(p_hwfn,
31422498 					  p_ptt,
31432499 					  dump_buf + offset,
....@@ -3150,20 +2506,21 @@
31502506 /* Dumps GRC memories entries. Returns the dumped size in dwords. */
31512507 static u32 qed_grc_dump_mem_entries(struct qed_hwfn *p_hwfn,
31522508 				    struct qed_ptt *p_ptt,
3153
-				    struct dbg_array input_mems_arr,
2509
+				    struct virt_mem_desc input_mems_arr,
31542510 				    u32 *dump_buf, bool dump)
31552511 {
31562512 	u32 i, offset = 0, input_offset = 0;
31572513 	bool mode_match = true;
31582514 
3159
-	while (input_offset < input_mems_arr.size_in_dwords) {
2515
+	while (input_offset < BYTES_TO_DWORDS(input_mems_arr.size)) {
31602516 		const struct dbg_dump_cond_hdr *cond_hdr;
31612517 		u16 modes_buf_offset;
31622518 		u32 num_entries;
31632519 		bool eval_mode;
31642520 
3165
-		cond_hdr = (const struct dbg_dump_cond_hdr *)
3166
-			   &input_mems_arr.ptr[input_offset++];
2521
+		cond_hdr =
2522
+		    (const struct dbg_dump_cond_hdr *)input_mems_arr.ptr +
2523
+		    input_offset++;
31672524 		num_entries = cond_hdr->data_size / MEM_DUMP_ENTRY_SIZE_DWORDS;
31682525 
31692526 		/* Check required mode */
....@@ -3185,24 +2542,25 @@
31852542 		for (i = 0; i < num_entries;
31862543 		     i++, input_offset += MEM_DUMP_ENTRY_SIZE_DWORDS) {
31872544 			const struct dbg_dump_mem *mem =
3188
-				(const struct dbg_dump_mem *)
3189
-				&input_mems_arr.ptr[input_offset];
3190
-			u8 mem_group_id = GET_FIELD(mem->dword0,
3191
-						    DBG_DUMP_MEM_MEM_GROUP_ID);
3192
-			bool is_storm = false, mem_wide_bus;
3193
-			enum dbg_grc_params grc_param;
3194
-			char storm_letter = 'a';
3195
-			enum block_id block_id;
2545
+			    (const struct dbg_dump_mem *)((u32 *)
2546
+							  input_mems_arr.ptr
2547
+							  + input_offset);
2548
+			const struct dbg_block *block;
2549
+			char storm_letter = 0;
31962550 			u32 mem_addr, mem_len;
2551
+			bool mem_wide_bus;
2552
+			u8 mem_group_id;
31972553 
2554
+			mem_group_id = GET_FIELD(mem->dword0,
2555
+						 DBG_DUMP_MEM_MEM_GROUP_ID);
31982556 			if (mem_group_id >= MEM_GROUPS_NUM) {
31992557 				DP_NOTICE(p_hwfn, "Invalid mem_group_id\n");
32002558 				return 0;
32012559 			}
32022560 
3203
-			block_id = (enum block_id)cond_hdr->block_id;
32042561 			if (!qed_grc_is_mem_included(p_hwfn,
3205
-						     block_id,
2562
+						     (enum block_id)
2563
+						     cond_hdr->block_id,
32062564 						     mem_group_id))
32072565 				continue;
32082566 
....@@ -3211,42 +2569,14 @@
32112569 			mem_wide_bus = GET_FIELD(mem->dword1,
32122570 						 DBG_DUMP_MEM_WIDE_BUS);
32132571 
3214
-			/* Update memory length for CCFC/TCFC memories
3215
-			 * according to number of LCIDs/LTIDs.
2572
+			block = get_dbg_block(p_hwfn,
2573
+					      cond_hdr->block_id);
2574
+
2575
+			/* If memory is associated with Storm,
2576
+			 * update storm details
32162577 			 */
3217
-			if (mem_group_id == MEM_GROUP_CONN_CFC_MEM) {
3218
-				if (mem_len % MAX_LCIDS) {
3219
-					DP_NOTICE(p_hwfn,
3220
-						  "Invalid CCFC connection memory size\n");
3221
-					return 0;
3222
-				}
3223
-
3224
-				grc_param = DBG_GRC_PARAM_NUM_LCIDS;
3225
-				mem_len = qed_grc_get_param(p_hwfn, grc_param) *
3226
-					  (mem_len / MAX_LCIDS);
3227
-			} else if (mem_group_id == MEM_GROUP_TASK_CFC_MEM) {
3228
-				if (mem_len % MAX_LTIDS) {
3229
-					DP_NOTICE(p_hwfn,
3230
-						  "Invalid TCFC task memory size\n");
3231
-					return 0;
3232
-				}
3233
-
3234
-				grc_param = DBG_GRC_PARAM_NUM_LTIDS;
3235
-				mem_len = qed_grc_get_param(p_hwfn, grc_param) *
3236
-					  (mem_len / MAX_LTIDS);
3237
-			}
3238
-
3239
-			/* If memory is associated with Storm, update Storm
3240
-			 * details.
3241
-			 */
3242
-			if (s_block_defs
3243
-			    [cond_hdr->block_id]->associated_to_storm) {
3244
-				is_storm = true;
3245
-				storm_letter =
3246
-				    s_storm_defs[s_block_defs
3247
-						 [cond_hdr->block_id]->
3248
-						 storm_id].letter;
3249
-			}
2578
+			if (block->associated_storm_letter)
2579
+				storm_letter = block->associated_storm_letter;
32502580 
32512581 			/* Dump memory */
32522582 			offset += qed_grc_dump_mem(p_hwfn,
....@@ -3260,7 +2590,6 @@
32602590 						0,
32612591 						false,
32622592 						s_mem_group_names[mem_group_id],
3263
-						is_storm,
32642593 						storm_letter);
32652594 		}
32662595 	}
....@@ -3275,26 +2604,25 @@
32752604 				 struct qed_ptt *p_ptt,
32762605 				 u32 *dump_buf, bool dump)
32772606 {
2607
+	struct virt_mem_desc *dbg_buf =
2608
+	    &p_hwfn->dbg_arrays[BIN_BUF_DBG_DUMP_MEM];
32782609 	u32 offset = 0, input_offset = 0;
32792610 
3280
-	while (input_offset <
3281
-	       s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].size_in_dwords) {
2611
+	while (input_offset < BYTES_TO_DWORDS(dbg_buf->size)) {
32822612 		const struct dbg_dump_split_hdr *split_hdr;
3283
-		struct dbg_array curr_input_mems_arr;
2613
+		struct virt_mem_desc curr_input_mems_arr;
32842614 		enum init_split_types split_type;
32852615 		u32 split_data_size;
32862616 
3287
-		split_hdr = (const struct dbg_dump_split_hdr *)
3288
-			&s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr[input_offset++];
3289
-		split_type =
3290
-			GET_FIELD(split_hdr->hdr,
3291
-				  DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID);
3292
-		split_data_size =
3293
-			GET_FIELD(split_hdr->hdr,
3294
-				  DBG_DUMP_SPLIT_HDR_DATA_SIZE);
3295
-		curr_input_mems_arr.ptr =
3296
-			&s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr[input_offset];
3297
-		curr_input_mems_arr.size_in_dwords = split_data_size;
2617
+		split_hdr =
2618
+		    (const struct dbg_dump_split_hdr *)dbg_buf->ptr +
2619
+		    input_offset++;
2620
+		split_type = GET_FIELD(split_hdr->hdr,
2621
+				       DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID);
2622
+		split_data_size = GET_FIELD(split_hdr->hdr,
2623
+					    DBG_DUMP_SPLIT_HDR_DATA_SIZE);
2624
+		curr_input_mems_arr.ptr = (u32 *)dbg_buf->ptr + input_offset;
2625
+		curr_input_mems_arr.size = DWORDS_TO_BYTES(split_data_size);
32982626 
32992627 		if (split_type == SPLIT_TYPE_NONE)
33002628 			offset += qed_grc_dump_mem_entries(p_hwfn,
....@@ -3322,17 +2650,19 @@
33222650 				 bool dump,
33232651 				 const char *name,
33242652 				 u32 num_lids,
3325
-				 u32 lid_size,
3326
-				 u32 rd_reg_addr,
3327
-				 u8 storm_id)
2653
+				 enum cm_ctx_types ctx_type, u8 storm_id)
33282654 {
2655
+	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
33292656 	struct storm_defs *storm = &s_storm_defs[storm_id];
3330
-	u32 i, lid, total_size, offset = 0;
2657
+	u32 i, lid, lid_size, total_size;
2658
+	u32 rd_reg_addr, offset = 0;
2659
+
2660
+	/* Convert quad-regs to dwords */
2661
+	lid_size = storm->cm_ctx_lid_sizes[dev_data->chip_id][ctx_type] * 4;
33312662 
33322663 	if (!lid_size)
33332664 		return 0;
33342665 
3335
-	lid_size *= BYTES_IN_DWORD;
33362666 	total_size = num_lids * lid_size;
33372667 
33382668 	offset += qed_grc_dump_mem_hdr(p_hwfn,
....@@ -3342,18 +2672,26 @@
33422672 				       0,
33432673 				       total_size,
33442674 				       lid_size * 32,
3345
-				       false, name, true, storm->letter);
2675
+				       false, name, storm->letter);
33462676 
33472677 	if (!dump)
33482678 		return offset + total_size;
33492679 
2680
+	rd_reg_addr = BYTES_TO_DWORDS(storm->cm_ctx_rd_addr[ctx_type]);
2681
+
33502682 	/* Dump context data */
33512683 	for (lid = 0; lid < num_lids; lid++) {
3352
-		for (i = 0; i < lid_size; i++, offset++) {
2684
+		for (i = 0; i < lid_size; i++) {
33532685 			qed_wr(p_hwfn,
33542686 			       p_ptt, storm->cm_ctx_wr_addr, (i << 9) | lid);
3355
-			*(dump_buf + offset) = qed_rd(p_hwfn,
3356
-						      p_ptt, rd_reg_addr);
2687
+			offset += qed_grc_dump_addr_range(p_hwfn,
2688
+							  p_ptt,
2689
+							  dump_buf + offset,
2690
+							  dump,
2691
+							  rd_reg_addr,
2692
+							  1,
2693
+							  false,
2694
+							  SPLIT_TYPE_NONE, 0);
33572695 		}
33582696 	}
33592697 
....@@ -3364,114 +2702,126 @@
33642702 static u32 qed_grc_dump_ctx(struct qed_hwfn *p_hwfn,
33652703 			    struct qed_ptt *p_ptt, u32 *dump_buf, bool dump)
33662704 {
3367
-	enum dbg_grc_params grc_param;
33682705 	u32 offset = 0;
33692706 	u8 storm_id;
33702707 
33712708 	for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
3372
-		struct storm_defs *storm = &s_storm_defs[storm_id];
3373
-
33742709 		if (!qed_grc_is_storm_included(p_hwfn,
33752710 					       (enum dbg_storms)storm_id))
33762711 			continue;
33772712 
33782713 		/* Dump Conn AG context size */
3379
-		grc_param = DBG_GRC_PARAM_NUM_LCIDS;
3380
-		offset +=
3381
-			qed_grc_dump_ctx_data(p_hwfn,
3382
-					      p_ptt,
3383
-					      dump_buf + offset,
3384
-					      dump,
3385
-					      "CONN_AG_CTX",
3386
-					      qed_grc_get_param(p_hwfn,
3387
-								grc_param),
3388
-					      storm->cm_conn_ag_ctx_lid_size,
3389
-					      storm->cm_conn_ag_ctx_rd_addr,
3390
-					      storm_id);
2714
+		offset += qed_grc_dump_ctx_data(p_hwfn,
2715
+						p_ptt,
2716
+						dump_buf + offset,
2717
+						dump,
2718
+						"CONN_AG_CTX",
2719
+						NUM_OF_LCIDS,
2720
+						CM_CTX_CONN_AG, storm_id);
33912721 
33922722 		/* Dump Conn ST context size */
3393
-		grc_param = DBG_GRC_PARAM_NUM_LCIDS;
3394
-		offset +=
3395
-			qed_grc_dump_ctx_data(p_hwfn,
3396
-					      p_ptt,
3397
-					      dump_buf + offset,
3398
-					      dump,
3399
-					      "CONN_ST_CTX",
3400
-					      qed_grc_get_param(p_hwfn,
3401
-								grc_param),
3402
-					      storm->cm_conn_st_ctx_lid_size,
3403
-					      storm->cm_conn_st_ctx_rd_addr,
3404
-					      storm_id);
2723
+		offset += qed_grc_dump_ctx_data(p_hwfn,
2724
+						p_ptt,
2725
+						dump_buf + offset,
2726
+						dump,
2727
+						"CONN_ST_CTX",
2728
+						NUM_OF_LCIDS,
2729
+						CM_CTX_CONN_ST, storm_id);
34052730 
34062731 		/* Dump Task AG context size */
3407
-		grc_param = DBG_GRC_PARAM_NUM_LTIDS;
3408
-		offset +=
3409
-			qed_grc_dump_ctx_data(p_hwfn,
3410
-					      p_ptt,
3411
-					      dump_buf + offset,
3412
-					      dump,
3413
-					      "TASK_AG_CTX",
3414
-					      qed_grc_get_param(p_hwfn,
3415
-								grc_param),
3416
-					      storm->cm_task_ag_ctx_lid_size,
3417
-					      storm->cm_task_ag_ctx_rd_addr,
3418
-					      storm_id);
2732
+		offset += qed_grc_dump_ctx_data(p_hwfn,
2733
+						p_ptt,
2734
+						dump_buf + offset,
2735
+						dump,
2736
+						"TASK_AG_CTX",
2737
+						NUM_OF_LTIDS,
2738
+						CM_CTX_TASK_AG, storm_id);
34192739 
34202740 		/* Dump Task ST context size */
3421
-		grc_param = DBG_GRC_PARAM_NUM_LTIDS;
3422
-		offset +=
3423
-			qed_grc_dump_ctx_data(p_hwfn,
3424
-					      p_ptt,
3425
-					      dump_buf + offset,
3426
-					      dump,
3427
-					      "TASK_ST_CTX",
3428
-					      qed_grc_get_param(p_hwfn,
3429
-								grc_param),
3430
-					      storm->cm_task_st_ctx_lid_size,
3431
-					      storm->cm_task_st_ctx_rd_addr,
3432
-					      storm_id);
2741
+		offset += qed_grc_dump_ctx_data(p_hwfn,
2742
+						p_ptt,
2743
+						dump_buf + offset,
2744
+						dump,
2745
+						"TASK_ST_CTX",
2746
+						NUM_OF_LTIDS,
2747
+						CM_CTX_TASK_ST, storm_id);
34332748 	}
34342749 
34352750 	return offset;
34362751 }
34372752 
3438
-/* Dumps GRC IORs data. Returns the dumped size in dwords. */
3439
-static u32 qed_grc_dump_iors(struct qed_hwfn *p_hwfn,
3440
-			     struct qed_ptt *p_ptt, u32 *dump_buf, bool dump)
2753
+#define VFC_STATUS_RESP_READY_BIT	0
2754
+#define VFC_STATUS_BUSY_BIT		1
2755
+#define VFC_STATUS_SENDING_CMD_BIT	2
2756
+
2757
+#define VFC_POLLING_DELAY_MS	1
2758
+#define VFC_POLLING_COUNT		20
2759
+
2760
+/* Reads data from VFC. Returns the number of dwords read (0 on error).
2761
+ * Sizes are specified in dwords.
2762
+ */
2763
+static u32 qed_grc_dump_read_from_vfc(struct qed_hwfn *p_hwfn,
2764
+				      struct qed_ptt *p_ptt,
2765
+				      struct storm_defs *storm,
2766
+				      u32 *cmd_data,
2767
+				      u32 cmd_size,
2768
+				      u32 *addr_data,
2769
+				      u32 addr_size,
2770
+				      u32 resp_size, u32 *dump_buf)
34412771 {
3442
-	char buf[10] = "IOR_SET_?";
3443
-	u32 addr, offset = 0;
3444
-	u8 storm_id, set_id;
2772
+	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
2773
+	u32 vfc_status, polling_ms, polling_count = 0, i;
2774
+	u32 reg_addr, sem_base;
2775
+	bool is_ready = false;
34452776 
3446
-	for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
3447
-		struct storm_defs *storm = &s_storm_defs[storm_id];
2777
+	sem_base = storm->sem_fast_mem_addr;
2778
+	polling_ms = VFC_POLLING_DELAY_MS *
2779
+	    s_hw_type_defs[dev_data->hw_type].delay_factor;
34482780 
3449
-		if (!qed_grc_is_storm_included(p_hwfn,
3450
-					       (enum dbg_storms)storm_id))
3451
-			continue;
2781
+	/* Write VFC command */
2782
+	ARR_REG_WR(p_hwfn,
2783
+		   p_ptt,
2784
+		   sem_base + SEM_FAST_REG_VFC_DATA_WR,
2785
+		   cmd_data, cmd_size);
34522786 
3453
-		for (set_id = 0; set_id < NUM_IOR_SETS; set_id++) {
3454
-			addr = BYTES_TO_DWORDS(storm->sem_fast_mem_addr +
3455
-					       SEM_FAST_REG_STORM_REG_FILE) +
3456
-			       IOR_SET_OFFSET(set_id);
3457
-			buf[strlen(buf) - 1] = '0' + set_id;
3458
-			offset += qed_grc_dump_mem(p_hwfn,
3459
-						   p_ptt,
3460
-						   dump_buf + offset,
3461
-						   dump,
3462
-						   buf,
3463
-						   addr,
3464
-						   IORS_PER_SET,
3465
-						   false,
3466
-						   32,
3467
-						   false,
3468
-						   "ior",
3469
-						   true,
3470
-						   storm->letter);
3471
-		}
2787
+	/* Write VFC address */
2788
+	ARR_REG_WR(p_hwfn,
2789
+		   p_ptt,
2790
+		   sem_base + SEM_FAST_REG_VFC_ADDR,
2791
+		   addr_data, addr_size);
2792
+
2793
+	/* Read response */
2794
+	for (i = 0; i < resp_size; i++) {
2795
+		/* Poll until ready */
2796
+		do {
2797
+			reg_addr = sem_base + SEM_FAST_REG_VFC_STATUS;
2798
+			qed_grc_dump_addr_range(p_hwfn,
2799
+						p_ptt,
2800
+						&vfc_status,
2801
+						true,
2802
+						BYTES_TO_DWORDS(reg_addr),
2803
+						1,
2804
+						false, SPLIT_TYPE_NONE, 0);
2805
+			is_ready = vfc_status & BIT(VFC_STATUS_RESP_READY_BIT);
2806
+
2807
+			if (!is_ready) {
2808
+				if (polling_count++ == VFC_POLLING_COUNT)
2809
+					return 0;
2810
+
2811
+				msleep(polling_ms);
2812
+			}
2813
+		} while (!is_ready);
2814
+
2815
+		reg_addr = sem_base + SEM_FAST_REG_VFC_DATA_RD;
2816
+		qed_grc_dump_addr_range(p_hwfn,
2817
+					p_ptt,
2818
+					dump_buf + i,
2819
+					true,
2820
+					BYTES_TO_DWORDS(reg_addr),
2821
+					1, false, SPLIT_TYPE_NONE, 0);
34722822 	}
34732823 
3474
-	return offset;
2824
+	return resp_size;
34752825 }
34762826 
34772827 /* Dump VFC CAM. Returns the dumped size in dwords. */
....@@ -3483,7 +2833,7 @@
34832833 	struct storm_defs *storm = &s_storm_defs[storm_id];
34842834 	u32 cam_addr[VFC_CAM_ADDR_DWORDS] = { 0 };
34852835 	u32 cam_cmd[VFC_CAM_CMD_DWORDS] = { 0 };
3486
-	u32 row, i, offset = 0;
2836
+	u32 row, offset = 0;
34872837 
34882838 	offset += qed_grc_dump_mem_hdr(p_hwfn,
34892839 				       dump_buf + offset,
....@@ -3492,7 +2842,7 @@
34922842 				       0,
34932843 				       total_size,
34942844 				       256,
3495
-				       false, "vfc_cam", true, storm->letter);
2845
+				       false, "vfc_cam", storm->letter);
34962846 
34972847 	if (!dump)
34982848 		return offset + total_size;
....@@ -3500,26 +2850,18 @@
35002850 	/* Prepare CAM address */
35012851 	SET_VAR_FIELD(cam_addr, VFC_CAM_ADDR, OP, VFC_OPCODE_CAM_RD);
35022852 
3503
-	for (row = 0; row < VFC_CAM_NUM_ROWS;
3504
-	     row++, offset += VFC_CAM_RESP_DWORDS) {
3505
-		/* Write VFC CAM command */
2853
+	/* Read VFC CAM data */
2854
+	for (row = 0; row < VFC_CAM_NUM_ROWS; row++) {
35062855 		SET_VAR_FIELD(cam_cmd, VFC_CAM_CMD, ROW, row);
3507
-		ARR_REG_WR(p_hwfn,
3508
-			   p_ptt,
3509
-			   storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_WR,
3510
-			   cam_cmd, VFC_CAM_CMD_DWORDS);
3511
-
3512
-		/* Write VFC CAM address */
3513
-		ARR_REG_WR(p_hwfn,
3514
-			   p_ptt,
3515
-			   storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_ADDR,
3516
-			   cam_addr, VFC_CAM_ADDR_DWORDS);
3517
-
3518
-		/* Read VFC CAM read response */
3519
-		ARR_REG_RD(p_hwfn,
3520
-			   p_ptt,
3521
-			   storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_RD,
3522
-			   dump_buf + offset, VFC_CAM_RESP_DWORDS);
2856
+		offset += qed_grc_dump_read_from_vfc(p_hwfn,
2857
+						     p_ptt,
2858
+						     storm,
2859
+						     cam_cmd,
2860
+						     VFC_CAM_CMD_DWORDS,
2861
+						     cam_addr,
2862
+						     VFC_CAM_ADDR_DWORDS,
2863
+						     VFC_CAM_RESP_DWORDS,
2864
+						     dump_buf + offset);
35232865 	}
35242866 
35252867 	return offset;
....@@ -3536,7 +2878,7 @@
35362878 	struct storm_defs *storm = &s_storm_defs[storm_id];
35372879 	u32 ram_addr[VFC_RAM_ADDR_DWORDS] = { 0 };
35382880 	u32 ram_cmd[VFC_RAM_CMD_DWORDS] = { 0 };
3539
-	u32 row, i, offset = 0;
2881
+	u32 row, offset = 0;
35402882 
35412883 	offset += qed_grc_dump_mem_hdr(p_hwfn,
35422884 				       dump_buf + offset,
....@@ -3547,35 +2889,27 @@
35472889 				       256,
35482890 				       false,
35492891 				       ram_defs->type_name,
3550
-				       true, storm->letter);
3551
-
3552
-	/* Prepare RAM address */
3553
-	SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, OP, VFC_OPCODE_RAM_RD);
2892
+				       storm->letter);
35542893 
35552894 	if (!dump)
35562895 		return offset + total_size;
35572896 
2897
+	/* Prepare RAM address */
2898
+	SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, OP, VFC_OPCODE_RAM_RD);
2899
+
2900
+	/* Read VFC RAM data */
35582901 	for (row = ram_defs->base_row;
3559
-	     row < ram_defs->base_row + ram_defs->num_rows;
3560
-	     row++, offset += VFC_RAM_RESP_DWORDS) {
3561
-		/* Write VFC RAM command */
3562
-		ARR_REG_WR(p_hwfn,
3563
-			   p_ptt,
3564
-			   storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_WR,
3565
-			   ram_cmd, VFC_RAM_CMD_DWORDS);
3566
-
3567
-		/* Write VFC RAM address */
2902
+	     row < ram_defs->base_row + ram_defs->num_rows; row++) {
35682903 		SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, ROW, row);
3569
-		ARR_REG_WR(p_hwfn,
3570
-			   p_ptt,
3571
-			   storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_ADDR,
3572
-			   ram_addr, VFC_RAM_ADDR_DWORDS);
3573
-
3574
-		/* Read VFC RAM read response */
3575
-		ARR_REG_RD(p_hwfn,
3576
-			   p_ptt,
3577
-			   storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_RD,
3578
-			   dump_buf + offset, VFC_RAM_RESP_DWORDS);
2904
+		offset += qed_grc_dump_read_from_vfc(p_hwfn,
2905
+						     p_ptt,
2906
+						     storm,
2907
+						     ram_cmd,
2908
+						     VFC_RAM_CMD_DWORDS,
2909
+						     ram_addr,
2910
+						     VFC_RAM_ADDR_DWORDS,
2911
+						     VFC_RAM_RESP_DWORDS,
2912
+						     dump_buf + offset);
35792913 	}
35802914 
35812915 	return offset;
....@@ -3585,16 +2919,13 @@
35852919 static u32 qed_grc_dump_vfc(struct qed_hwfn *p_hwfn,
35862920 			    struct qed_ptt *p_ptt, u32 *dump_buf, bool dump)
35872921 {
3588
-	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
35892922 	u8 storm_id, i;
35902923 	u32 offset = 0;
35912924 
35922925 	for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) {
35932926 		if (!qed_grc_is_storm_included(p_hwfn,
35942927 					       (enum dbg_storms)storm_id) ||
3595
-		    !s_storm_defs[storm_id].has_vfc ||
3596
-		    (storm_id == DBG_PSTORM_ID && dev_data->platform_id !=
3597
-		     PLATFORM_ASIC))
2928
+		    !s_storm_defs[storm_id].has_vfc)
35982929 			continue;
35992930 
36002931 		/* Read CAM */
....@@ -3644,7 +2975,7 @@
36442975 					       total_dwords,
36452976 					       rss_defs->entry_width,
36462977 					       packed,
3647
-					       rss_defs->type_name, false, 0);
2978
+					       rss_defs->type_name, 0);
36482979 
36492980 		/* Dump RSS data */
36502981 		if (!dump) {
....@@ -3704,7 +3035,7 @@
37043035 				       0,
37053036 				       ram_size,
37063037 				       block_size * 8,
3707
-				       false, type_name, false, 0);
3038
+				       false, type_name, 0);
37083039 
37093040 	/* Read and dump Big RAM data */
37103041 	if (!dump)
....@@ -3730,6 +3061,7 @@
37303061 	return offset;
37313062 }
37323063 
3064
+/* Dumps MCP scratchpad. Returns the dumped size in dwords. */
37333065 static u32 qed_grc_dump_mcp(struct qed_hwfn *p_hwfn,
37343066 			    struct qed_ptt *p_ptt, u32 *dump_buf, bool dump)
37353067 {
....@@ -3751,8 +3083,8 @@
37513083 				   dump,
37523084 				   NULL,
37533085 				   BYTES_TO_DWORDS(MCP_REG_SCRATCH),
3754
-				   MCP_REG_SCRATCH_SIZE_BB_K2,
3755
-				   false, 0, false, "MCP", false, 0);
3086
+				   MCP_REG_SCRATCH_SIZE,
3087
+				   false, 0, false, "MCP", 0);
37563088 
37573089 	/* Dump MCP cpu_reg_file */
37583090 	offset += qed_grc_dump_mem(p_hwfn,
....@@ -3762,19 +3094,19 @@
37623094 				   NULL,
37633095 				   BYTES_TO_DWORDS(MCP_REG_CPU_REG_FILE),
37643096 				   MCP_REG_CPU_REG_FILE_SIZE,
3765
-				   false, 0, false, "MCP", false, 0);
3097
+				   false, 0, false, "MCP", 0);
37663098 
37673099 	/* Dump MCP registers */
37683100 	block_enable[BLOCK_MCP] = true;
37693101 	offset += qed_grc_dump_registers(p_hwfn,
37703102 					 p_ptt,
37713103 					 dump_buf + offset,
3772
-					 dump, block_enable, "block", "MCP");
3104
+					 dump, block_enable, "MCP");
37733105 
37743106 	/* Dump required non-MCP registers */
37753107 	offset += qed_grc_dump_regs_hdr(dump_buf + offset,
37763108 					dump, 1, SPLIT_TYPE_NONE, 0,
3777
-					"block", "MCP");
3109
+					"MCP");
37783110 	addr = BYTES_TO_DWORDS(MISC_REG_SHARED_MEM_ADDR);
37793111 	offset += qed_grc_dump_reg_entry(p_hwfn,
37803112 					 p_ptt,
....@@ -3791,7 +3123,9 @@
37913123 	return offset;
37923124 }
37933125 
3794
-/* Dumps the tbus indirect memory for all PHYs. */
3126
+/* Dumps the tbus indirect memory for all PHYs.
3127
+ * Returns the dumped size in dwords.
3128
+ */
37953129 static u32 qed_grc_dump_phy(struct qed_hwfn *p_hwfn,
37963130 			    struct qed_ptt *p_ptt, u32 *dump_buf, bool dump)
37973131 {
....@@ -3825,7 +3159,7 @@
38253159 					       mem_name,
38263160 					       0,
38273161 					       PHY_DUMP_SIZE_DWORDS,
3828
-					       16, true, mem_name, false, 0);
3162
+					       16, true, mem_name, 0);
38293163 
38303164 		if (!dump) {
38313165 			offset += PHY_DUMP_SIZE_DWORDS;
....@@ -3856,21 +3190,58 @@
38563190 	return offset;
38573191 }
38583192 
3859
-static void qed_config_dbg_line(struct qed_hwfn *p_hwfn,
3860
-				struct qed_ptt *p_ptt,
3861
-				enum block_id block_id,
3862
-				u8 line_id,
3863
-				u8 enable_mask,
3864
-				u8 right_shift,
3865
-				u8 force_valid_mask, u8 force_frame_mask)
3866
-{
3867
-	struct block_defs *block = s_block_defs[block_id];
3193
+static enum dbg_status qed_find_nvram_image(struct qed_hwfn *p_hwfn,
3194
+					    struct qed_ptt *p_ptt,
3195
+					    u32 image_type,
3196
+					    u32 *nvram_offset_bytes,
3197
+					    u32 *nvram_size_bytes);
38683198 
3869
-	qed_wr(p_hwfn, p_ptt, block->dbg_select_addr, line_id);
3870
-	qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr, enable_mask);
3871
-	qed_wr(p_hwfn, p_ptt, block->dbg_shift_addr, right_shift);
3872
-	qed_wr(p_hwfn, p_ptt, block->dbg_force_valid_addr, force_valid_mask);
3873
-	qed_wr(p_hwfn, p_ptt, block->dbg_force_frame_addr, force_frame_mask);
3199
+static enum dbg_status qed_nvram_read(struct qed_hwfn *p_hwfn,
3200
+				      struct qed_ptt *p_ptt,
3201
+				      u32 nvram_offset_bytes,
3202
+				      u32 nvram_size_bytes, u32 *ret_buf);
3203
+
3204
+/* Dumps the MCP HW dump from NVRAM. Returns the dumped size in dwords. */
3205
+static u32 qed_grc_dump_mcp_hw_dump(struct qed_hwfn *p_hwfn,
3206
+				    struct qed_ptt *p_ptt,
3207
+				    u32 *dump_buf, bool dump)
3208
+{
3209
+	u32 hw_dump_offset_bytes = 0, hw_dump_size_bytes = 0;
3210
+	u32 hw_dump_size_dwords = 0, offset = 0;
3211
+	enum dbg_status status;
3212
+
3213
+	/* Read HW dump image from NVRAM */
3214
+	status = qed_find_nvram_image(p_hwfn,
3215
+				      p_ptt,
3216
+				      NVM_TYPE_HW_DUMP_OUT,
3217
+				      &hw_dump_offset_bytes,
3218
+				      &hw_dump_size_bytes);
3219
+	if (status != DBG_STATUS_OK)
3220
+		return 0;
3221
+
3222
+	hw_dump_size_dwords = BYTES_TO_DWORDS(hw_dump_size_bytes);
3223
+
3224
+	/* Dump HW dump image section */
3225
+	offset += qed_dump_section_hdr(dump_buf + offset,
3226
+				       dump, "mcp_hw_dump", 1);
3227
+	offset += qed_dump_num_param(dump_buf + offset,
3228
+				     dump, "size", hw_dump_size_dwords);
3229
+
3230
+	/* Read MCP HW dump image into dump buffer */
3231
+	if (dump && hw_dump_size_dwords) {
3232
+		status = qed_nvram_read(p_hwfn,
3233
+					p_ptt,
3234
+					hw_dump_offset_bytes,
3235
+					hw_dump_size_bytes, dump_buf + offset);
3236
+		if (status != DBG_STATUS_OK) {
3237
+			DP_NOTICE(p_hwfn,
3238
+				  "Failed to read MCP HW Dump image from NVRAM\n");
3239
+			return 0;
3240
+		}
3241
+	}
3242
+	offset += hw_dump_size_dwords;
3243
+
3244
+	return offset;
38743245 }
38753246 
38763247 /* Dumps Static Debug data. Returns the dumped size in dwords. */
....@@ -3879,26 +3250,19 @@
38793250 				     u32 *dump_buf, bool dump)
38803251 {
38813252 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
3882
-	u32 block_id, line_id, offset = 0;
3253
+	u32 block_id, line_id, offset = 0, addr, len;
38833254 
38843255 	/* Don't dump static debug if a debug bus recording is in progress */
38853256 	if (dump && qed_rd(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON))
38863257 		return 0;
38873258 
38883259 	if (dump) {
3889
-		/* Disable all blocks debug output */
3890
-		for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
3891
-			struct block_defs *block = s_block_defs[block_id];
3892
-
3893
-			if (block->dbg_client_id[dev_data->chip_id] !=
3894
-			    MAX_DBG_BUS_CLIENTS)
3895
-				qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr,
3896
-				       0);
3897
-		}
3260
+		/* Disable debug bus in all blocks */
3261
+		qed_bus_disable_blocks(p_hwfn, p_ptt);
38983262 
38993263 		qed_bus_reset_dbg_block(p_hwfn, p_ptt);
3900
-		qed_bus_set_framing_mode(p_hwfn,
3901
-					 p_ptt, DBG_BUS_FRAME_MODE_8HW_0ST);
3264
+		qed_wr(p_hwfn,
3265
+		       p_ptt, DBG_REG_FRAMING_MODE, DBG_BUS_FRAME_MODE_8HW);
39023266 		qed_wr(p_hwfn,
39033267 		       p_ptt, DBG_REG_DEBUG_TARGET, DBG_BUS_TARGET_ID_INT_BUF);
39043268 		qed_wr(p_hwfn, p_ptt, DBG_REG_FULL_MODE, 1);
....@@ -3907,28 +3271,48 @@
39073271 
39083272 	/* Dump all static debug lines for each relevant block */
39093273 	for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) {
3910
-		struct block_defs *block = s_block_defs[block_id];
3911
-		struct dbg_bus_block *block_desc;
3912
-		u32 block_dwords, addr, len;
3913
-		u8 dbg_client_id;
3274
+		const struct dbg_block_chip *block_per_chip;
3275
+		const struct dbg_block *block;
3276
+		bool is_removed, has_dbg_bus;
3277
+		u16 modes_buf_offset;
3278
+		u32 block_dwords;
39143279 
3915
-		if (block->dbg_client_id[dev_data->chip_id] ==
3916
-		    MAX_DBG_BUS_CLIENTS)
3280
+		block_per_chip =
3281
+		    qed_get_dbg_block_per_chip(p_hwfn, (enum block_id)block_id);
3282
+		is_removed = GET_FIELD(block_per_chip->flags,
3283
+				       DBG_BLOCK_CHIP_IS_REMOVED);
3284
+		has_dbg_bus = GET_FIELD(block_per_chip->flags,
3285
+					DBG_BLOCK_CHIP_HAS_DBG_BUS);
3286
+
3287
+		/* read+clear for NWS parity is not working, skip NWS block */
3288
+		if (block_id == BLOCK_NWS)
39173289 			continue;
39183290 
3919
-		block_desc = get_dbg_bus_block_desc(p_hwfn,
3920
-						    (enum block_id)block_id);
3921
-		block_dwords = NUM_DBG_LINES(block_desc) *
3291
+		if (!is_removed && has_dbg_bus &&
3292
+		    GET_FIELD(block_per_chip->dbg_bus_mode.data,
3293
+			      DBG_MODE_HDR_EVAL_MODE) > 0) {
3294
+			modes_buf_offset =
3295
+			    GET_FIELD(block_per_chip->dbg_bus_mode.data,
3296
+				      DBG_MODE_HDR_MODES_BUF_OFFSET);
3297
+			if (!qed_is_mode_match(p_hwfn, &modes_buf_offset))
3298
+				has_dbg_bus = false;
3299
+		}
3300
+
3301
+		if (is_removed || !has_dbg_bus)
3302
+			continue;
3303
+
3304
+		block_dwords = NUM_DBG_LINES(block_per_chip) *
39223305 			       STATIC_DEBUG_LINE_DWORDS;
39233306 
39243307 		/* Dump static section params */
3308
+		block = get_dbg_block(p_hwfn, (enum block_id)block_id);
39253309 		offset += qed_grc_dump_mem_hdr(p_hwfn,
39263310 					       dump_buf + offset,
39273311 					       dump,
39283312 					       block->name,
39293313 					       0,
39303314 					       block_dwords,
3931
-					       32, false, "STATIC", false, 0);
3315
+					       32, false, "STATIC", 0);
39323316 
39333317 		if (!dump) {
39343318 			offset += block_dwords;
....@@ -3944,20 +3328,19 @@
39443328 		}
39453329 
39463330 		/* Enable block's client */
3947
-		dbg_client_id = block->dbg_client_id[dev_data->chip_id];
39483331 		qed_bus_enable_clients(p_hwfn,
39493332 				       p_ptt,
3950
-				       BIT(dbg_client_id));
3333
+				       BIT(block_per_chip->dbg_client_id));
39513334 
39523335 		addr = BYTES_TO_DWORDS(DBG_REG_CALENDAR_OUT_DATA);
39533336 		len = STATIC_DEBUG_LINE_DWORDS;
3954
-		for (line_id = 0; line_id < (u32)NUM_DBG_LINES(block_desc);
3337
+		for (line_id = 0; line_id < (u32)NUM_DBG_LINES(block_per_chip);
39553338 		     line_id++) {
39563339 			/* Configure debug line ID */
3957
-			qed_config_dbg_line(p_hwfn,
3958
-					    p_ptt,
3959
-					    (enum block_id)block_id,
3960
-					    (u8)line_id, 0xf, 0, 0, 0);
3340
+			qed_bus_config_dbg_line(p_hwfn,
3341
+						p_ptt,
3342
+						(enum block_id)block_id,
3343
+						(u8)line_id, 0xf, 0, 0, 0);
39613344 
39623345 			/* Read debug line info */
39633346 			offset += qed_grc_dump_addr_range(p_hwfn,
....@@ -3972,7 +3355,8 @@
39723355 
39733356 		/* Disable block's client and debug output */
39743357 		qed_bus_enable_clients(p_hwfn, p_ptt, 0);
3975
-		qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr, 0);
3358
+		qed_bus_config_dbg_line(p_hwfn, p_ptt,
3359
+					(enum block_id)block_id, 0, 0, 0, 0, 0);
39763360 	}
39773361 
39783362 	if (dump) {
....@@ -3992,8 +3376,8 @@
39923376 				    bool dump, u32 *num_dumped_dwords)
39933377 {
39943378 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
3379
+	u32 dwords_read, offset = 0;
39953380 	bool parities_masked = false;
3996
-	u32 offset = 0;
39973381 	u8 i;
39983382 
39993383 	*num_dumped_dwords = 0;
....@@ -4012,13 +3396,11 @@
40123396 	offset += qed_dump_num_param(dump_buf + offset,
40133397 				     dump,
40143398 				     "num-lcids",
4015
-				     qed_grc_get_param(p_hwfn,
4016
-						DBG_GRC_PARAM_NUM_LCIDS));
3399
+				     NUM_OF_LCIDS);
40173400 	offset += qed_dump_num_param(dump_buf + offset,
40183401 				     dump,
40193402 				     "num-ltids",
4020
-				     qed_grc_get_param(p_hwfn,
4021
-						DBG_GRC_PARAM_NUM_LTIDS));
3403
+				     NUM_OF_LTIDS);
40223404 	offset += qed_dump_num_param(dump_buf + offset,
40233405 				     dump, "num-ports", dev_data->num_ports);
40243406 
....@@ -4030,7 +3412,7 @@
40303412 
40313413 	/* Take all blocks out of reset (using reset registers) */
40323414 	if (dump) {
4033
-		qed_grc_unreset_blocks(p_hwfn, p_ptt);
3415
+		qed_grc_unreset_blocks(p_hwfn, p_ptt, false);
40343416 		qed_update_blocks_reset_state(p_hwfn, p_ptt);
40353417 	}
40363418 
....@@ -4073,7 +3455,7 @@
40733455 						 dump_buf +
40743456 						 offset,
40753457 						 dump,
4076
-						 block_enable, NULL, NULL);
3458
+						 block_enable, NULL);
40773459 
40783460 		/* Dump special registers */
40793461 		offset += qed_grc_dump_special_regs(p_hwfn,
....@@ -4107,22 +3489,28 @@
41073489 						       dump_buf + offset,
41083490 						       dump, i);
41093491 
4110
-	/* Dump IORs */
4111
-	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IOR))
4112
-		offset += qed_grc_dump_iors(p_hwfn,
4113
-					    p_ptt, dump_buf + offset, dump);
4114
-
41153492 	/* Dump VFC */
4116
-	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_VFC))
4117
-		offset += qed_grc_dump_vfc(p_hwfn,
4118
-					   p_ptt, dump_buf + offset, dump);
3493
+	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_VFC)) {
3494
+		dwords_read = qed_grc_dump_vfc(p_hwfn,
3495
+					       p_ptt, dump_buf + offset, dump);
3496
+		offset += dwords_read;
3497
+		if (!dwords_read)
3498
+			return DBG_STATUS_VFC_READ_ERROR;
3499
+	}
41193500 
41203501 	/* Dump PHY tbus */
41213502 	if (qed_grc_is_included(p_hwfn,
41223503 				DBG_GRC_PARAM_DUMP_PHY) && dev_data->chip_id ==
4123
-	    CHIP_K2 && dev_data->platform_id == PLATFORM_ASIC)
3504
+	    CHIP_K2 && dev_data->hw_type == HW_TYPE_ASIC)
41243505 		offset += qed_grc_dump_phy(p_hwfn,
41253506 					   p_ptt, dump_buf + offset, dump);
3507
+
3508
+	/* Dump MCP HW Dump */
3509
+	if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_MCP_HW_DUMP) &&
3510
+	    !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP) && 1)
3511
+		offset += qed_grc_dump_mcp_hw_dump(p_hwfn,
3512
+						   p_ptt,
3513
+						   dump_buf + offset, dump);
41263514 
41273515 	/* Dump static debug data (only if not during debug bus recording) */
41283516 	if (qed_grc_is_included(p_hwfn,
....@@ -4174,8 +3562,9 @@
41743562 	u8 reg_id;
41753563 
41763564 	hdr = (struct dbg_idle_chk_result_hdr *)dump_buf;
4177
-	regs = &((const union dbg_idle_chk_reg *)
4178
-		 s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr)[rule->reg_offset];
3565
+	regs = (const union dbg_idle_chk_reg *)
3566
+		p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr +
3567
+		rule->reg_offset;
41793568 	cond_regs = &regs[0].cond_reg;
41803569 	info_regs = &regs[rule->num_cond_regs].info_reg;
41813570 
....@@ -4195,8 +3584,8 @@
41953584 		const struct dbg_idle_chk_cond_reg *reg = &cond_regs[reg_id];
41963585 		struct dbg_idle_chk_result_reg_hdr *reg_hdr;
41973586 
4198
-		reg_hdr = (struct dbg_idle_chk_result_reg_hdr *)
4199
-			  (dump_buf + offset);
3587
+		reg_hdr =
3588
+		    (struct dbg_idle_chk_result_reg_hdr *)(dump_buf + offset);
42003589 
42013590 		/* Write register header */
42023591 		if (!dump) {
....@@ -4313,12 +3702,13 @@
43133702 		const u32 *imm_values;
43143703 
43153704 		rule = &input_rules[i];
4316
-		regs = &((const union dbg_idle_chk_reg *)
4317
-			 s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr)
4318
-			[rule->reg_offset];
3705
+		regs = (const union dbg_idle_chk_reg *)
3706
+			p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr +
3707
+			rule->reg_offset;
43193708 		cond_regs = &regs[0].cond_reg;
4320
-		imm_values = &s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr
4321
-			     [rule->imm_offset];
3709
+		imm_values =
3710
+		    (u32 *)p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr +
3711
+		    rule->imm_offset;
43223712 
43233713 		/* Check if all condition register blocks are out of reset, and
43243714 		 * find maximal number of entries (all condition registers that
....@@ -4436,10 +3826,12 @@
44363826 static u32 qed_idle_chk_dump(struct qed_hwfn *p_hwfn,
44373827 			     struct qed_ptt *p_ptt, u32 *dump_buf, bool dump)
44383828 {
4439
-	u32 num_failing_rules_offset, offset = 0, input_offset = 0;
4440
-	u32 num_failing_rules = 0;
3829
+	struct virt_mem_desc *dbg_buf =
3830
+	    &p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES];
3831
+	u32 num_failing_rules_offset, offset = 0,
3832
+	    input_offset = 0, num_failing_rules = 0;
44413833 
4442
-	/* Dump global params */
3834
+	/* Dump global params  - 1 must match below amount of params */
44433835 	offset += qed_dump_common_global_params(p_hwfn,
44443836 						p_ptt,
44453837 						dump_buf + offset, dump, 1);
....@@ -4451,12 +3843,10 @@
44513843 	num_failing_rules_offset = offset;
44523844 	offset += qed_dump_num_param(dump_buf + offset, dump, "num_rules", 0);
44533845 
4454
-	while (input_offset <
4455
-	       s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].size_in_dwords) {
3846
+	while (input_offset < BYTES_TO_DWORDS(dbg_buf->size)) {
44563847 		const struct dbg_idle_chk_cond_hdr *cond_hdr =
4457
-			(const struct dbg_idle_chk_cond_hdr *)
4458
-			&s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].ptr
4459
-			[input_offset++];
3848
+		    (const struct dbg_idle_chk_cond_hdr *)dbg_buf->ptr +
3849
+		    input_offset++;
44603850 		bool eval_mode, mode_match = true;
44613851 		u32 curr_failing_rules;
44623852 		u16 modes_buf_offset;
....@@ -4473,16 +3863,21 @@
44733863 		}
44743864 
44753865 		if (mode_match) {
3866
+			const struct dbg_idle_chk_rule *rule =
3867
+			    (const struct dbg_idle_chk_rule *)((u32 *)
3868
+							       dbg_buf->ptr
3869
+							       + input_offset);
3870
+			u32 num_input_rules =
3871
+				cond_hdr->data_size / IDLE_CHK_RULE_SIZE_DWORDS;
44763872 			offset +=
44773873 			    qed_idle_chk_dump_rule_entries(p_hwfn,
4478
-				p_ptt,
4479
-				dump_buf + offset,
4480
-				dump,
4481
-				(const struct dbg_idle_chk_rule *)
4482
-				&s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].
4483
-				ptr[input_offset],
4484
-				cond_hdr->data_size / IDLE_CHK_RULE_SIZE_DWORDS,
4485
-				&curr_failing_rules);
3874
+							   p_ptt,
3875
+							   dump_buf +
3876
+							   offset,
3877
+							   dump,
3878
+							   rule,
3879
+							   num_input_rules,
3880
+							   &curr_failing_rules);
44863881 			num_failing_rules += curr_failing_rules;
44873882 		}
44883883 
....@@ -4549,7 +3944,7 @@
45493944 {
45503945 	u32 ret_mcp_resp, ret_mcp_param, ret_read_size, bytes_to_copy;
45513946 	s32 bytes_left = nvram_size_bytes;
4552
-	u32 read_offset = 0;
3947
+	u32 read_offset = 0, param = 0;
45533948 
45543949 	DP_VERBOSE(p_hwfn,
45553950 		   QED_MSG_DEBUG,
....@@ -4562,14 +3957,14 @@
45623957 		     MCP_DRV_NVM_BUF_LEN) ? MCP_DRV_NVM_BUF_LEN : bytes_left;
45633958 
45643959 		/* Call NVRAM read command */
3960
+		SET_MFW_FIELD(param,
3961
+			      DRV_MB_PARAM_NVM_OFFSET,
3962
+			      nvram_offset_bytes + read_offset);
3963
+		SET_MFW_FIELD(param, DRV_MB_PARAM_NVM_LEN, bytes_to_copy);
45653964 		if (qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
4566
-				       DRV_MSG_CODE_NVM_READ_NVRAM,
4567
-				       (nvram_offset_bytes +
4568
-					read_offset) |
4569
-				       (bytes_to_copy <<
4570
-					DRV_MB_PARAM_NVM_LEN_OFFSET),
4571
-				       &ret_mcp_resp, &ret_mcp_param,
4572
-				       &ret_read_size,
3965
+				       DRV_MSG_CODE_NVM_READ_NVRAM, param,
3966
+				       &ret_mcp_resp,
3967
+				       &ret_mcp_param, &ret_read_size,
45733968 				       (u32 *)((u8 *)ret_buf + read_offset)))
45743969 			return DBG_STATUS_NVRAM_READ_FAILED;
45753970 
....@@ -4707,12 +4102,12 @@
47074102 	u32 trace_meta_size_dwords = 0, running_bundle_id, offset = 0;
47084103 	u32 trace_meta_offset_bytes = 0, trace_meta_size_bytes = 0;
47094104 	enum dbg_status status;
4710
-	bool mcp_access;
47114105 	int halted = 0;
4106
+	bool use_mfw;
47124107 
47134108 	*num_dumped_dwords = 0;
47144109 
4715
-	mcp_access = !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP);
4110
+	use_mfw = !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP);
47164111 
47174112 	/* Get trace data info */
47184113 	status = qed_mcp_trace_get_data_info(p_hwfn,
....@@ -4733,7 +4128,7 @@
47334128 	 * consistent. if halt fails, MCP trace is taken anyway, with a small
47344129 	 * risk that it may be corrupt.
47354130 	 */
4736
-	if (dump && mcp_access) {
4131
+	if (dump && use_mfw) {
47374132 		halted = !qed_mcp_halt(p_hwfn, p_ptt);
47384133 		if (!halted)
47394134 			DP_NOTICE(p_hwfn, "MCP halt failed!\n");
....@@ -4773,17 +4168,15 @@
47734168 	 */
47744169 	trace_meta_size_bytes =
47754170 		qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_MCP_TRACE_META_SIZE);
4776
-	if ((!trace_meta_size_bytes || dump) && mcp_access) {
4171
+	if ((!trace_meta_size_bytes || dump) && use_mfw)
47774172 		status = qed_mcp_trace_get_meta_info(p_hwfn,
47784173 						     p_ptt,
47794174 						     trace_data_size_bytes,
47804175 						     &running_bundle_id,
47814176 						     &trace_meta_offset_bytes,
47824177 						     &trace_meta_size_bytes);
4783
-		if (status == DBG_STATUS_OK)
4784
-			trace_meta_size_dwords =
4785
-				BYTES_TO_DWORDS(trace_meta_size_bytes);
4786
-	}
4178
+	if (status == DBG_STATUS_OK)
4179
+		trace_meta_size_dwords = BYTES_TO_DWORDS(trace_meta_size_bytes);
47874180 
47884181 	/* Dump trace meta size param */
47894182 	offset += qed_dump_num_param(dump_buf + offset,
....@@ -4807,7 +4200,7 @@
48074200 	/* If no mcp access, indicate that the dump doesn't contain the meta
48084201 	 * data from NVRAM.
48094202 	 */
4810
-	return mcp_access ? status : DBG_STATUS_NVRAM_GET_IMAGE_FAILED;
4203
+	return use_mfw ? status : DBG_STATUS_NVRAM_GET_IMAGE_FAILED;
48114204 }
48124205 
48134206 /* Dump GRC FIFO */
....@@ -4985,16 +4378,18 @@
49854378 	override_window_dwords =
49864379 		qed_rd(p_hwfn, p_ptt, GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW) *
49874380 		PROTECTION_OVERRIDE_ELEMENT_DWORDS;
4988
-	addr = BYTES_TO_DWORDS(GRC_REG_PROTECTION_OVERRIDE_WINDOW);
4989
-	offset += qed_grc_dump_addr_range(p_hwfn,
4990
-					  p_ptt,
4991
-					  dump_buf + offset,
4992
-					  true,
4993
-					  addr,
4994
-					  override_window_dwords,
4995
-					  true, SPLIT_TYPE_NONE, 0);
4996
-	qed_dump_num_param(dump_buf + size_param_offset, dump, "size",
4997
-			   override_window_dwords);
4381
+	if (override_window_dwords) {
4382
+		addr = BYTES_TO_DWORDS(GRC_REG_PROTECTION_OVERRIDE_WINDOW);
4383
+		offset += qed_grc_dump_addr_range(p_hwfn,
4384
+						  p_ptt,
4385
+						  dump_buf + offset,
4386
+						  true,
4387
+						  addr,
4388
+						  override_window_dwords,
4389
+						  true, SPLIT_TYPE_NONE, 0);
4390
+		qed_dump_num_param(dump_buf + size_param_offset, dump, "size",
4391
+				   override_window_dwords);
4392
+	}
49984393 out:
49994394 	/* Dump last section */
50004395 	offset += qed_dump_last_section(dump_buf, offset, dump);
....@@ -5030,7 +4425,7 @@
50304425 		struct storm_defs *storm = &s_storm_defs[storm_id];
50314426 		u32 last_list_idx, addr;
50324427 
5033
-		if (dev_data->block_in_reset[storm->block_id])
4428
+		if (dev_data->block_in_reset[storm->sem_block_id])
50344429 			continue;
50354430 
50364431 		/* Read FW info for the current Storm */
....@@ -5055,9 +4450,11 @@
50554450 			continue;
50564451 		}
50574452 
4453
+		addr = le16_to_cpu(asserts->section_ram_line_offset);
50584454 		fw_asserts_section_addr = storm->sem_fast_mem_addr +
5059
-			SEM_FAST_REG_INT_RAM +
5060
-			RAM_LINES_TO_BYTES(asserts->section_ram_line_offset);
4455
+					  SEM_FAST_REG_INT_RAM +
4456
+					  RAM_LINES_TO_BYTES(addr);
4457
+
50614458 		next_list_idx_addr = fw_asserts_section_addr +
50624459 			DWORDS_TO_BYTES(asserts->list_next_index_dword_offset);
50634460 		next_list_idx = qed_rd(p_hwfn, p_ptt, next_list_idx_addr);
....@@ -5081,20 +4478,362 @@
50814478 	return offset;
50824479 }
50834480 
4481
+/* Dumps the specified ILT pages to the specified buffer.
4482
+ * Returns the dumped size in dwords.
4483
+ */
4484
+static u32 qed_ilt_dump_pages_range(u32 *dump_buf,
4485
+				    bool dump,
4486
+				    u32 start_page_id,
4487
+				    u32 num_pages,
4488
+				    struct phys_mem_desc *ilt_pages,
4489
+				    bool dump_page_ids)
4490
+{
4491
+	u32 page_id, end_page_id, offset = 0;
4492
+
4493
+	if (num_pages == 0)
4494
+		return offset;
4495
+
4496
+	end_page_id = start_page_id + num_pages - 1;
4497
+
4498
+	for (page_id = start_page_id; page_id <= end_page_id; page_id++) {
4499
+		struct phys_mem_desc *mem_desc = &ilt_pages[page_id];
4500
+
4501
+		/**
4502
+		 *
4503
+		 * if (page_id >= ->p_cxt_mngr->ilt_shadow_size)
4504
+		 *     break;
4505
+		 */
4506
+
4507
+		if (!ilt_pages[page_id].virt_addr)
4508
+			continue;
4509
+
4510
+		if (dump_page_ids) {
4511
+			/* Copy page ID to dump buffer */
4512
+			if (dump)
4513
+				*(dump_buf + offset) = page_id;
4514
+			offset++;
4515
+		} else {
4516
+			/* Copy page memory to dump buffer */
4517
+			if (dump)
4518
+				memcpy(dump_buf + offset,
4519
+				       mem_desc->virt_addr, mem_desc->size);
4520
+			offset += BYTES_TO_DWORDS(mem_desc->size);
4521
+		}
4522
+	}
4523
+
4524
+	return offset;
4525
+}
4526
+
4527
+/* Dumps a section containing the dumped ILT pages.
4528
+ * Returns the dumped size in dwords.
4529
+ */
4530
+static u32 qed_ilt_dump_pages_section(struct qed_hwfn *p_hwfn,
4531
+				      u32 *dump_buf,
4532
+				      bool dump,
4533
+				      u32 valid_conn_pf_pages,
4534
+				      u32 valid_conn_vf_pages,
4535
+				      struct phys_mem_desc *ilt_pages,
4536
+				      bool dump_page_ids)
4537
+{
4538
+	struct qed_ilt_client_cfg *clients = p_hwfn->p_cxt_mngr->clients;
4539
+	u32 pf_start_line, start_page_id, offset = 0;
4540
+	u32 cdut_pf_init_pages, cdut_vf_init_pages;
4541
+	u32 cdut_pf_work_pages, cdut_vf_work_pages;
4542
+	u32 base_data_offset, size_param_offset;
4543
+	u32 cdut_pf_pages, cdut_vf_pages;
4544
+	const char *section_name;
4545
+	u8 i;
4546
+
4547
+	section_name = dump_page_ids ? "ilt_page_ids" : "ilt_page_mem";
4548
+	cdut_pf_init_pages = qed_get_cdut_num_pf_init_pages(p_hwfn);
4549
+	cdut_vf_init_pages = qed_get_cdut_num_vf_init_pages(p_hwfn);
4550
+	cdut_pf_work_pages = qed_get_cdut_num_pf_work_pages(p_hwfn);
4551
+	cdut_vf_work_pages = qed_get_cdut_num_vf_work_pages(p_hwfn);
4552
+	cdut_pf_pages = cdut_pf_init_pages + cdut_pf_work_pages;
4553
+	cdut_vf_pages = cdut_vf_init_pages + cdut_vf_work_pages;
4554
+	pf_start_line = p_hwfn->p_cxt_mngr->pf_start_line;
4555
+
4556
+	offset +=
4557
+	    qed_dump_section_hdr(dump_buf + offset, dump, section_name, 1);
4558
+
4559
+	/* Dump size parameter (0 for now, overwritten with real size later) */
4560
+	size_param_offset = offset;
4561
+	offset += qed_dump_num_param(dump_buf + offset, dump, "size", 0);
4562
+	base_data_offset = offset;
4563
+
4564
+	/* CDUC pages are ordered as follows:
4565
+	 * - PF pages - valid section (included in PF connection type mapping)
4566
+	 * - PF pages - invalid section (not dumped)
4567
+	 * - For each VF in the PF:
4568
+	 *   - VF pages - valid section (included in VF connection type mapping)
4569
+	 *   - VF pages - invalid section (not dumped)
4570
+	 */
4571
+	if (qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_DUMP_ILT_CDUC)) {
4572
+		/* Dump connection PF pages */
4573
+		start_page_id = clients[ILT_CLI_CDUC].first.val - pf_start_line;
4574
+		offset += qed_ilt_dump_pages_range(dump_buf + offset,
4575
+						   dump,
4576
+						   start_page_id,
4577
+						   valid_conn_pf_pages,
4578
+						   ilt_pages, dump_page_ids);
4579
+
4580
+		/* Dump connection VF pages */
4581
+		start_page_id += clients[ILT_CLI_CDUC].pf_total_lines;
4582
+		for (i = 0; i < p_hwfn->p_cxt_mngr->vf_count;
4583
+		     i++, start_page_id += clients[ILT_CLI_CDUC].vf_total_lines)
4584
+			offset += qed_ilt_dump_pages_range(dump_buf + offset,
4585
+							   dump,
4586
+							   start_page_id,
4587
+							   valid_conn_vf_pages,
4588
+							   ilt_pages,
4589
+							   dump_page_ids);
4590
+	}
4591
+
4592
+	/* CDUT pages are ordered as follows:
4593
+	 * - PF init pages (not dumped)
4594
+	 * - PF work pages
4595
+	 * - For each VF in the PF:
4596
+	 *   - VF init pages (not dumped)
4597
+	 *   - VF work pages
4598
+	 */
4599
+	if (qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_DUMP_ILT_CDUT)) {
4600
+		/* Dump task PF pages */
4601
+		start_page_id = clients[ILT_CLI_CDUT].first.val +
4602
+		    cdut_pf_init_pages - pf_start_line;
4603
+		offset += qed_ilt_dump_pages_range(dump_buf + offset,
4604
+						   dump,
4605
+						   start_page_id,
4606
+						   cdut_pf_work_pages,
4607
+						   ilt_pages, dump_page_ids);
4608
+
4609
+		/* Dump task VF pages */
4610
+		start_page_id = clients[ILT_CLI_CDUT].first.val +
4611
+		    cdut_pf_pages + cdut_vf_init_pages - pf_start_line;
4612
+		for (i = 0; i < p_hwfn->p_cxt_mngr->vf_count;
4613
+		     i++, start_page_id += cdut_vf_pages)
4614
+			offset += qed_ilt_dump_pages_range(dump_buf + offset,
4615
+							   dump,
4616
+							   start_page_id,
4617
+							   cdut_vf_work_pages,
4618
+							   ilt_pages,
4619
+							   dump_page_ids);
4620
+	}
4621
+
4622
+	/* Overwrite size param */
4623
+	if (dump)
4624
+		qed_dump_num_param(dump_buf + size_param_offset,
4625
+				   dump, "size", offset - base_data_offset);
4626
+
4627
+	return offset;
4628
+}
4629
+
4630
+/* Performs ILT Dump to the specified buffer.
4631
+ * Returns the dumped size in dwords.
4632
+ */
4633
+static u32 qed_ilt_dump(struct qed_hwfn *p_hwfn,
4634
+			struct qed_ptt *p_ptt, u32 *dump_buf, bool dump)
4635
+{
4636
+	struct qed_ilt_client_cfg *clients = p_hwfn->p_cxt_mngr->clients;
4637
+	u32 valid_conn_vf_cids, valid_conn_vf_pages, offset = 0;
4638
+	u32 valid_conn_pf_cids, valid_conn_pf_pages, num_pages;
4639
+	u32 num_cids_per_page, conn_ctx_size;
4640
+	u32 cduc_page_size, cdut_page_size;
4641
+	struct phys_mem_desc *ilt_pages;
4642
+	u8 conn_type;
4643
+
4644
+	cduc_page_size = 1 <<
4645
+	    (clients[ILT_CLI_CDUC].p_size.val + PXP_ILT_PAGE_SIZE_NUM_BITS_MIN);
4646
+	cdut_page_size = 1 <<
4647
+	    (clients[ILT_CLI_CDUT].p_size.val + PXP_ILT_PAGE_SIZE_NUM_BITS_MIN);
4648
+	conn_ctx_size = p_hwfn->p_cxt_mngr->conn_ctx_size;
4649
+	num_cids_per_page = (int)(cduc_page_size / conn_ctx_size);
4650
+	ilt_pages = p_hwfn->p_cxt_mngr->ilt_shadow;
4651
+
4652
+	/* Dump global params - 22 must match number of params below */
4653
+	offset += qed_dump_common_global_params(p_hwfn, p_ptt,
4654
+						dump_buf + offset, dump, 22);
4655
+	offset += qed_dump_str_param(dump_buf + offset,
4656
+				     dump, "dump-type", "ilt-dump");
4657
+	offset += qed_dump_num_param(dump_buf + offset,
4658
+				     dump,
4659
+				     "cduc-page-size", cduc_page_size);
4660
+	offset += qed_dump_num_param(dump_buf + offset,
4661
+				     dump,
4662
+				     "cduc-first-page-id",
4663
+				     clients[ILT_CLI_CDUC].first.val);
4664
+	offset += qed_dump_num_param(dump_buf + offset,
4665
+				     dump,
4666
+				     "cduc-last-page-id",
4667
+				     clients[ILT_CLI_CDUC].last.val);
4668
+	offset += qed_dump_num_param(dump_buf + offset,
4669
+				     dump,
4670
+				     "cduc-num-pf-pages",
4671
+				     clients
4672
+				     [ILT_CLI_CDUC].pf_total_lines);
4673
+	offset += qed_dump_num_param(dump_buf + offset,
4674
+				     dump,
4675
+				     "cduc-num-vf-pages",
4676
+				     clients
4677
+				     [ILT_CLI_CDUC].vf_total_lines);
4678
+	offset += qed_dump_num_param(dump_buf + offset,
4679
+				     dump,
4680
+				     "max-conn-ctx-size",
4681
+				     conn_ctx_size);
4682
+	offset += qed_dump_num_param(dump_buf + offset,
4683
+				     dump,
4684
+				     "cdut-page-size", cdut_page_size);
4685
+	offset += qed_dump_num_param(dump_buf + offset,
4686
+				     dump,
4687
+				     "cdut-first-page-id",
4688
+				     clients[ILT_CLI_CDUT].first.val);
4689
+	offset += qed_dump_num_param(dump_buf + offset,
4690
+				     dump,
4691
+				     "cdut-last-page-id",
4692
+				     clients[ILT_CLI_CDUT].last.val);
4693
+	offset += qed_dump_num_param(dump_buf + offset,
4694
+				     dump,
4695
+				     "cdut-num-pf-init-pages",
4696
+				     qed_get_cdut_num_pf_init_pages(p_hwfn));
4697
+	offset += qed_dump_num_param(dump_buf + offset,
4698
+				     dump,
4699
+				     "cdut-num-vf-init-pages",
4700
+				     qed_get_cdut_num_vf_init_pages(p_hwfn));
4701
+	offset += qed_dump_num_param(dump_buf + offset,
4702
+				     dump,
4703
+				     "cdut-num-pf-work-pages",
4704
+				     qed_get_cdut_num_pf_work_pages(p_hwfn));
4705
+	offset += qed_dump_num_param(dump_buf + offset,
4706
+				     dump,
4707
+				     "cdut-num-vf-work-pages",
4708
+				     qed_get_cdut_num_vf_work_pages(p_hwfn));
4709
+	offset += qed_dump_num_param(dump_buf + offset,
4710
+				     dump,
4711
+				     "max-task-ctx-size",
4712
+				     p_hwfn->p_cxt_mngr->task_ctx_size);
4713
+	offset += qed_dump_num_param(dump_buf + offset,
4714
+				     dump,
4715
+				     "task-type-id",
4716
+				     p_hwfn->p_cxt_mngr->task_type_id);
4717
+	offset += qed_dump_num_param(dump_buf + offset,
4718
+				     dump,
4719
+				     "first-vf-id-in-pf",
4720
+				     p_hwfn->p_cxt_mngr->first_vf_in_pf);
4721
+	offset += /* 18 */ qed_dump_num_param(dump_buf + offset,
4722
+					      dump,
4723
+					      "num-vfs-in-pf",
4724
+					      p_hwfn->p_cxt_mngr->vf_count);
4725
+	offset += qed_dump_num_param(dump_buf + offset,
4726
+				     dump,
4727
+				     "ptr-size-bytes", sizeof(void *));
4728
+	offset += qed_dump_num_param(dump_buf + offset,
4729
+				     dump,
4730
+				     "pf-start-line",
4731
+				     p_hwfn->p_cxt_mngr->pf_start_line);
4732
+	offset += qed_dump_num_param(dump_buf + offset,
4733
+				     dump,
4734
+				     "page-mem-desc-size-dwords",
4735
+				     PAGE_MEM_DESC_SIZE_DWORDS);
4736
+	offset += qed_dump_num_param(dump_buf + offset,
4737
+				     dump,
4738
+				     "ilt-shadow-size",
4739
+				     p_hwfn->p_cxt_mngr->ilt_shadow_size);
4740
+	/* Additional/Less parameters require matching of number in call to
4741
+	 * dump_common_global_params()
4742
+	 */
4743
+
4744
+	/* Dump section containing number of PF CIDs per connection type */
4745
+	offset += qed_dump_section_hdr(dump_buf + offset,
4746
+				       dump, "num_pf_cids_per_conn_type", 1);
4747
+	offset += qed_dump_num_param(dump_buf + offset,
4748
+				     dump, "size", NUM_OF_CONNECTION_TYPES_E4);
4749
+	for (conn_type = 0, valid_conn_pf_cids = 0;
4750
+	     conn_type < NUM_OF_CONNECTION_TYPES_E4; conn_type++, offset++) {
4751
+		u32 num_pf_cids =
4752
+		    p_hwfn->p_cxt_mngr->conn_cfg[conn_type].cid_count;
4753
+
4754
+		if (dump)
4755
+			*(dump_buf + offset) = num_pf_cids;
4756
+		valid_conn_pf_cids += num_pf_cids;
4757
+	}
4758
+
4759
+	/* Dump section containing number of VF CIDs per connection type */
4760
+	offset += qed_dump_section_hdr(dump_buf + offset,
4761
+				       dump, "num_vf_cids_per_conn_type", 1);
4762
+	offset += qed_dump_num_param(dump_buf + offset,
4763
+				     dump, "size", NUM_OF_CONNECTION_TYPES_E4);
4764
+	for (conn_type = 0, valid_conn_vf_cids = 0;
4765
+	     conn_type < NUM_OF_CONNECTION_TYPES_E4; conn_type++, offset++) {
4766
+		u32 num_vf_cids =
4767
+		    p_hwfn->p_cxt_mngr->conn_cfg[conn_type].cids_per_vf;
4768
+
4769
+		if (dump)
4770
+			*(dump_buf + offset) = num_vf_cids;
4771
+		valid_conn_vf_cids += num_vf_cids;
4772
+	}
4773
+
4774
+	/* Dump section containing physical memory descs for each ILT page */
4775
+	num_pages = p_hwfn->p_cxt_mngr->ilt_shadow_size;
4776
+	offset += qed_dump_section_hdr(dump_buf + offset,
4777
+				       dump, "ilt_page_desc", 1);
4778
+	offset += qed_dump_num_param(dump_buf + offset,
4779
+				     dump,
4780
+				     "size",
4781
+				     num_pages * PAGE_MEM_DESC_SIZE_DWORDS);
4782
+
4783
+	/* Copy memory descriptors to dump buffer */
4784
+	if (dump) {
4785
+		u32 page_id;
4786
+
4787
+		for (page_id = 0; page_id < num_pages;
4788
+		     page_id++, offset += PAGE_MEM_DESC_SIZE_DWORDS)
4789
+			memcpy(dump_buf + offset,
4790
+			       &ilt_pages[page_id],
4791
+			       DWORDS_TO_BYTES(PAGE_MEM_DESC_SIZE_DWORDS));
4792
+	} else {
4793
+		offset += num_pages * PAGE_MEM_DESC_SIZE_DWORDS;
4794
+	}
4795
+
4796
+	valid_conn_pf_pages = DIV_ROUND_UP(valid_conn_pf_cids,
4797
+					   num_cids_per_page);
4798
+	valid_conn_vf_pages = DIV_ROUND_UP(valid_conn_vf_cids,
4799
+					   num_cids_per_page);
4800
+
4801
+	/* Dump ILT pages IDs */
4802
+	offset += qed_ilt_dump_pages_section(p_hwfn,
4803
+					     dump_buf + offset,
4804
+					     dump,
4805
+					     valid_conn_pf_pages,
4806
+					     valid_conn_vf_pages,
4807
+					     ilt_pages, true);
4808
+
4809
+	/* Dump ILT pages memory */
4810
+	offset += qed_ilt_dump_pages_section(p_hwfn,
4811
+					     dump_buf + offset,
4812
+					     dump,
4813
+					     valid_conn_pf_pages,
4814
+					     valid_conn_vf_pages,
4815
+					     ilt_pages, false);
4816
+
4817
+	/* Dump last section */
4818
+	offset += qed_dump_last_section(dump_buf, offset, dump);
4819
+
4820
+	return offset;
4821
+}
4822
+
50844823 /***************************** Public Functions *******************************/
50854824 
5086
-enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr)
4825
+enum dbg_status qed_dbg_set_bin_ptr(struct qed_hwfn *p_hwfn,
4826
+				    const u8 * const bin_ptr)
50874827 {
5088
-	struct bin_buffer_hdr *buf_array = (struct bin_buffer_hdr *)bin_ptr;
4828
+	struct bin_buffer_hdr *buf_hdrs = (struct bin_buffer_hdr *)bin_ptr;
50894829 	u8 buf_id;
50904830 
5091
-	/* convert binary data to debug arrays */
5092
-	for (buf_id = 0; buf_id < MAX_BIN_DBG_BUFFER_TYPE; buf_id++) {
5093
-		s_dbg_arrays[buf_id].ptr =
5094
-		    (u32 *)(bin_ptr + buf_array[buf_id].offset);
5095
-		s_dbg_arrays[buf_id].size_in_dwords =
5096
-		    BYTES_TO_DWORDS(buf_array[buf_id].length);
5097
-	}
4831
+	/* Convert binary data to debug arrays */
4832
+	for (buf_id = 0; buf_id < MAX_BIN_DBG_BUFFER_TYPE; buf_id++)
4833
+		qed_set_dbg_bin_buf(p_hwfn,
4834
+				    buf_id,
4835
+				    (u32 *)(bin_ptr + buf_hdrs[buf_id].offset),
4836
+				    buf_hdrs[buf_id].length);
50984837 
50994838 	return DBG_STATUS_OK;
51004839 }
....@@ -5109,7 +4848,7 @@
51094848 		struct storm_defs *storm = &s_storm_defs[storm_id];
51104849 
51114850 		/* Skip Storm if it's in reset */
5112
-		if (dev_data->block_in_reset[storm->block_id])
4851
+		if (dev_data->block_in_reset[storm->sem_block_id])
51134852 			continue;
51144853 
51154854 		/* Read FW info for the current Storm */
....@@ -5119,6 +4858,69 @@
51194858 	}
51204859 
51214860 	return false;
4861
+}
4862
+
4863
+enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn,
4864
+				   enum dbg_grc_params grc_param, u32 val)
4865
+{
4866
+	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
4867
+	enum dbg_status status;
4868
+	int i;
4869
+
4870
+	DP_VERBOSE(p_hwfn,
4871
+		   QED_MSG_DEBUG,
4872
+		   "dbg_grc_config: paramId = %d, val = %d\n", grc_param, val);
4873
+
4874
+	status = qed_dbg_dev_init(p_hwfn);
4875
+	if (status != DBG_STATUS_OK)
4876
+		return status;
4877
+
4878
+	/* Initializes the GRC parameters (if not initialized). Needed in order
4879
+	 * to set the default parameter values for the first time.
4880
+	 */
4881
+	qed_dbg_grc_init_params(p_hwfn);
4882
+
4883
+	if (grc_param >= MAX_DBG_GRC_PARAMS)
4884
+		return DBG_STATUS_INVALID_ARGS;
4885
+	if (val < s_grc_param_defs[grc_param].min ||
4886
+	    val > s_grc_param_defs[grc_param].max)
4887
+		return DBG_STATUS_INVALID_ARGS;
4888
+
4889
+	if (s_grc_param_defs[grc_param].is_preset) {
4890
+		/* Preset param */
4891
+
4892
+		/* Disabling a preset is not allowed. Call
4893
+		 * dbg_grc_set_params_default instead.
4894
+		 */
4895
+		if (!val)
4896
+			return DBG_STATUS_INVALID_ARGS;
4897
+
4898
+		/* Update all params with the preset values */
4899
+		for (i = 0; i < MAX_DBG_GRC_PARAMS; i++) {
4900
+			struct grc_param_defs *defs = &s_grc_param_defs[i];
4901
+			u32 preset_val;
4902
+			/* Skip persistent params */
4903
+			if (defs->is_persistent)
4904
+				continue;
4905
+
4906
+			/* Find preset value */
4907
+			if (grc_param == DBG_GRC_PARAM_EXCLUDE_ALL)
4908
+				preset_val =
4909
+				    defs->exclude_all_preset_val;
4910
+			else if (grc_param == DBG_GRC_PARAM_CRASH)
4911
+				preset_val =
4912
+				    defs->crash_preset_val[dev_data->chip_id];
4913
+			else
4914
+				return DBG_STATUS_INVALID_ARGS;
4915
+
4916
+			qed_grc_set_param(p_hwfn, i, preset_val);
4917
+		}
4918
+	} else {
4919
+		/* Regular param - set its value */
4920
+		qed_grc_set_param(p_hwfn, grc_param, val);
4921
+	}
4922
+
4923
+	return DBG_STATUS_OK;
51224924 }
51234925 
51244926 /* Assign default GRC param values */
....@@ -5137,18 +4939,18 @@
51374939 					      struct qed_ptt *p_ptt,
51384940 					      u32 *buf_size)
51394941 {
5140
-	enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt);
4942
+	enum dbg_status status = qed_dbg_dev_init(p_hwfn);
51414943 
51424944 	*buf_size = 0;
51434945 
51444946 	if (status != DBG_STATUS_OK)
51454947 		return status;
51464948 
5147
-	if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr ||
5148
-	    !s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr ||
5149
-	    !s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr ||
5150
-	    !s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr ||
5151
-	    !s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr)
4949
+	if (!p_hwfn->dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr ||
4950
+	    !p_hwfn->dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr ||
4951
+	    !p_hwfn->dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr ||
4952
+	    !p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr ||
4953
+	    !p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr)
51524954 		return DBG_STATUS_DBG_ARRAY_NOT_SET;
51534955 
51544956 	return qed_grc_dump(p_hwfn, p_ptt, NULL, false, buf_size);
....@@ -5188,20 +4990,19 @@
51884990 						   u32 *buf_size)
51894991 {
51904992 	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
5191
-	struct idle_chk_data *idle_chk;
4993
+	struct idle_chk_data *idle_chk = &dev_data->idle_chk;
51924994 	enum dbg_status status;
51934995 
5194
-	idle_chk = &dev_data->idle_chk;
51954996 	*buf_size = 0;
51964997 
5197
-	status = qed_dbg_dev_init(p_hwfn, p_ptt);
4998
+	status = qed_dbg_dev_init(p_hwfn);
51984999 	if (status != DBG_STATUS_OK)
51995000 		return status;
52005001 
5201
-	if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr ||
5202
-	    !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr ||
5203
-	    !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr ||
5204
-	    !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].ptr)
5002
+	if (!p_hwfn->dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr ||
5003
+	    !p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr ||
5004
+	    !p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr ||
5005
+	    !p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].ptr)
52055006 		return DBG_STATUS_DBG_ARRAY_NOT_SET;
52065007 
52075008 	if (!idle_chk->buf_size_set) {
....@@ -5236,6 +5037,7 @@
52365037 		return DBG_STATUS_DUMP_BUF_TOO_SMALL;
52375038 
52385039 	/* Update reset state */
5040
+	qed_grc_unreset_blocks(p_hwfn, p_ptt, true);
52395041 	qed_update_blocks_reset_state(p_hwfn, p_ptt);
52405042 
52415043 	/* Idle Check Dump */
....@@ -5251,7 +5053,7 @@
52515053 						    struct qed_ptt *p_ptt,
52525054 						    u32 *buf_size)
52535055 {
5254
-	enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt);
5056
+	enum dbg_status status = qed_dbg_dev_init(p_hwfn);
52555057 
52565058 	*buf_size = 0;
52575059 
....@@ -5298,7 +5100,7 @@
52985100 						   struct qed_ptt *p_ptt,
52995101 						   u32 *buf_size)
53005102 {
5301
-	enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt);
5103
+	enum dbg_status status = qed_dbg_dev_init(p_hwfn);
53025104 
53035105 	*buf_size = 0;
53045106 
....@@ -5344,7 +5146,7 @@
53445146 						   struct qed_ptt *p_ptt,
53455147 						   u32 *buf_size)
53465148 {
5347
-	enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt);
5149
+	enum dbg_status status = qed_dbg_dev_init(p_hwfn);
53485150 
53495151 	*buf_size = 0;
53505152 
....@@ -5390,7 +5192,7 @@
53905192 					      struct qed_ptt *p_ptt,
53915193 					      u32 *buf_size)
53925194 {
5393
-	enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt);
5195
+	enum dbg_status status = qed_dbg_dev_init(p_hwfn);
53945196 
53955197 	*buf_size = 0;
53965198 
....@@ -5440,7 +5242,7 @@
54405242 						     struct qed_ptt *p_ptt,
54415243 						     u32 *buf_size)
54425244 {
5443
-	enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt);
5245
+	enum dbg_status status = qed_dbg_dev_init(p_hwfn);
54445246 
54455247 	*buf_size = 0;
54465248 
....@@ -5484,6 +5286,50 @@
54845286 	return DBG_STATUS_OK;
54855287 }
54865288 
5289
+static enum dbg_status qed_dbg_ilt_get_dump_buf_size(struct qed_hwfn *p_hwfn,
5290
+						     struct qed_ptt *p_ptt,
5291
+						     u32 *buf_size)
5292
+{
5293
+	enum dbg_status status = qed_dbg_dev_init(p_hwfn);
5294
+
5295
+	*buf_size = 0;
5296
+
5297
+	if (status != DBG_STATUS_OK)
5298
+		return status;
5299
+
5300
+	*buf_size = qed_ilt_dump(p_hwfn, p_ptt, NULL, false);
5301
+
5302
+	return DBG_STATUS_OK;
5303
+}
5304
+
5305
+static enum dbg_status qed_dbg_ilt_dump(struct qed_hwfn *p_hwfn,
5306
+					struct qed_ptt *p_ptt,
5307
+					u32 *dump_buf,
5308
+					u32 buf_size_in_dwords,
5309
+					u32 *num_dumped_dwords)
5310
+{
5311
+	u32 needed_buf_size_in_dwords;
5312
+	enum dbg_status status;
5313
+
5314
+	*num_dumped_dwords = 0;
5315
+
5316
+	status = qed_dbg_ilt_get_dump_buf_size(p_hwfn,
5317
+					       p_ptt,
5318
+					       &needed_buf_size_in_dwords);
5319
+	if (status != DBG_STATUS_OK)
5320
+		return status;
5321
+
5322
+	if (buf_size_in_dwords < needed_buf_size_in_dwords)
5323
+		return DBG_STATUS_DUMP_BUF_TOO_SMALL;
5324
+
5325
+	*num_dumped_dwords = qed_ilt_dump(p_hwfn, p_ptt, dump_buf, true);
5326
+
5327
+	/* Reveret GRC params to their default */
5328
+	qed_dbg_grc_set_params_default(p_hwfn);
5329
+
5330
+	return DBG_STATUS_OK;
5331
+}
5332
+
54875333 enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn,
54885334 				  struct qed_ptt *p_ptt,
54895335 				  enum block_id block_id,
....@@ -5491,19 +5337,20 @@
54915337 				  bool clear_status,
54925338 				  struct dbg_attn_block_result *results)
54935339 {
5494
-	enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt);
5340
+	enum dbg_status status = qed_dbg_dev_init(p_hwfn);
54955341 	u8 reg_idx, num_attn_regs, num_result_regs = 0;
54965342 	const struct dbg_attn_reg *attn_reg_arr;
54975343 
54985344 	if (status != DBG_STATUS_OK)
54995345 		return status;
55005346 
5501
-	if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr ||
5502
-	    !s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr ||
5503
-	    !s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr)
5347
+	if (!p_hwfn->dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr ||
5348
+	    !p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr ||
5349
+	    !p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr)
55045350 		return DBG_STATUS_DBG_ARRAY_NOT_SET;
55055351 
5506
-	attn_reg_arr = qed_get_block_attn_regs(block_id,
5352
+	attn_reg_arr = qed_get_block_attn_regs(p_hwfn,
5353
+					       block_id,
55075354 					       attn_type, &num_attn_regs);
55085355 
55095356 	for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) {
....@@ -5548,7 +5395,7 @@
55485395 
55495396 	results->block_id = (u8)block_id;
55505397 	results->names_offset =
5551
-	    qed_get_block_attn_data(block_id, attn_type)->names_offset;
5398
+	    qed_get_block_attn_data(p_hwfn, block_id, attn_type)->names_offset;
55525399 	SET_FIELD(results->data, DBG_ATTN_BLOCK_RESULT_ATTN_TYPE, attn_type);
55535400 	SET_FIELD(results->data,
55545401 		  DBG_ATTN_BLOCK_RESULT_NUM_REGS, num_result_regs);
....@@ -5557,40 +5404,6 @@
55575404 }
55585405 
55595406 /******************************* Data Types **********************************/
5560
-
5561
-struct block_info {
5562
-	const char *name;
5563
-	enum block_id id;
5564
-};
5565
-
5566
-struct mcp_trace_format {
5567
-	u32 data;
5568
-#define MCP_TRACE_FORMAT_MODULE_MASK	0x0000ffff
5569
-#define MCP_TRACE_FORMAT_MODULE_SHIFT	0
5570
-#define MCP_TRACE_FORMAT_LEVEL_MASK	0x00030000
5571
-#define MCP_TRACE_FORMAT_LEVEL_SHIFT	16
5572
-#define MCP_TRACE_FORMAT_P1_SIZE_MASK	0x000c0000
5573
-#define MCP_TRACE_FORMAT_P1_SIZE_SHIFT	18
5574
-#define MCP_TRACE_FORMAT_P2_SIZE_MASK	0x00300000
5575
-#define MCP_TRACE_FORMAT_P2_SIZE_SHIFT	20
5576
-#define MCP_TRACE_FORMAT_P3_SIZE_MASK	0x00c00000
5577
-#define MCP_TRACE_FORMAT_P3_SIZE_SHIFT	22
5578
-#define MCP_TRACE_FORMAT_LEN_MASK	0xff000000
5579
-#define MCP_TRACE_FORMAT_LEN_SHIFT	24
5580
-
5581
-	char *format_str;
5582
-};
5583
-
5584
-/* Meta data structure, generated by a perl script during MFW build. therefore,
5585
- * the structs mcp_trace_meta and mcp_trace_format are duplicated in the perl
5586
- * script.
5587
- */
5588
-struct mcp_trace_meta {
5589
-	u32 modules_num;
5590
-	char **modules;
5591
-	u32 formats_num;
5592
-	struct mcp_trace_format *formats;
5593
-};
55945407 
55955408 /* REG fifo element */
55965409 struct reg_fifo_element {
....@@ -5613,6 +5426,12 @@
56135426 #define REG_FIFO_ELEMENT_MASTER_MASK		0xf
56145427 #define REG_FIFO_ELEMENT_ERROR_SHIFT		47
56155428 #define REG_FIFO_ELEMENT_ERROR_MASK		0x1f
5429
+};
5430
+
5431
+/* REG fifo error element */
5432
+struct reg_fifo_err {
5433
+	u32 err_code;
5434
+	const char *err_msg;
56165435 };
56175436 
56185437 /* IGU fifo element */
....@@ -5721,7 +5540,7 @@
57215540 #define MCP_TRACE_MAX_MODULE_LEN		8
57225541 #define MCP_TRACE_FORMAT_MAX_PARAMS		3
57235542 #define MCP_TRACE_FORMAT_PARAM_WIDTH \
5724
-	(MCP_TRACE_FORMAT_P2_SIZE_SHIFT - MCP_TRACE_FORMAT_P1_SIZE_SHIFT)
5543
+	(MCP_TRACE_FORMAT_P2_SIZE_OFFSET - MCP_TRACE_FORMAT_P1_SIZE_OFFSET)
57255544 
57265545 #define REG_FIFO_ELEMENT_ADDR_FACTOR		4
57275546 #define REG_FIFO_ELEMENT_IS_PF_VF_VAL		127
....@@ -5729,107 +5548,6 @@
57295548 #define PROTECTION_OVERRIDE_ELEMENT_ADDR_FACTOR	4
57305549 
57315550 /***************************** Constant Arrays *******************************/
5732
-
5733
-struct user_dbg_array {
5734
-	const u32 *ptr;
5735
-	u32 size_in_dwords;
5736
-};
5737
-
5738
-/* Debug arrays */
5739
-static struct user_dbg_array
5740
-s_user_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { {NULL} };
5741
-
5742
-/* Block names array */
5743
-static struct block_info s_block_info_arr[] = {
5744
-	{"grc", BLOCK_GRC},
5745
-	{"miscs", BLOCK_MISCS},
5746
-	{"misc", BLOCK_MISC},
5747
-	{"dbu", BLOCK_DBU},
5748
-	{"pglue_b", BLOCK_PGLUE_B},
5749
-	{"cnig", BLOCK_CNIG},
5750
-	{"cpmu", BLOCK_CPMU},
5751
-	{"ncsi", BLOCK_NCSI},
5752
-	{"opte", BLOCK_OPTE},
5753
-	{"bmb", BLOCK_BMB},
5754
-	{"pcie", BLOCK_PCIE},
5755
-	{"mcp", BLOCK_MCP},
5756
-	{"mcp2", BLOCK_MCP2},
5757
-	{"pswhst", BLOCK_PSWHST},
5758
-	{"pswhst2", BLOCK_PSWHST2},
5759
-	{"pswrd", BLOCK_PSWRD},
5760
-	{"pswrd2", BLOCK_PSWRD2},
5761
-	{"pswwr", BLOCK_PSWWR},
5762
-	{"pswwr2", BLOCK_PSWWR2},
5763
-	{"pswrq", BLOCK_PSWRQ},
5764
-	{"pswrq2", BLOCK_PSWRQ2},
5765
-	{"pglcs", BLOCK_PGLCS},
5766
-	{"ptu", BLOCK_PTU},
5767
-	{"dmae", BLOCK_DMAE},
5768
-	{"tcm", BLOCK_TCM},
5769
-	{"mcm", BLOCK_MCM},
5770
-	{"ucm", BLOCK_UCM},
5771
-	{"xcm", BLOCK_XCM},
5772
-	{"ycm", BLOCK_YCM},
5773
-	{"pcm", BLOCK_PCM},
5774
-	{"qm", BLOCK_QM},
5775
-	{"tm", BLOCK_TM},
5776
-	{"dorq", BLOCK_DORQ},
5777
-	{"brb", BLOCK_BRB},
5778
-	{"src", BLOCK_SRC},
5779
-	{"prs", BLOCK_PRS},
5780
-	{"tsdm", BLOCK_TSDM},
5781
-	{"msdm", BLOCK_MSDM},
5782
-	{"usdm", BLOCK_USDM},
5783
-	{"xsdm", BLOCK_XSDM},
5784
-	{"ysdm", BLOCK_YSDM},
5785
-	{"psdm", BLOCK_PSDM},
5786
-	{"tsem", BLOCK_TSEM},
5787
-	{"msem", BLOCK_MSEM},
5788
-	{"usem", BLOCK_USEM},
5789
-	{"xsem", BLOCK_XSEM},
5790
-	{"ysem", BLOCK_YSEM},
5791
-	{"psem", BLOCK_PSEM},
5792
-	{"rss", BLOCK_RSS},
5793
-	{"tmld", BLOCK_TMLD},
5794
-	{"muld", BLOCK_MULD},
5795
-	{"yuld", BLOCK_YULD},
5796
-	{"xyld", BLOCK_XYLD},
5797
-	{"ptld", BLOCK_PTLD},
5798
-	{"ypld", BLOCK_YPLD},
5799
-	{"prm", BLOCK_PRM},
5800
-	{"pbf_pb1", BLOCK_PBF_PB1},
5801
-	{"pbf_pb2", BLOCK_PBF_PB2},
5802
-	{"rpb", BLOCK_RPB},
5803
-	{"btb", BLOCK_BTB},
5804
-	{"pbf", BLOCK_PBF},
5805
-	{"rdif", BLOCK_RDIF},
5806
-	{"tdif", BLOCK_TDIF},
5807
-	{"cdu", BLOCK_CDU},
5808
-	{"ccfc", BLOCK_CCFC},
5809
-	{"tcfc", BLOCK_TCFC},
5810
-	{"igu", BLOCK_IGU},
5811
-	{"cau", BLOCK_CAU},
5812
-	{"rgfs", BLOCK_RGFS},
5813
-	{"rgsrc", BLOCK_RGSRC},
5814
-	{"tgfs", BLOCK_TGFS},
5815
-	{"tgsrc", BLOCK_TGSRC},
5816
-	{"umac", BLOCK_UMAC},
5817
-	{"xmac", BLOCK_XMAC},
5818
-	{"dbg", BLOCK_DBG},
5819
-	{"nig", BLOCK_NIG},
5820
-	{"wol", BLOCK_WOL},
5821
-	{"bmbn", BLOCK_BMBN},
5822
-	{"ipc", BLOCK_IPC},
5823
-	{"nwm", BLOCK_NWM},
5824
-	{"nws", BLOCK_NWS},
5825
-	{"ms", BLOCK_MS},
5826
-	{"phy_pcie", BLOCK_PHY_PCIE},
5827
-	{"led", BLOCK_LED},
5828
-	{"avs_wrap", BLOCK_AVS_WRAP},
5829
-	{"pxpreqbus", BLOCK_PXPREQBUS},
5830
-	{"misc_aeu", BLOCK_MISC_AEU},
5831
-	{"bar0_map", BLOCK_BAR0_MAP}
5832
-};
58335551 
58345552 /* Status string array */
58355553 static const char * const s_status_str[] = {
....@@ -5860,14 +5578,13 @@
58605578 	/* DBG_STATUS_PCI_BUF_NOT_ALLOCATED */
58615579 	"A PCI buffer wasn't allocated",
58625580 
5863
-	/* DBG_STATUS_TOO_MANY_INPUTS */
5864
-	"Too many inputs were enabled. Enabled less inputs, or set 'unifyInputs' to true",
5581
+	/* DBG_STATUS_INVALID_FILTER_TRIGGER_DWORDS */
5582
+	"The filter/trigger constraint dword offsets are not enabled for recording",
5583
+	/* DBG_STATUS_NO_MATCHING_FRAMING_MODE */
5584
+	"No matching framing mode",
58655585 
5866
-	/* DBG_STATUS_INPUT_OVERLAP */
5867
-	"Overlapping debug bus inputs",
5868
-
5869
-	/* DBG_STATUS_HW_ONLY_RECORDING */
5870
-	"Cannot record Storm data since the entire recording cycle is used by HW",
5586
+	/* DBG_STATUS_VFC_READ_ERROR */
5587
+	"Error reading from VFC",
58715588 
58725589 	/* DBG_STATUS_STORM_ALREADY_ENABLED */
58735590 	"The Storm was already enabled",
....@@ -5884,8 +5601,8 @@
58845601 	/* DBG_STATUS_NO_INPUT_ENABLED */
58855602 	"No input was enabled for recording",
58865603 
5887
-	/* DBG_STATUS_NO_FILTER_TRIGGER_64B */
5888
-	"Filters and triggers are not allowed when recording in 64b units",
5604
+	/* DBG_STATUS_NO_FILTER_TRIGGER_256B */
5605
+	"Filters and triggers are not allowed in E4 256-bit mode",
58895606 
58905607 	/* DBG_STATUS_FILTER_ALREADY_ENABLED */
58915608 	"The filter was already enabled",
....@@ -5959,8 +5676,8 @@
59595676 	/* DBG_STATUS_MCP_COULD_NOT_RESUME */
59605677 	"Failed to resume MCP after halt",
59615678 
5962
-	/* DBG_STATUS_RESERVED2 */
5963
-	"Reserved debug status - shouldn't be returned",
5679
+	/* DBG_STATUS_RESERVED0 */
5680
+	"",
59645681 
59655682 	/* DBG_STATUS_SEMI_FIFO_NOT_EMPTY */
59665683 	"Failed to empty SEMI sync FIFO",
....@@ -5983,17 +5700,32 @@
59835700 	/* DBG_STATUS_DBG_ARRAY_NOT_SET */
59845701 	"Debug arrays were not set (when using binary files, dbg_set_bin_ptr must be called)",
59855702 
5986
-	/* DBG_STATUS_FILTER_BUG */
5987
-	"Debug Bus filtering requires the -unifyInputs option (due to a HW bug)",
5703
+	/* DBG_STATUS_RESERVED1 */
5704
+	"",
59885705 
59895706 	/* DBG_STATUS_NON_MATCHING_LINES */
5990
-	"Non-matching debug lines - all lines must be of the same type (either 128b or 256b)",
5707
+	"Non-matching debug lines - in E4, all lines must be of the same type (either 128b or 256b)",
59915708 
5992
-	/* DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET */
5993
-	"The selected trigger dword offset wasn't enabled in the recorded HW block",
5709
+	/* DBG_STATUS_INSUFFICIENT_HW_IDS */
5710
+	"Insufficient HW IDs. Try to record less Storms/blocks",
59945711 
59955712 	/* DBG_STATUS_DBG_BUS_IN_USE */
5996
-	"The debug bus is in use"
5713
+	"The debug bus is in use",
5714
+
5715
+	/* DBG_STATUS_INVALID_STORM_DBG_MODE */
5716
+	"The storm debug mode is not supported in the current chip",
5717
+
5718
+	/* DBG_STATUS_OTHER_ENGINE_BB_ONLY */
5719
+	"Other engine is supported only in BB",
5720
+
5721
+	/* DBG_STATUS_FILTER_SINGLE_HW_ID */
5722
+	"The configured filter mode requires a single Storm/block input",
5723
+
5724
+	/* DBG_STATUS_TRIGGER_SINGLE_HW_ID */
5725
+	"The configured filter mode requires that all the constraints of a single trigger state will be defined on a single Storm/block input",
5726
+
5727
+	/* DBG_STATUS_MISSING_TRIGGER_STATE_STORM */
5728
+	"When triggering on Storm data, the Storm to trigger on must be specified"
59975729 };
59985730 
59995731 /* Idle check severity names array */
....@@ -6049,7 +5781,7 @@
60495781 	"xsdm",
60505782 	"dbu",
60515783 	"dmae",
6052
-	"???",
5784
+	"jdap",
60535785 	"???",
60545786 	"???",
60555787 	"???",
....@@ -6057,12 +5789,13 @@
60575789 };
60585790 
60595791 /* REG FIFO error messages array */
6060
-static const char * const s_reg_fifo_error_strs[] = {
6061
-	"grc timeout",
6062
-	"address doesn't belong to any block",
6063
-	"reserved address in block or write to read-only address",
6064
-	"privilege/protection mismatch",
6065
-	"path isolation error"
5792
+static struct reg_fifo_err s_reg_fifo_errors[] = {
5793
+	{1, "grc timeout"},
5794
+	{2, "address doesn't belong to any block"},
5795
+	{4, "reserved address in block or write to read-only address"},
5796
+	{8, "privilege/protection mismatch"},
5797
+	{16, "path isolation error"},
5798
+	{17, "RSL error"}
60665799 };
60675800 
60685801 /* IGU FIFO sources array */
....@@ -6085,7 +5818,7 @@
60855818 	"no error",
60865819 	"length error",
60875820 	"function disabled",
6088
-	"VF sent command to attnetion address",
5821
+	"VF sent command to attention address",
60895822 	"host sent prod update command",
60905823 	"read of during interrupt register while in MIMD mode",
60915824 	"access to PXP BAR reserved address",
....@@ -6136,15 +5869,6 @@
61365869 };
61375870 
61385871 /******************************** Variables **********************************/
6139
-
6140
-/* MCP Trace meta data array - used in case the dump doesn't contain the
6141
- * meta data (e.g. due to no NVRAM access).
6142
- */
6143
-static struct user_dbg_array s_mcp_trace_meta_arr = { NULL, 0 };
6144
-
6145
-/* Parsed MCP Trace meta data info, based on MCP trace meta array */
6146
-static struct mcp_trace_meta s_mcp_trace_meta;
6147
-static bool s_mcp_trace_meta_valid;
61485872 
61495873 /* Temporary buffer, used for print size calculations */
61505874 static char s_temp_buf[MAX_MSG_LEN];
....@@ -6311,10 +6035,30 @@
63116035 	return dump_offset;
63126036 }
63136037 
6038
+/* Returns the block name that matches the specified block ID,
6039
+ * or NULL if not found.
6040
+ */
6041
+static const char *qed_dbg_get_block_name(struct qed_hwfn *p_hwfn,
6042
+					  enum block_id block_id)
6043
+{
6044
+	const struct dbg_block_user *block =
6045
+	    (const struct dbg_block_user *)
6046
+	    p_hwfn->dbg_arrays[BIN_BUF_DBG_BLOCKS_USER_DATA].ptr + block_id;
6047
+
6048
+	return (const char *)block->name;
6049
+}
6050
+
6051
+static struct dbg_tools_user_data *qed_dbg_get_user_data(struct qed_hwfn
6052
+							 *p_hwfn)
6053
+{
6054
+	return (struct dbg_tools_user_data *)p_hwfn->dbg_user_info;
6055
+}
6056
+
63146057 /* Parses the idle check rules and returns the number of characters printed.
63156058  * In case of parsing error, returns 0.
63166059  */
6317
-static u32 qed_parse_idle_chk_dump_rules(u32 *dump_buf,
6060
+static u32 qed_parse_idle_chk_dump_rules(struct qed_hwfn *p_hwfn,
6061
+					 u32 *dump_buf,
63186062 					 u32 *dump_buf_end,
63196063 					 u32 num_rules,
63206064 					 bool print_fw_idle_chk,
....@@ -6342,19 +6086,18 @@
63426086 
63436087 		hdr = (struct dbg_idle_chk_result_hdr *)dump_buf;
63446088 		rule_parsing_data =
6345
-			(const struct dbg_idle_chk_rule_parsing_data *)
6346
-			&s_user_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_PARSING_DATA].
6347
-			ptr[hdr->rule_id];
6089
+		    (const struct dbg_idle_chk_rule_parsing_data *)
6090
+		    p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_PARSING_DATA].ptr +
6091
+		    hdr->rule_id;
63486092 		parsing_str_offset =
6349
-			GET_FIELD(rule_parsing_data->data,
6350
-				  DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET);
6093
+		    GET_FIELD(rule_parsing_data->data,
6094
+			      DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET);
63516095 		has_fw_msg =
6352
-			GET_FIELD(rule_parsing_data->data,
6353
-				DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG) > 0;
6354
-		parsing_str =
6355
-			&((const char *)
6356
-			s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr)
6357
-			[parsing_str_offset];
6096
+		    GET_FIELD(rule_parsing_data->data,
6097
+			      DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG) > 0;
6098
+		parsing_str = (const char *)
6099
+		    p_hwfn->dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr +
6100
+		    parsing_str_offset;
63586101 		lsi_msg = parsing_str;
63596102 		curr_reg_id = 0;
63606103 
....@@ -6458,7 +6201,8 @@
64586201  * parsed_results_bytes.
64596202  * The parsing status is returned.
64606203  */
6461
-static enum dbg_status qed_parse_idle_chk_dump(u32 *dump_buf,
6204
+static enum dbg_status qed_parse_idle_chk_dump(struct qed_hwfn *p_hwfn,
6205
+					       u32 *dump_buf,
64626206 					       u32 num_dumped_dwords,
64636207 					       char *results_buf,
64646208 					       u32 *parsed_results_bytes,
....@@ -6476,8 +6220,8 @@
64766220 	*num_errors = 0;
64776221 	*num_warnings = 0;
64786222 
6479
-	if (!s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr ||
6480
-	    !s_user_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_PARSING_DATA].ptr)
6223
+	if (!p_hwfn->dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr ||
6224
+	    !p_hwfn->dbg_arrays[BIN_BUF_DBG_IDLE_CHK_PARSING_DATA].ptr)
64816225 		return DBG_STATUS_DBG_ARRAY_NOT_SET;
64826226 
64836227 	/* Read global_params section */
....@@ -6510,7 +6254,8 @@
65106254 					    results_offset),
65116255 			    "FW_IDLE_CHECK:\n");
65126256 		rules_print_size =
6513
-			qed_parse_idle_chk_dump_rules(dump_buf,
6257
+			qed_parse_idle_chk_dump_rules(p_hwfn,
6258
+						      dump_buf,
65146259 						      dump_buf_end,
65156260 						      num_rules,
65166261 						      true,
....@@ -6530,7 +6275,8 @@
65306275 					    results_offset),
65316276 			    "\nLSI_IDLE_CHECK:\n");
65326277 		rules_print_size =
6533
-			qed_parse_idle_chk_dump_rules(dump_buf,
6278
+			qed_parse_idle_chk_dump_rules(p_hwfn,
6279
+						      dump_buf,
65346280 						      dump_buf_end,
65356281 						      num_rules,
65366282 						      false,
....@@ -6570,43 +6316,26 @@
65706316 	return DBG_STATUS_OK;
65716317 }
65726318 
6573
-/* Frees the specified MCP Trace meta data */
6574
-static void qed_mcp_trace_free_meta(struct qed_hwfn *p_hwfn,
6575
-				    struct mcp_trace_meta *meta)
6576
-{
6577
-	u32 i;
6578
-
6579
-	s_mcp_trace_meta_valid = false;
6580
-
6581
-	/* Release modules */
6582
-	if (meta->modules) {
6583
-		for (i = 0; i < meta->modules_num; i++)
6584
-			kfree(meta->modules[i]);
6585
-		kfree(meta->modules);
6586
-	}
6587
-
6588
-	/* Release formats */
6589
-	if (meta->formats) {
6590
-		for (i = 0; i < meta->formats_num; i++)
6591
-			kfree(meta->formats[i].format_str);
6592
-		kfree(meta->formats);
6593
-	}
6594
-}
6595
-
65966319 /* Allocates and fills MCP Trace meta data based on the specified meta data
65976320  * dump buffer.
65986321  * Returns debug status code.
65996322  */
6600
-static enum dbg_status qed_mcp_trace_alloc_meta(struct qed_hwfn *p_hwfn,
6601
-						const u32 *meta_buf,
6602
-						struct mcp_trace_meta *meta)
6323
+static enum dbg_status
6324
+qed_mcp_trace_alloc_meta_data(struct qed_hwfn *p_hwfn,
6325
+			      const u32 *meta_buf)
66036326 {
6604
-	u8 *meta_buf_bytes = (u8 *)meta_buf;
6327
+	struct dbg_tools_user_data *dev_user_data;
66056328 	u32 offset = 0, signature, i;
6329
+	struct mcp_trace_meta *meta;
6330
+	u8 *meta_buf_bytes;
6331
+
6332
+	dev_user_data = qed_dbg_get_user_data(p_hwfn);
6333
+	meta = &dev_user_data->mcp_trace_meta;
6334
+	meta_buf_bytes = (u8 *)meta_buf;
66066335 
66076336 	/* Free the previous meta before loading a new one. */
6608
-	if (s_mcp_trace_meta_valid)
6609
-		qed_mcp_trace_free_meta(p_hwfn, meta);
6337
+	if (meta->is_allocated)
6338
+		qed_mcp_trace_free_meta_data(p_hwfn);
66106339 
66116340 	memset(meta, 0, sizeof(*meta));
66126341 
....@@ -6659,9 +6388,8 @@
66596388 
66606389 		format_ptr->data = qed_read_dword_from_buf(meta_buf_bytes,
66616390 							   &offset);
6662
-		format_len =
6663
-		    (format_ptr->data &
6664
-		     MCP_TRACE_FORMAT_LEN_MASK) >> MCP_TRACE_FORMAT_LEN_SHIFT;
6391
+		format_len = GET_MFW_FIELD(format_ptr->data,
6392
+					   MCP_TRACE_FORMAT_LEN);
66656393 		format_ptr->format_str = kzalloc(format_len, GFP_KERNEL);
66666394 		if (!format_ptr->format_str) {
66676395 			/* Update number of modules to be released */
....@@ -6674,7 +6402,7 @@
66746402 				      format_len, format_ptr->format_str);
66756403 	}
66766404 
6677
-	s_mcp_trace_meta_valid = true;
6405
+	meta->is_allocated = true;
66786406 	return DBG_STATUS_OK;
66796407 }
66806408 
....@@ -6684,24 +6412,29 @@
66846412  * trace_buf - MCP trace cyclic buffer
66856413  * trace_buf_size - MCP trace cyclic buffer size in bytes
66866414  * data_offset - offset in bytes of the data to parse in the MCP trace cyclic
6687
- *               buffer.
6415
+ *		 buffer.
66886416  * data_size - size in bytes of data to parse.
66896417  * parsed_buf - destination buffer for parsed data.
6690
- * parsed_bytes - size of parsed data in bytes.
6418
+ * parsed_results_bytes - size of parsed data in bytes.
66916419  */
6692
-static enum dbg_status qed_parse_mcp_trace_buf(u8 *trace_buf,
6420
+static enum dbg_status qed_parse_mcp_trace_buf(struct qed_hwfn *p_hwfn,
6421
+					       u8 *trace_buf,
66936422 					       u32 trace_buf_size,
66946423 					       u32 data_offset,
66956424 					       u32 data_size,
66966425 					       char *parsed_buf,
6697
-					       u32 *parsed_bytes)
6426
+					       u32 *parsed_results_bytes)
66986427 {
6428
+	struct dbg_tools_user_data *dev_user_data;
6429
+	struct mcp_trace_meta *meta;
66996430 	u32 param_mask, param_shift;
67006431 	enum dbg_status status;
67016432 
6702
-	*parsed_bytes = 0;
6433
+	dev_user_data = qed_dbg_get_user_data(p_hwfn);
6434
+	meta = &dev_user_data->mcp_trace_meta;
6435
+	*parsed_results_bytes = 0;
67036436 
6704
-	if (!s_mcp_trace_meta_valid)
6437
+	if (!meta->is_allocated)
67056438 		return DBG_STATUS_MCP_TRACE_BAD_DATA;
67066439 
67076440 	status = DBG_STATUS_OK;
....@@ -6723,10 +6456,9 @@
67236456 		format_idx = header & MFW_TRACE_EVENTID_MASK;
67246457 
67256458 		/* Skip message if its index doesn't exist in the meta data */
6726
-		if (format_idx >= s_mcp_trace_meta.formats_num) {
6727
-			u8 format_size =
6728
-				(u8)((header & MFW_TRACE_PRM_SIZE_MASK) >>
6729
-				     MFW_TRACE_PRM_SIZE_SHIFT);
6459
+		if (format_idx >= meta->formats_num) {
6460
+			u8 format_size = (u8)GET_MFW_FIELD(header,
6461
+							   MFW_TRACE_PRM_SIZE);
67306462 
67316463 			if (data_size < format_size)
67326464 				return DBG_STATUS_MCP_TRACE_BAD_DATA;
....@@ -6738,14 +6470,13 @@
67386470 			continue;
67396471 		}
67406472 
6741
-		format_ptr = &s_mcp_trace_meta.formats[format_idx];
6473
+		format_ptr = &meta->formats[format_idx];
67426474 
67436475 		for (i = 0,
6744
-		     param_mask = MCP_TRACE_FORMAT_P1_SIZE_MASK,
6745
-		     param_shift = MCP_TRACE_FORMAT_P1_SIZE_SHIFT;
6476
+		     param_mask = MCP_TRACE_FORMAT_P1_SIZE_MASK, param_shift =
6477
+		     MCP_TRACE_FORMAT_P1_SIZE_OFFSET;
67466478 		     i < MCP_TRACE_FORMAT_MAX_PARAMS;
6747
-		     i++,
6748
-		     param_mask <<= MCP_TRACE_FORMAT_PARAM_WIDTH,
6479
+		     i++, param_mask <<= MCP_TRACE_FORMAT_PARAM_WIDTH,
67496480 		     param_shift += MCP_TRACE_FORMAT_PARAM_WIDTH) {
67506481 			/* Extract param size (0..3) */
67516482 			u8 param_size = (u8)((format_ptr->data & param_mask) >>
....@@ -6773,29 +6504,28 @@
67736504 			data_size -= param_size;
67746505 		}
67756506 
6776
-		format_level = (u8)((format_ptr->data &
6777
-				     MCP_TRACE_FORMAT_LEVEL_MASK) >>
6778
-				    MCP_TRACE_FORMAT_LEVEL_SHIFT);
6779
-		format_module = (u8)((format_ptr->data &
6780
-				      MCP_TRACE_FORMAT_MODULE_MASK) >>
6781
-				     MCP_TRACE_FORMAT_MODULE_SHIFT);
6507
+		format_level = (u8)GET_MFW_FIELD(format_ptr->data,
6508
+						 MCP_TRACE_FORMAT_LEVEL);
6509
+		format_module = (u8)GET_MFW_FIELD(format_ptr->data,
6510
+						  MCP_TRACE_FORMAT_MODULE);
67826511 		if (format_level >= ARRAY_SIZE(s_mcp_trace_level_str))
67836512 			return DBG_STATUS_MCP_TRACE_BAD_DATA;
67846513 
67856514 		/* Print current message to results buffer */
6786
-		*parsed_bytes +=
6787
-			sprintf(qed_get_buf_ptr(parsed_buf, *parsed_bytes),
6515
+		*parsed_results_bytes +=
6516
+			sprintf(qed_get_buf_ptr(parsed_buf,
6517
+						*parsed_results_bytes),
67886518 				"%s %-8s: ",
67896519 				s_mcp_trace_level_str[format_level],
6790
-				s_mcp_trace_meta.modules[format_module]);
6791
-		*parsed_bytes +=
6792
-		    sprintf(qed_get_buf_ptr(parsed_buf, *parsed_bytes),
6520
+				meta->modules[format_module]);
6521
+		*parsed_results_bytes +=
6522
+		    sprintf(qed_get_buf_ptr(parsed_buf, *parsed_results_bytes),
67936523 			    format_ptr->format_str,
67946524 			    params[0], params[1], params[2]);
67956525 	}
67966526 
67976527 	/* Add string NULL terminator */
6798
-	(*parsed_bytes)++;
6528
+	(*parsed_results_bytes)++;
67996529 
68006530 	return status;
68016531 }
....@@ -6803,24 +6533,25 @@
68036533 /* Parses an MCP Trace dump buffer.
68046534  * If result_buf is not NULL, the MCP Trace results are printed to it.
68056535  * In any case, the required results buffer size is assigned to
6806
- * parsed_bytes.
6536
+ * parsed_results_bytes.
68076537  * The parsing status is returned.
68086538  */
68096539 static enum dbg_status qed_parse_mcp_trace_dump(struct qed_hwfn *p_hwfn,
68106540 						u32 *dump_buf,
6811
-						char *parsed_buf,
6812
-						u32 *parsed_bytes)
6541
+						char *results_buf,
6542
+						u32 *parsed_results_bytes,
6543
+						bool free_meta_data)
68136544 {
68146545 	const char *section_name, *param_name, *param_str_val;
68156546 	u32 data_size, trace_data_dwords, trace_meta_dwords;
6816
-	u32 offset, results_offset, parsed_buf_bytes;
6547
+	u32 offset, results_offset, results_buf_bytes;
68176548 	u32 param_num_val, num_section_params;
68186549 	struct mcp_trace *trace;
68196550 	enum dbg_status status;
68206551 	const u32 *meta_buf;
68216552 	u8 *trace_buf;
68226553 
6823
-	*parsed_bytes = 0;
6554
+	*parsed_results_bytes = 0;
68246555 
68256556 	/* Read global_params section */
68266557 	dump_buf += qed_read_section_hdr(dump_buf,
....@@ -6831,7 +6562,7 @@
68316562 	/* Print global params */
68326563 	dump_buf += qed_print_section_params(dump_buf,
68336564 					     num_section_params,
6834
-					     parsed_buf, &results_offset);
6565
+					     results_buf, &results_offset);
68356566 
68366567 	/* Read trace_data section */
68376568 	dump_buf += qed_read_section_hdr(dump_buf,
....@@ -6846,6 +6577,9 @@
68466577 
68476578 	/* Prepare trace info */
68486579 	trace = (struct mcp_trace *)dump_buf;
6580
+	if (trace->signature != MFW_TRACE_SIGNATURE || !trace->size)
6581
+		return DBG_STATUS_MCP_TRACE_BAD_DATA;
6582
+
68496583 	trace_buf = (u8 *)dump_buf + sizeof(*trace);
68506584 	offset = trace->trace_oldest;
68516585 	data_size = qed_cyclic_sub(trace->trace_prod, offset, trace->size);
....@@ -6865,31 +6599,39 @@
68656599 	/* Choose meta data buffer */
68666600 	if (!trace_meta_dwords) {
68676601 		/* Dump doesn't include meta data */
6868
-		if (!s_mcp_trace_meta_arr.ptr)
6602
+		struct dbg_tools_user_data *dev_user_data =
6603
+			qed_dbg_get_user_data(p_hwfn);
6604
+
6605
+		if (!dev_user_data->mcp_trace_user_meta_buf)
68696606 			return DBG_STATUS_MCP_TRACE_NO_META;
6870
-		meta_buf = s_mcp_trace_meta_arr.ptr;
6607
+
6608
+		meta_buf = dev_user_data->mcp_trace_user_meta_buf;
68716609 	} else {
68726610 		/* Dump includes meta data */
68736611 		meta_buf = dump_buf;
68746612 	}
68756613 
68766614 	/* Allocate meta data memory */
6877
-	status = qed_mcp_trace_alloc_meta(p_hwfn, meta_buf, &s_mcp_trace_meta);
6615
+	status = qed_mcp_trace_alloc_meta_data(p_hwfn, meta_buf);
68786616 	if (status != DBG_STATUS_OK)
68796617 		return status;
68806618 
6881
-	status = qed_parse_mcp_trace_buf(trace_buf,
6619
+	status = qed_parse_mcp_trace_buf(p_hwfn,
6620
+					 trace_buf,
68826621 					 trace->size,
68836622 					 offset,
68846623 					 data_size,
6885
-					 parsed_buf ?
6886
-					 parsed_buf + results_offset :
6624
+					 results_buf ?
6625
+					 results_buf + results_offset :
68876626 					 NULL,
6888
-					 &parsed_buf_bytes);
6627
+					 &results_buf_bytes);
68896628 	if (status != DBG_STATUS_OK)
68906629 		return status;
68916630 
6892
-	*parsed_bytes = results_offset + parsed_buf_bytes;
6631
+	if (free_meta_data)
6632
+		qed_mcp_trace_free_meta_data(p_hwfn);
6633
+
6634
+	*parsed_results_bytes = results_offset + results_buf_bytes;
68936635 
68946636 	return DBG_STATUS_OK;
68956637 }
....@@ -6907,7 +6649,7 @@
69076649 	const char *section_name, *param_name, *param_str_val;
69086650 	u32 param_num_val, num_section_params, num_elements;
69096651 	struct reg_fifo_element *elements;
6910
-	u8 i, j, err_val, vf_val;
6652
+	u8 i, j, err_code, vf_val;
69116653 	u32 results_offset = 0;
69126654 	char vf_str[4];
69136655 
....@@ -6938,7 +6680,7 @@
69386680 
69396681 	/* Decode elements */
69406682 	for (i = 0; i < num_elements; i++) {
6941
-		bool err_printed = false;
6683
+		const char *err_msg = NULL;
69426684 
69436685 		/* Discover if element belongs to a VF or a PF */
69446686 		vf_val = GET_FIELD(elements[i].data, REG_FIFO_ELEMENT_VF);
....@@ -6947,11 +6689,17 @@
69476689 		else
69486690 			sprintf(vf_str, "%d", vf_val);
69496691 
6692
+		/* Find error message */
6693
+		err_code = GET_FIELD(elements[i].data, REG_FIFO_ELEMENT_ERROR);
6694
+		for (j = 0; j < ARRAY_SIZE(s_reg_fifo_errors) && !err_msg; j++)
6695
+			if (err_code == s_reg_fifo_errors[j].err_code)
6696
+				err_msg = s_reg_fifo_errors[j].err_msg;
6697
+
69506698 		/* Add parsed element to parsed buffer */
69516699 		results_offset +=
69526700 		    sprintf(qed_get_buf_ptr(results_buf,
69536701 					    results_offset),
6954
-			    "raw: 0x%016llx, address: 0x%07x, access: %-5s, pf: %2d, vf: %s, port: %d, privilege: %-3s, protection: %-12s, master: %-4s, errors: ",
6702
+			    "raw: 0x%016llx, address: 0x%07x, access: %-5s, pf: %2d, vf: %s, port: %d, privilege: %-3s, protection: %-12s, master: %-4s, error: %s\n",
69556703 			    elements[i].data,
69566704 			    (u32)GET_FIELD(elements[i].data,
69576705 					   REG_FIFO_ELEMENT_ADDRESS) *
....@@ -6968,30 +6716,8 @@
69686716 			    s_protection_strs[GET_FIELD(elements[i].data,
69696717 						REG_FIFO_ELEMENT_PROTECTION)],
69706718 			    s_master_strs[GET_FIELD(elements[i].data,
6971
-						REG_FIFO_ELEMENT_MASTER)]);
6972
-
6973
-		/* Print errors */
6974
-		for (j = 0,
6975
-		     err_val = GET_FIELD(elements[i].data,
6976
-					 REG_FIFO_ELEMENT_ERROR);
6977
-		     j < ARRAY_SIZE(s_reg_fifo_error_strs);
6978
-		     j++, err_val >>= 1) {
6979
-			if (err_val & 0x1) {
6980
-				if (err_printed)
6981
-					results_offset +=
6982
-					    sprintf(qed_get_buf_ptr
6983
-						    (results_buf,
6984
-						     results_offset), ", ");
6985
-				results_offset +=
6986
-				    sprintf(qed_get_buf_ptr
6987
-					    (results_buf, results_offset), "%s",
6988
-					    s_reg_fifo_error_strs[j]);
6989
-				err_printed = true;
6990
-			}
6991
-		}
6992
-
6993
-		results_offset +=
6994
-		    sprintf(qed_get_buf_ptr(results_buf, results_offset), "\n");
6719
+						    REG_FIFO_ELEMENT_MASTER)],
6720
+			    err_msg ? err_msg : "unknown error code");
69956721 	}
69966722 
69976723 	results_offset += sprintf(qed_get_buf_ptr(results_buf,
....@@ -7345,18 +7071,29 @@
73457071 
73467072 /***************************** Public Functions *******************************/
73477073 
7348
-enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr)
7074
+enum dbg_status qed_dbg_user_set_bin_ptr(struct qed_hwfn *p_hwfn,
7075
+					 const u8 * const bin_ptr)
73497076 {
7350
-	struct bin_buffer_hdr *buf_array = (struct bin_buffer_hdr *)bin_ptr;
7077
+	struct bin_buffer_hdr *buf_hdrs = (struct bin_buffer_hdr *)bin_ptr;
73517078 	u8 buf_id;
73527079 
73537080 	/* Convert binary data to debug arrays */
7354
-	for (buf_id = 0; buf_id < MAX_BIN_DBG_BUFFER_TYPE; buf_id++) {
7355
-		s_user_dbg_arrays[buf_id].ptr =
7356
-			(u32 *)(bin_ptr + buf_array[buf_id].offset);
7357
-		s_user_dbg_arrays[buf_id].size_in_dwords =
7358
-			BYTES_TO_DWORDS(buf_array[buf_id].length);
7359
-	}
7081
+	for (buf_id = 0; buf_id < MAX_BIN_DBG_BUFFER_TYPE; buf_id++)
7082
+		qed_set_dbg_bin_buf(p_hwfn,
7083
+				    (enum bin_dbg_buffer_type)buf_id,
7084
+				    (u32 *)(bin_ptr + buf_hdrs[buf_id].offset),
7085
+				    buf_hdrs[buf_id].length);
7086
+
7087
+	return DBG_STATUS_OK;
7088
+}
7089
+
7090
+enum dbg_status qed_dbg_alloc_user_data(struct qed_hwfn *p_hwfn,
7091
+					void **user_data_ptr)
7092
+{
7093
+	*user_data_ptr = kzalloc(sizeof(struct dbg_tools_user_data),
7094
+				 GFP_KERNEL);
7095
+	if (!(*user_data_ptr))
7096
+		return DBG_STATUS_VIRT_MEM_ALLOC_FAILED;
73607097 
73617098 	return DBG_STATUS_OK;
73627099 }
....@@ -7374,7 +7111,8 @@
73747111 {
73757112 	u32 num_errors, num_warnings;
73767113 
7377
-	return qed_parse_idle_chk_dump(dump_buf,
7114
+	return qed_parse_idle_chk_dump(p_hwfn,
7115
+				       dump_buf,
73787116 				       num_dumped_dwords,
73797117 				       NULL,
73807118 				       results_buf_size,
....@@ -7390,17 +7128,21 @@
73907128 {
73917129 	u32 parsed_buf_size;
73927130 
7393
-	return qed_parse_idle_chk_dump(dump_buf,
7131
+	return qed_parse_idle_chk_dump(p_hwfn,
7132
+				       dump_buf,
73947133 				       num_dumped_dwords,
73957134 				       results_buf,
73967135 				       &parsed_buf_size,
73977136 				       num_errors, num_warnings);
73987137 }
73997138 
7400
-void qed_dbg_mcp_trace_set_meta_data(u32 *data, u32 size)
7139
+void qed_dbg_mcp_trace_set_meta_data(struct qed_hwfn *p_hwfn,
7140
+				     const u32 *meta_buf)
74017141 {
7402
-	s_mcp_trace_meta_arr.ptr = data;
7403
-	s_mcp_trace_meta_arr.size_in_dwords = size;
7142
+	struct dbg_tools_user_data *dev_user_data =
7143
+		qed_dbg_get_user_data(p_hwfn);
7144
+
7145
+	dev_user_data->mcp_trace_user_meta_buf = meta_buf;
74047146 }
74057147 
74067148 enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn,
....@@ -7409,7 +7151,7 @@
74097151 						   u32 *results_buf_size)
74107152 {
74117153 	return qed_parse_mcp_trace_dump(p_hwfn,
7412
-					dump_buf, NULL, results_buf_size);
7154
+					dump_buf, NULL, results_buf_size, true);
74137155 }
74147156 
74157157 enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
....@@ -7421,20 +7163,61 @@
74217163 
74227164 	return qed_parse_mcp_trace_dump(p_hwfn,
74237165 					dump_buf,
7424
-					results_buf, &parsed_buf_size);
7166
+					results_buf, &parsed_buf_size, true);
74257167 }
74267168 
7427
-enum dbg_status qed_print_mcp_trace_line(u8 *dump_buf,
7169
+enum dbg_status qed_print_mcp_trace_results_cont(struct qed_hwfn *p_hwfn,
7170
+						 u32 *dump_buf,
7171
+						 char *results_buf)
7172
+{
7173
+	u32 parsed_buf_size;
7174
+
7175
+	return qed_parse_mcp_trace_dump(p_hwfn, dump_buf, results_buf,
7176
+					&parsed_buf_size, false);
7177
+}
7178
+
7179
+enum dbg_status qed_print_mcp_trace_line(struct qed_hwfn *p_hwfn,
7180
+					 u8 *dump_buf,
74287181 					 u32 num_dumped_bytes,
74297182 					 char *results_buf)
74307183 {
7431
-	u32 parsed_bytes;
7184
+	u32 parsed_results_bytes;
74327185 
7433
-	return qed_parse_mcp_trace_buf(dump_buf,
7186
+	return qed_parse_mcp_trace_buf(p_hwfn,
7187
+				       dump_buf,
74347188 				       num_dumped_bytes,
74357189 				       0,
74367190 				       num_dumped_bytes,
7437
-				       results_buf, &parsed_bytes);
7191
+				       results_buf, &parsed_results_bytes);
7192
+}
7193
+
7194
+/* Frees the specified MCP Trace meta data */
7195
+void qed_mcp_trace_free_meta_data(struct qed_hwfn *p_hwfn)
7196
+{
7197
+	struct dbg_tools_user_data *dev_user_data;
7198
+	struct mcp_trace_meta *meta;
7199
+	u32 i;
7200
+
7201
+	dev_user_data = qed_dbg_get_user_data(p_hwfn);
7202
+	meta = &dev_user_data->mcp_trace_meta;
7203
+	if (!meta->is_allocated)
7204
+		return;
7205
+
7206
+	/* Release modules */
7207
+	if (meta->modules) {
7208
+		for (i = 0; i < meta->modules_num; i++)
7209
+			kfree(meta->modules[i]);
7210
+		kfree(meta->modules);
7211
+	}
7212
+
7213
+	/* Release formats */
7214
+	if (meta->formats) {
7215
+		for (i = 0; i < meta->formats_num; i++)
7216
+			kfree(meta->formats[i].format_str);
7217
+		kfree(meta->formats);
7218
+	}
7219
+
7220
+	meta->is_allocated = false;
74387221 }
74397222 
74407223 enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
....@@ -7517,25 +7300,28 @@
75177300 enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
75187301 				   struct dbg_attn_block_result *results)
75197302 {
7520
-	struct user_dbg_array *block_attn, *pstrings;
75217303 	const u32 *block_attn_name_offsets;
7522
-	enum dbg_attn_type attn_type;
7304
+	const char *attn_name_base;
75237305 	const char *block_name;
7306
+	enum dbg_attn_type attn_type;
75247307 	u8 num_regs, i, j;
75257308 
75267309 	num_regs = GET_FIELD(results->data, DBG_ATTN_BLOCK_RESULT_NUM_REGS);
7527
-	attn_type = (enum dbg_attn_type)
7528
-		    GET_FIELD(results->data,
7529
-			      DBG_ATTN_BLOCK_RESULT_ATTN_TYPE);
7530
-	block_name = s_block_info_arr[results->block_id].name;
7310
+	attn_type = GET_FIELD(results->data, DBG_ATTN_BLOCK_RESULT_ATTN_TYPE);
7311
+	block_name = qed_dbg_get_block_name(p_hwfn, results->block_id);
7312
+	if (!block_name)
7313
+		return DBG_STATUS_INVALID_ARGS;
75317314 
7532
-	if (!s_user_dbg_arrays[BIN_BUF_DBG_ATTN_INDEXES].ptr ||
7533
-	    !s_user_dbg_arrays[BIN_BUF_DBG_ATTN_NAME_OFFSETS].ptr ||
7534
-	    !s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr)
7315
+	if (!p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_INDEXES].ptr ||
7316
+	    !p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_NAME_OFFSETS].ptr ||
7317
+	    !p_hwfn->dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr)
75357318 		return DBG_STATUS_DBG_ARRAY_NOT_SET;
75367319 
7537
-	block_attn = &s_user_dbg_arrays[BIN_BUF_DBG_ATTN_NAME_OFFSETS];
7538
-	block_attn_name_offsets = &block_attn->ptr[results->names_offset];
7320
+	block_attn_name_offsets =
7321
+	    (u32 *)p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_NAME_OFFSETS].ptr +
7322
+	    results->names_offset;
7323
+
7324
+	attn_name_base = p_hwfn->dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr;
75397325 
75407326 	/* Go over registers with a non-zero attention status */
75417327 	for (i = 0; i < num_regs; i++) {
....@@ -7546,18 +7332,17 @@
75467332 		reg_result = &results->reg_results[i];
75477333 		num_reg_attn = GET_FIELD(reg_result->data,
75487334 					 DBG_ATTN_REG_RESULT_NUM_REG_ATTN);
7549
-		block_attn = &s_user_dbg_arrays[BIN_BUF_DBG_ATTN_INDEXES];
7550
-		bit_mapping = &((struct dbg_attn_bit_mapping *)
7551
-				block_attn->ptr)[reg_result->block_attn_offset];
7552
-
7553
-		pstrings = &s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS];
7335
+		bit_mapping = (struct dbg_attn_bit_mapping *)
7336
+		    p_hwfn->dbg_arrays[BIN_BUF_DBG_ATTN_INDEXES].ptr +
7337
+		    reg_result->block_attn_offset;
75547338 
75557339 		/* Go over attention status bits */
7556
-		for (j = 0; j < num_reg_attn; j++) {
7340
+		for (j = 0; j < num_reg_attn; j++, bit_idx++) {
75577341 			u16 attn_idx_val = GET_FIELD(bit_mapping[j].data,
75587342 						     DBG_ATTN_BIT_MAPPING_VAL);
75597343 			const char *attn_name, *attn_type_str, *masked_str;
7560
-			u32 attn_name_offset, sts_addr;
7344
+			u32 attn_name_offset;
7345
+			u32 sts_addr;
75617346 
75627347 			/* Check if bit mask should be advanced (due to unused
75637348 			 * bits).
....@@ -7569,18 +7354,19 @@
75697354 			}
75707355 
75717356 			/* Check current bit index */
7572
-			if (!(reg_result->sts_val & BIT(bit_idx))) {
7573
-				bit_idx++;
7357
+			if (!(reg_result->sts_val & BIT(bit_idx)))
75747358 				continue;
7575
-			}
75767359 
7577
-			/* Find attention name */
7360
+			/* An attention bit with value=1 was found
7361
+			 * Find attention name
7362
+			 */
75787363 			attn_name_offset =
75797364 				block_attn_name_offsets[attn_idx_val];
7580
-			attn_name = &((const char *)
7581
-				      pstrings->ptr)[attn_name_offset];
7582
-			attn_type_str = attn_type == ATTN_TYPE_INTERRUPT ?
7583
-					"Interrupt" : "Parity";
7365
+			attn_name = attn_name_base + attn_name_offset;
7366
+			attn_type_str =
7367
+				(attn_type ==
7368
+				 ATTN_TYPE_INTERRUPT ? "Interrupt" :
7369
+				 "Parity");
75847370 			masked_str = reg_result->mask_val & BIT(bit_idx) ?
75857371 				     " [masked]" : "";
75867372 			sts_addr = GET_FIELD(reg_result->data,
....@@ -7588,14 +7374,14 @@
75887374 			DP_NOTICE(p_hwfn,
75897375 				  "%s (%s) : %s [address 0x%08x, bit %d]%s\n",
75907376 				  block_name, attn_type_str, attn_name,
7591
-				  sts_addr, bit_idx, masked_str);
7592
-
7593
-			bit_idx++;
7377
+				  sts_addr * 4, bit_idx, masked_str);
75947378 		}
75957379 	}
75967380 
75977381 	return DBG_STATUS_OK;
75987382 }
7383
+
7384
+static DEFINE_MUTEX(qed_dbg_lock);
75997385 
76007386 /* Wrapper for unifying the idle_chk and mcp_trace api */
76017387 static enum dbg_status
....@@ -7656,7 +7442,10 @@
76567442 		    qed_dbg_fw_asserts_get_dump_buf_size,
76577443 		    qed_dbg_fw_asserts_dump,
76587444 		    qed_print_fw_asserts_results,
7659
-		    qed_get_fw_asserts_results_buf_size},};
7445
+		    qed_get_fw_asserts_results_buf_size}, {
7446
+	"ilt",
7447
+		    qed_dbg_ilt_get_dump_buf_size,
7448
+		    qed_dbg_ilt_dump, NULL, NULL},};
76607449 
76617450 static void qed_dbg_print_feature(u8 *p_text_buf, u32 text_size)
76627451 {
....@@ -7677,7 +7466,7 @@
76777466 				      enum qed_dbg_features feature_idx)
76787467 {
76797468 	struct qed_dbg_feature *feature =
7680
-	    &p_hwfn->cdev->dbg_params.features[feature_idx];
7469
+	    &p_hwfn->cdev->dbg_features[feature_idx];
76817470 	u32 text_size_bytes, null_char_pos, i;
76827471 	enum dbg_status rc;
76837472 	char *text_buf;
....@@ -7726,8 +7515,14 @@
77267515 		text_buf[i] = '\n';
77277516 
77287517 	/* Dump printable feature to log */
7729
-	if (p_hwfn->cdev->dbg_params.print_data)
7518
+	if (p_hwfn->cdev->print_dbg_data)
77307519 		qed_dbg_print_feature(text_buf, text_size_bytes);
7520
+
7521
+	/* Just return the original binary buffer if requested */
7522
+	if (p_hwfn->cdev->dbg_bin_dump) {
7523
+		vfree(text_buf);
7524
+		return DBG_STATUS_OK;
7525
+	}
77317526 
77327527 	/* Free the old dump_buf and point the dump_buf to the newly allocagted
77337528 	 * and formatted text buffer.
....@@ -7739,13 +7534,15 @@
77397534 	return rc;
77407535 }
77417536 
7537
+#define MAX_DBG_FEATURE_SIZE_DWORDS	0x3FFFFFFF
7538
+
77427539 /* Generic function for performing the dump of a debug feature. */
77437540 static enum dbg_status qed_dbg_dump(struct qed_hwfn *p_hwfn,
77447541 				    struct qed_ptt *p_ptt,
77457542 				    enum qed_dbg_features feature_idx)
77467543 {
77477544 	struct qed_dbg_feature *feature =
7748
-	    &p_hwfn->cdev->dbg_params.features[feature_idx];
7545
+	    &p_hwfn->cdev->dbg_features[feature_idx];
77497546 	u32 buf_size_dwords;
77507547 	enum dbg_status rc;
77517548 
....@@ -7768,6 +7565,17 @@
77687565 						       &buf_size_dwords);
77697566 	if (rc != DBG_STATUS_OK && rc != DBG_STATUS_NVRAM_GET_IMAGE_FAILED)
77707567 		return rc;
7568
+
7569
+	if (buf_size_dwords > MAX_DBG_FEATURE_SIZE_DWORDS) {
7570
+		feature->buf_size = 0;
7571
+		DP_NOTICE(p_hwfn->cdev,
7572
+			  "Debug feature [\"%s\"] size (0x%x dwords) exceeds maximum size (0x%x dwords)\n",
7573
+			  qed_features_lookup[feature_idx].name,
7574
+			  buf_size_dwords, MAX_DBG_FEATURE_SIZE_DWORDS);
7575
+
7576
+		return DBG_STATUS_OK;
7577
+	}
7578
+
77717579 	feature->buf_size = buf_size_dwords * sizeof(u32);
77727580 	feature->dump_buf = vmalloc(feature->buf_size);
77737581 	if (!feature->dump_buf)
....@@ -7859,9 +7667,8 @@
78597667 			     enum qed_nvm_images image_id)
78607668 {
78617669 	struct qed_hwfn *p_hwfn =
7862
-		&cdev->hwfns[cdev->dbg_params.engine_for_debug];
7863
-	u32 len_rounded, i;
7864
-	__be32 val;
7670
+		&cdev->hwfns[cdev->engine_for_debug];
7671
+	u32 len_rounded;
78657672 	int rc;
78667673 
78677674 	*num_dumped_bytes = 0;
....@@ -7880,10 +7687,9 @@
78807687 
78817688 	/* QED_NVM_IMAGE_NVM_META image is not swapped like other images */
78827689 	if (image_id != QED_NVM_IMAGE_NVM_META)
7883
-		for (i = 0; i < len_rounded; i += 4) {
7884
-			val = cpu_to_be32(*(u32 *)(buffer + i));
7885
-			*(u32 *)(buffer + i) = val;
7886
-		}
7690
+		cpu_to_be32_array((__force __be32 *)buffer,
7691
+				  (const u32 *)buffer,
7692
+				  len_rounded / sizeof(u32));
78877693 
78887694 	*num_dumped_bytes = len_rounded;
78897695 
....@@ -7914,6 +7720,16 @@
79147720 	return qed_dbg_feature_size(cdev, DBG_FEATURE_FW_ASSERTS);
79157721 }
79167722 
7723
+int qed_dbg_ilt(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes)
7724
+{
7725
+	return qed_dbg_feature(cdev, buffer, DBG_FEATURE_ILT, num_dumped_bytes);
7726
+}
7727
+
7728
+int qed_dbg_ilt_size(struct qed_dev *cdev)
7729
+{
7730
+	return qed_dbg_feature_size(cdev, DBG_FEATURE_ILT);
7731
+}
7732
+
79177733 int qed_dbg_mcp_trace(struct qed_dev *cdev, void *buffer,
79187734 		      u32 *num_dumped_bytes)
79197735 {
....@@ -7930,9 +7746,19 @@
79307746  * feature buffer.
79317747  */
79327748 #define REGDUMP_HEADER_SIZE			sizeof(u32)
7749
+#define REGDUMP_HEADER_SIZE_SHIFT		0
7750
+#define REGDUMP_HEADER_SIZE_MASK		0xffffff
79337751 #define REGDUMP_HEADER_FEATURE_SHIFT		24
7934
-#define REGDUMP_HEADER_ENGINE_SHIFT		31
7752
+#define REGDUMP_HEADER_FEATURE_MASK		0x1f
7753
+#define REGDUMP_HEADER_BIN_DUMP_SHIFT		29
7754
+#define REGDUMP_HEADER_BIN_DUMP_MASK		0x1
79357755 #define REGDUMP_HEADER_OMIT_ENGINE_SHIFT	30
7756
+#define REGDUMP_HEADER_OMIT_ENGINE_MASK		0x1
7757
+#define REGDUMP_HEADER_ENGINE_SHIFT		31
7758
+#define REGDUMP_HEADER_ENGINE_MASK		0x1
7759
+#define REGDUMP_MAX_SIZE			0x1000000
7760
+#define ILT_DUMP_MAX_SIZE			(1024 * 1024 * 15)
7761
+
79367762 enum debug_print_features {
79377763 	OLD_MODE = 0,
79387764 	IDLE_CHK = 1,
....@@ -7946,27 +7772,48 @@
79467772 	NVM_CFG1 = 9,
79477773 	DEFAULT_CFG = 10,
79487774 	NVM_META = 11,
7775
+	MDUMP = 12,
7776
+	ILT_DUMP = 13,
79497777 };
79507778 
7951
-static u32 qed_calc_regdump_header(enum debug_print_features feature,
7779
+static u32 qed_calc_regdump_header(struct qed_dev *cdev,
7780
+				   enum debug_print_features feature,
79527781 				   int engine, u32 feature_size, u8 omit_engine)
79537782 {
7954
-	/* Insert the engine, feature and mode inside the header and combine it
7955
-	 * with feature size.
7956
-	 */
7957
-	return feature_size | (feature << REGDUMP_HEADER_FEATURE_SHIFT) |
7958
-	       (omit_engine << REGDUMP_HEADER_OMIT_ENGINE_SHIFT) |
7959
-	       (engine << REGDUMP_HEADER_ENGINE_SHIFT);
7783
+	u32 res = 0;
7784
+
7785
+	SET_FIELD(res, REGDUMP_HEADER_SIZE, feature_size);
7786
+	if (res != feature_size)
7787
+		DP_NOTICE(cdev,
7788
+			  "Feature %d is too large (size 0x%x) and will corrupt the dump\n",
7789
+			  feature, feature_size);
7790
+
7791
+	SET_FIELD(res, REGDUMP_HEADER_FEATURE, feature);
7792
+	SET_FIELD(res, REGDUMP_HEADER_BIN_DUMP, 1);
7793
+	SET_FIELD(res, REGDUMP_HEADER_OMIT_ENGINE, omit_engine);
7794
+	SET_FIELD(res, REGDUMP_HEADER_ENGINE, engine);
7795
+
7796
+	return res;
79607797 }
79617798 
79627799 int qed_dbg_all_data(struct qed_dev *cdev, void *buffer)
79637800 {
79647801 	u8 cur_engine, omit_engine = 0, org_engine;
7802
+	struct qed_hwfn *p_hwfn =
7803
+		&cdev->hwfns[cdev->engine_for_debug];
7804
+	struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
7805
+	int grc_params[MAX_DBG_GRC_PARAMS], i;
79657806 	u32 offset = 0, feature_size;
79667807 	int rc;
79677808 
7968
-	if (cdev->num_hwfns == 1)
7809
+	for (i = 0; i < MAX_DBG_GRC_PARAMS; i++)
7810
+		grc_params[i] = dev_data->grc.param_val[i];
7811
+
7812
+	if (!QED_IS_CMT(cdev))
79697813 		omit_engine = 1;
7814
+
7815
+	mutex_lock(&qed_dbg_lock);
7816
+	cdev->dbg_bin_dump = true;
79707817 
79717818 	org_engine = qed_get_debug_engine(cdev);
79727819 	for (cur_engine = 0; cur_engine < cdev->num_hwfns; cur_engine++) {
....@@ -7980,7 +7827,7 @@
79807827 				      REGDUMP_HEADER_SIZE, &feature_size);
79817828 		if (!rc) {
79827829 			*(u32 *)((u8 *)buffer + offset) =
7983
-			    qed_calc_regdump_header(IDLE_CHK, cur_engine,
7830
+			    qed_calc_regdump_header(cdev, IDLE_CHK, cur_engine,
79847831 						    feature_size, omit_engine);
79857832 			offset += (feature_size + REGDUMP_HEADER_SIZE);
79867833 		} else {
....@@ -7992,7 +7839,7 @@
79927839 				      REGDUMP_HEADER_SIZE, &feature_size);
79937840 		if (!rc) {
79947841 			*(u32 *)((u8 *)buffer + offset) =
7995
-			    qed_calc_regdump_header(IDLE_CHK, cur_engine,
7842
+			    qed_calc_regdump_header(cdev, IDLE_CHK, cur_engine,
79967843 						    feature_size, omit_engine);
79977844 			offset += (feature_size + REGDUMP_HEADER_SIZE);
79987845 		} else {
....@@ -8004,7 +7851,7 @@
80047851 				      REGDUMP_HEADER_SIZE, &feature_size);
80057852 		if (!rc) {
80067853 			*(u32 *)((u8 *)buffer + offset) =
8007
-			    qed_calc_regdump_header(REG_FIFO, cur_engine,
7854
+			    qed_calc_regdump_header(cdev, REG_FIFO, cur_engine,
80087855 						    feature_size, omit_engine);
80097856 			offset += (feature_size + REGDUMP_HEADER_SIZE);
80107857 		} else {
....@@ -8016,7 +7863,7 @@
80167863 				      REGDUMP_HEADER_SIZE, &feature_size);
80177864 		if (!rc) {
80187865 			*(u32 *)((u8 *)buffer + offset) =
8019
-			    qed_calc_regdump_header(IGU_FIFO, cur_engine,
7866
+			    qed_calc_regdump_header(cdev, IGU_FIFO, cur_engine,
80207867 						    feature_size, omit_engine);
80217868 			offset += (feature_size + REGDUMP_HEADER_SIZE);
80227869 		} else {
....@@ -8029,7 +7876,7 @@
80297876 						 &feature_size);
80307877 		if (!rc) {
80317878 			*(u32 *)((u8 *)buffer + offset) =
8032
-			    qed_calc_regdump_header(PROTECTION_OVERRIDE,
7879
+			    qed_calc_regdump_header(cdev, PROTECTION_OVERRIDE,
80337880 						    cur_engine,
80347881 						    feature_size, omit_engine);
80357882 			offset += (feature_size + REGDUMP_HEADER_SIZE);
....@@ -8044,22 +7891,45 @@
80447891 					REGDUMP_HEADER_SIZE, &feature_size);
80457892 		if (!rc) {
80467893 			*(u32 *)((u8 *)buffer + offset) =
8047
-			    qed_calc_regdump_header(FW_ASSERTS, cur_engine,
8048
-						    feature_size, omit_engine);
7894
+			    qed_calc_regdump_header(cdev, FW_ASSERTS,
7895
+						    cur_engine, feature_size,
7896
+						    omit_engine);
80497897 			offset += (feature_size + REGDUMP_HEADER_SIZE);
80507898 		} else {
80517899 			DP_ERR(cdev, "qed_dbg_fw_asserts failed. rc = %d\n",
80527900 			       rc);
80537901 		}
80547902 
7903
+		feature_size = qed_dbg_ilt_size(cdev);
7904
+		if (!cdev->disable_ilt_dump &&
7905
+		    feature_size < ILT_DUMP_MAX_SIZE) {
7906
+			rc = qed_dbg_ilt(cdev, (u8 *)buffer + offset +
7907
+					 REGDUMP_HEADER_SIZE, &feature_size);
7908
+			if (!rc) {
7909
+				*(u32 *)((u8 *)buffer + offset) =
7910
+				    qed_calc_regdump_header(cdev, ILT_DUMP,
7911
+							    cur_engine,
7912
+							    feature_size,
7913
+							    omit_engine);
7914
+				offset += feature_size + REGDUMP_HEADER_SIZE;
7915
+			} else {
7916
+				DP_ERR(cdev, "qed_dbg_ilt failed. rc = %d\n",
7917
+				       rc);
7918
+			}
7919
+		}
7920
+
80557921 		/* GRC dump - must be last because when mcp stuck it will
80567922 		 * clutter idle_chk, reg_fifo, ...
80577923 		 */
7924
+		for (i = 0; i < MAX_DBG_GRC_PARAMS; i++)
7925
+			dev_data->grc.param_val[i] = grc_params[i];
7926
+
80587927 		rc = qed_dbg_grc(cdev, (u8 *)buffer + offset +
80597928 				 REGDUMP_HEADER_SIZE, &feature_size);
80607929 		if (!rc) {
80617930 			*(u32 *)((u8 *)buffer + offset) =
8062
-			    qed_calc_regdump_header(GRC_DUMP, cur_engine,
7931
+			    qed_calc_regdump_header(cdev, GRC_DUMP,
7932
+						    cur_engine,
80637933 						    feature_size, omit_engine);
80647934 			offset += (feature_size + REGDUMP_HEADER_SIZE);
80657935 		} else {
....@@ -8068,25 +7938,31 @@
80687938 	}
80697939 
80707940 	qed_set_debug_engine(cdev, org_engine);
7941
+
80717942 	/* mcp_trace */
80727943 	rc = qed_dbg_mcp_trace(cdev, (u8 *)buffer + offset +
80737944 			       REGDUMP_HEADER_SIZE, &feature_size);
80747945 	if (!rc) {
80757946 		*(u32 *)((u8 *)buffer + offset) =
8076
-		    qed_calc_regdump_header(MCP_TRACE, cur_engine,
7947
+		    qed_calc_regdump_header(cdev, MCP_TRACE, cur_engine,
80777948 					    feature_size, omit_engine);
80787949 		offset += (feature_size + REGDUMP_HEADER_SIZE);
80797950 	} else {
80807951 		DP_ERR(cdev, "qed_dbg_mcp_trace failed. rc = %d\n", rc);
80817952 	}
80827953 
7954
+	/* Re-populate nvm attribute info */
7955
+	qed_mcp_nvm_info_free(p_hwfn);
7956
+	qed_mcp_nvm_info_populate(p_hwfn);
7957
+
80837958 	/* nvm cfg1 */
80847959 	rc = qed_dbg_nvm_image(cdev,
8085
-			       (u8 *)buffer + offset + REGDUMP_HEADER_SIZE,
8086
-			       &feature_size, QED_NVM_IMAGE_NVM_CFG1);
7960
+			       (u8 *)buffer + offset +
7961
+			       REGDUMP_HEADER_SIZE, &feature_size,
7962
+			       QED_NVM_IMAGE_NVM_CFG1);
80877963 	if (!rc) {
80887964 		*(u32 *)((u8 *)buffer + offset) =
8089
-		    qed_calc_regdump_header(NVM_CFG1, cur_engine,
7965
+		    qed_calc_regdump_header(cdev, NVM_CFG1, cur_engine,
80907966 					    feature_size, omit_engine);
80917967 		offset += (feature_size + REGDUMP_HEADER_SIZE);
80927968 	} else if (rc != -ENOENT) {
....@@ -8101,7 +7977,7 @@
81017977 			       &feature_size, QED_NVM_IMAGE_DEFAULT_CFG);
81027978 	if (!rc) {
81037979 		*(u32 *)((u8 *)buffer + offset) =
8104
-		    qed_calc_regdump_header(DEFAULT_CFG, cur_engine,
7980
+		    qed_calc_regdump_header(cdev, DEFAULT_CFG, cur_engine,
81057981 					    feature_size, omit_engine);
81067982 		offset += (feature_size + REGDUMP_HEADER_SIZE);
81077983 	} else if (rc != -ENOENT) {
....@@ -8117,8 +7993,8 @@
81177993 			       &feature_size, QED_NVM_IMAGE_NVM_META);
81187994 	if (!rc) {
81197995 		*(u32 *)((u8 *)buffer + offset) =
8120
-		    qed_calc_regdump_header(NVM_META, cur_engine,
8121
-					    feature_size, omit_engine);
7996
+			qed_calc_regdump_header(cdev, NVM_META, cur_engine,
7997
+						feature_size, omit_engine);
81227998 		offset += (feature_size + REGDUMP_HEADER_SIZE);
81237999 	} else if (rc != -ENOENT) {
81248000 		DP_ERR(cdev,
....@@ -8126,16 +8002,35 @@
81268002 		       QED_NVM_IMAGE_NVM_META, "QED_NVM_IMAGE_NVM_META", rc);
81278003 	}
81288004 
8005
+	/* nvm mdump */
8006
+	rc = qed_dbg_nvm_image(cdev, (u8 *)buffer + offset +
8007
+			       REGDUMP_HEADER_SIZE, &feature_size,
8008
+			       QED_NVM_IMAGE_MDUMP);
8009
+	if (!rc) {
8010
+		*(u32 *)((u8 *)buffer + offset) =
8011
+			qed_calc_regdump_header(cdev, MDUMP, cur_engine,
8012
+						feature_size, omit_engine);
8013
+		offset += (feature_size + REGDUMP_HEADER_SIZE);
8014
+	} else if (rc != -ENOENT) {
8015
+		DP_ERR(cdev,
8016
+		       "qed_dbg_nvm_image failed for image %d (%s), rc = %d\n",
8017
+		       QED_NVM_IMAGE_MDUMP, "QED_NVM_IMAGE_MDUMP", rc);
8018
+	}
8019
+
8020
+	cdev->dbg_bin_dump = false;
8021
+	mutex_unlock(&qed_dbg_lock);
8022
+
81298023 	return 0;
81308024 }
81318025 
81328026 int qed_dbg_all_data_size(struct qed_dev *cdev)
81338027 {
81348028 	struct qed_hwfn *p_hwfn =
8135
-		&cdev->hwfns[cdev->dbg_params.engine_for_debug];
8136
-	u32 regs_len = 0, image_len = 0;
8029
+		&cdev->hwfns[cdev->engine_for_debug];
8030
+	u32 regs_len = 0, image_len = 0, ilt_len = 0, total_ilt_len = 0;
81378031 	u8 cur_engine, org_engine;
81388032 
8033
+	cdev->disable_ilt_dump = false;
81398034 	org_engine = qed_get_debug_engine(cdev);
81408035 	for (cur_engine = 0; cur_engine < cdev->num_hwfns; cur_engine++) {
81418036 		/* Engine specific */
....@@ -8150,6 +8045,12 @@
81508045 			    REGDUMP_HEADER_SIZE +
81518046 			    qed_dbg_protection_override_size(cdev) +
81528047 			    REGDUMP_HEADER_SIZE + qed_dbg_fw_asserts_size(cdev);
8048
+
8049
+		ilt_len = REGDUMP_HEADER_SIZE + qed_dbg_ilt_size(cdev);
8050
+		if (ilt_len < ILT_DUMP_MAX_SIZE) {
8051
+			total_ilt_len += ilt_len;
8052
+			regs_len += ilt_len;
8053
+		}
81538054 	}
81548055 
81558056 	qed_set_debug_engine(cdev, org_engine);
....@@ -8165,6 +8066,17 @@
81658066 	qed_dbg_nvm_image_length(p_hwfn, QED_NVM_IMAGE_NVM_META, &image_len);
81668067 	if (image_len)
81678068 		regs_len += REGDUMP_HEADER_SIZE + image_len;
8069
+	qed_dbg_nvm_image_length(p_hwfn, QED_NVM_IMAGE_MDUMP, &image_len);
8070
+	if (image_len)
8071
+		regs_len += REGDUMP_HEADER_SIZE + image_len;
8072
+
8073
+	if (regs_len > REGDUMP_MAX_SIZE) {
8074
+		DP_VERBOSE(cdev, QED_MSG_DEBUG,
8075
+			   "Dump exceeds max size 0x%x, disable ILT dump\n",
8076
+			   REGDUMP_MAX_SIZE);
8077
+		cdev->disable_ilt_dump = true;
8078
+		regs_len -= total_ilt_len;
8079
+	}
81688080 
81698081 	return regs_len;
81708082 }
....@@ -8173,9 +8085,9 @@
81738085 		    enum qed_dbg_features feature, u32 *num_dumped_bytes)
81748086 {
81758087 	struct qed_hwfn *p_hwfn =
8176
-		&cdev->hwfns[cdev->dbg_params.engine_for_debug];
8088
+		&cdev->hwfns[cdev->engine_for_debug];
81778089 	struct qed_dbg_feature *qed_feature =
8178
-		&cdev->dbg_params.features[feature];
8090
+		&cdev->dbg_features[feature];
81798091 	enum dbg_status dbg_rc;
81808092 	struct qed_ptt *p_ptt;
81818093 	int rc = 0;
....@@ -8198,7 +8110,7 @@
81988110 	DP_VERBOSE(cdev, QED_MSG_DEBUG,
81998111 		   "copying debugfs feature to external buffer\n");
82008112 	memcpy(buffer, qed_feature->dump_buf, qed_feature->buf_size);
8201
-	*num_dumped_bytes = cdev->dbg_params.features[feature].dumped_dwords *
8113
+	*num_dumped_bytes = cdev->dbg_features[feature].dumped_dwords *
82028114 			    4;
82038115 
82048116 out:
....@@ -8209,10 +8121,9 @@
82098121 int qed_dbg_feature_size(struct qed_dev *cdev, enum qed_dbg_features feature)
82108122 {
82118123 	struct qed_hwfn *p_hwfn =
8212
-		&cdev->hwfns[cdev->dbg_params.engine_for_debug];
8124
+		&cdev->hwfns[cdev->engine_for_debug];
8125
+	struct qed_dbg_feature *qed_feature = &cdev->dbg_features[feature];
82138126 	struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
8214
-	struct qed_dbg_feature *qed_feature =
8215
-		&cdev->dbg_params.features[feature];
82168127 	u32 buf_size_dwords;
82178128 	enum dbg_status rc;
82188129 
....@@ -8224,6 +8135,10 @@
82248135 	if (rc != DBG_STATUS_OK)
82258136 		buf_size_dwords = 0;
82268137 
8138
+	/* Feature will not be dumped if it exceeds maximum size */
8139
+	if (buf_size_dwords > MAX_DBG_FEATURE_SIZE_DWORDS)
8140
+		buf_size_dwords = 0;
8141
+
82278142 	qed_ptt_release(p_hwfn, p_ptt);
82288143 	qed_feature->buf_size = buf_size_dwords * sizeof(u32);
82298144 	return qed_feature->buf_size;
....@@ -8231,26 +8146,33 @@
82318146 
82328147 u8 qed_get_debug_engine(struct qed_dev *cdev)
82338148 {
8234
-	return cdev->dbg_params.engine_for_debug;
8149
+	return cdev->engine_for_debug;
82358150 }
82368151 
82378152 void qed_set_debug_engine(struct qed_dev *cdev, int engine_number)
82388153 {
82398154 	DP_VERBOSE(cdev, QED_MSG_DEBUG, "set debug engine to %d\n",
82408155 		   engine_number);
8241
-	cdev->dbg_params.engine_for_debug = engine_number;
8156
+	cdev->engine_for_debug = engine_number;
82428157 }
82438158 
82448159 void qed_dbg_pf_init(struct qed_dev *cdev)
82458160 {
8246
-	const u8 *dbg_values;
8161
+	const u8 *dbg_values = NULL;
8162
+	int i;
82478163 
82488164 	/* Debug values are after init values.
82498165 	 * The offset is the first dword of the file.
82508166 	 */
82518167 	dbg_values = cdev->firmware->data + *(u32 *)cdev->firmware->data;
8252
-	qed_dbg_set_bin_ptr((u8 *)dbg_values);
8253
-	qed_dbg_user_set_bin_ptr((u8 *)dbg_values);
8168
+
8169
+	for_each_hwfn(cdev, i) {
8170
+		qed_dbg_set_bin_ptr(&cdev->hwfns[i], dbg_values);
8171
+		qed_dbg_user_set_bin_ptr(&cdev->hwfns[i], dbg_values);
8172
+	}
8173
+
8174
+	/* Set the hwfn to be 0 as default */
8175
+	cdev->engine_for_debug = 0;
82548176 }
82558177 
82568178 void qed_dbg_pf_exit(struct qed_dev *cdev)
....@@ -8258,11 +8180,11 @@
82588180 	struct qed_dbg_feature *feature = NULL;
82598181 	enum qed_dbg_features feature_idx;
82608182 
8261
-	/* Debug features' buffers may be allocated if debug feature was used
8262
-	 * but dump wasn't called.
8183
+	/* debug features' buffers may be allocated if debug feature was used
8184
+	 * but dump wasn't called
82638185 	 */
82648186 	for (feature_idx = 0; feature_idx < DBG_FEATURE_NUM; feature_idx++) {
8265
-		feature = &cdev->dbg_params.features[feature_idx];
8187
+		feature = &cdev->dbg_features[feature_idx];
82668188 		if (feature->dump_buf) {
82678189 			vfree(feature->dump_buf);
82688190 			feature->dump_buf = NULL;