~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,33 +1,7 @@
	1	+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
1	2	/* QLogic qed NIC Driver
2	3	* Copyright (c) 2015-2017 QLogic Corporation
3		- *
4		- * This software is available to you under a choice of one of two
5		- * licenses. You may choose to be licensed under the terms of the GNU
6		- * General Public License (GPL) Version 2, available from the file
7		- * COPYING in the main directory of this source tree, or the
8		- * OpenIB.org BSD license below:
9		- *
10		- * Redistribution and use in source and binary forms, with or
11		- * without modification, are permitted provided that the following
12		- * conditions are met:
13		- *
14		- * - Redistributions of source code must retain the above
15		- * copyright notice, this list of conditions and the following
16		- * disclaimer.
17		- *
18		- * - Redistributions in binary form must reproduce the above
19		- * copyright notice, this list of conditions and the following
20		- * disclaimer in the documentation and /or other materials
21		- * provided with the distribution.
22		- *
23		- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24		- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25		- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26		- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27		- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28		- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29		- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30		- * SOFTWARE.
	4	+ * Copyright (c) 2019-2020 Marvell International Ltd.
31	5	*/
32	6
33	7	#include <linux/types.h>
..	..	@@ -40,7 +14,6 @@
40	14	#include <linux/pci.h>
41	15	#include <linux/slab.h>
42	16	#include <linux/string.h>
43		-#include <linux/bitops.h>
44	17	#include "qed.h"
45	18	#include "qed_cxt.h"
46	19	#include "qed_dev_api.h"
..	..	@@ -50,12 +23,6 @@
50	23	#include "qed_rdma.h"
51	24	#include "qed_reg_addr.h"
52	25	#include "qed_sriov.h"
53		-
54		-/* Max number of connection types in HW (DQ/CDU etc.) */
55		-#define MAX_CONN_TYPES PROTOCOLID_COMMON
56		-#define NUM_TASK_TYPES 2
57		-#define NUM_TASK_PF_SEGMENTS 4
58		-#define NUM_TASK_VF_SEGMENTS 1
59	26
60	27	/* QM constants */
61	28	#define QM_PQ_ELEMENT_SIZE 4 /* in bytes */
..	..	@@ -106,8 +73,8 @@
106	73	};
107	74
108	75	struct src_ent {
109		- u8 opaque[56];
110		- u64 next;
	76	+ __u8 opaque[56];
	77	+ __be64 next;
111	78	};
112	79
113	80	#define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
..	..	@@ -117,6 +84,7 @@
117	84	ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
118	85
119	86	#define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context))
	87	+#define XRC_SRQ_CXT_SIZE (sizeof(struct rdma_xrc_srq_context))
120	88
121	89	#define TYPE0_TASK_CXT_SIZE(p_hwfn) \
122	90	ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
..	..	@@ -124,126 +92,6 @@
124	92	/* Alignment is inherent to the type1_task_context structure */
125	93	#define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
126	94
127		-/* PF per protocl configuration object */
128		-#define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
129		-#define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
130		-
131		-struct qed_tid_seg {
132		- u32 count;
133		- u8 type;
134		- bool has_fl_mem;
135		-};
136		-
137		-struct qed_conn_type_cfg {
138		- u32 cid_count;
139		- u32 cids_per_vf;
140		- struct qed_tid_seg tid_seg[TASK_SEGMENTS];
141		-};
142		-
143		-/* ILT Client configuration, Per connection type (protocol) resources. */
144		-#define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2)
145		-#define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2)
146		-#define CDUC_BLK (0)
147		-#define SRQ_BLK (0)
148		-#define CDUT_SEG_BLK(n) (1 + (u8)(n))
149		-#define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_ ## X ## _SEGMENTS)
150		-
151		-enum ilt_clients {
152		- ILT_CLI_CDUC,
153		- ILT_CLI_CDUT,
154		- ILT_CLI_QM,
155		- ILT_CLI_TM,
156		- ILT_CLI_SRC,
157		- ILT_CLI_TSDM,
158		- ILT_CLI_MAX
159		-};
160		-
161		-struct ilt_cfg_pair {
162		- u32 reg;
163		- u32 val;
164		-};
165		-
166		-struct qed_ilt_cli_blk {
167		- u32 total_size; /* 0 means not active */
168		- u32 real_size_in_page;
169		- u32 start_line;
170		- u32 dynamic_line_cnt;
171		-};
172		-
173		-struct qed_ilt_client_cfg {
174		- bool active;
175		-
176		- /* ILT boundaries */
177		- struct ilt_cfg_pair first;
178		- struct ilt_cfg_pair last;
179		- struct ilt_cfg_pair p_size;
180		-
181		- /* ILT client blocks for PF */
182		- struct qed_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];
183		- u32 pf_total_lines;
184		-
185		- /* ILT client blocks for VFs */
186		- struct qed_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];
187		- u32 vf_total_lines;
188		-};
189		-
190		-/* Per Path -
191		- * ILT shadow table
192		- * Protocol acquired CID lists
193		- * PF start line in ILT
194		- */
195		-struct qed_dma_mem {
196		- dma_addr_t p_phys;
197		- void *p_virt;
198		- size_t size;
199		-};
200		-
201		-struct qed_cid_acquired_map {
202		- u32 start_cid;
203		- u32 max_count;
204		- unsigned long *cid_map;
205		-};
206		-
207		-struct qed_cxt_mngr {
208		- /* Per protocl configuration */
209		- struct qed_conn_type_cfg conn_cfg[MAX_CONN_TYPES];
210		-
211		- /* computed ILT structure */
212		- struct qed_ilt_client_cfg clients[ILT_CLI_MAX];
213		-
214		- /* Task type sizes */
215		- u32 task_type_size[NUM_TASK_TYPES];
216		-
217		- /* total number of VFs for this hwfn -
218		- * ALL VFs are symmetric in terms of HW resources
219		- */
220		- u32 vf_count;
221		-
222		- /* Acquired CIDs */
223		- struct qed_cid_acquired_map acquired[MAX_CONN_TYPES];
224		-
225		- struct qed_cid_acquired_map
226		- acquired_vf[MAX_CONN_TYPES][MAX_NUM_VFS];
227		-
228		- /* ILT shadow table */
229		- struct qed_dma_mem *ilt_shadow;
230		- u32 pf_start_line;
231		-
232		- /* Mutex for a dynamic ILT allocation */
233		- struct mutex mutex;
234		-
235		- /* SRC T2 */
236		- struct qed_dma_mem *t2;
237		- u32 t2_num_pages;
238		- u64 first_free;
239		- u64 last_free;
240		-
241		- /* total number of SRQ's for this hwfn */
242		- u32 srq_count;
243		-
244		- /* Maximal number of L2 steering filters */
245		- u32 arfs_count;
246		-};
247	95	static bool src_proto(enum protocol_type type)
248	96	{
249	97	return type == PROTOCOLID_ISCSI \|\|
..	..	@@ -420,18 +268,40 @@
420	268	return NULL;
421	269	}
422	270
423		-static void qed_cxt_set_srq_count(struct qed_hwfn *p_hwfn, u32 num_srqs)
	271	+static void qed_cxt_set_srq_count(struct qed_hwfn *p_hwfn,
	272	+ u32 num_srqs, u32 num_xrc_srqs)
424	273	{
425	274	struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
426	275
427	276	p_mgr->srq_count = num_srqs;
	277	+ p_mgr->xrc_srq_count = num_xrc_srqs;
428	278	}
429	279
430		-u32 qed_cxt_get_srq_count(struct qed_hwfn *p_hwfn)
	280	+u32 qed_cxt_get_ilt_page_size(struct qed_hwfn *p_hwfn,
	281	+ enum ilt_clients ilt_client)
	282	+{
	283	+ struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
	284	+ struct qed_ilt_client_cfg *p_cli = &p_mngr->clients[ilt_client];
	285	+
	286	+ return ILT_PAGE_IN_BYTES(p_cli->p_size.val);
	287	+}
	288	+
	289	+static u32 qed_cxt_xrc_srqs_per_page(struct qed_hwfn *p_hwfn)
	290	+{
	291	+ u32 page_size;
	292	+
	293	+ page_size = qed_cxt_get_ilt_page_size(p_hwfn, ILT_CLI_TSDM);
	294	+ return page_size / XRC_SRQ_CXT_SIZE;
	295	+}
	296	+
	297	+u32 qed_cxt_get_total_srq_count(struct qed_hwfn *p_hwfn)
431	298	{
432	299	struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
	300	+ u32 total_srqs;
433	301
434		- return p_mgr->srq_count;
	302	+ total_srqs = p_mgr->srq_count + p_mgr->xrc_srq_count;
	303	+
	304	+ return total_srqs;
435	305	}
436	306
437	307	/* set the iids count per protocol */
..	..	@@ -569,6 +439,20 @@
569	439	return p_blk;
570	440	}
571	441
	442	+static void qed_cxt_ilt_blk_reset(struct qed_hwfn *p_hwfn)
	443	+{
	444	+ struct qed_ilt_client_cfg *clients = p_hwfn->p_cxt_mngr->clients;
	445	+ u32 cli_idx, blk_idx;
	446	+
	447	+ for (cli_idx = 0; cli_idx < MAX_ILT_CLIENTS; cli_idx++) {
	448	+ for (blk_idx = 0; blk_idx < ILT_CLI_PF_BLOCKS; blk_idx++)
	449	+ clients[cli_idx].pf_blks[blk_idx].total_size = 0;
	450	+
	451	+ for (blk_idx = 0; blk_idx < ILT_CLI_VF_BLOCKS; blk_idx++)
	452	+ clients[cli_idx].vf_blks[blk_idx].total_size = 0;
	453	+ }
	454	+}
	455	+
572	456	int qed_cxt_cfg_ilt_compute(struct qed_hwfn p_hwfn, u32 line_count)
573	457	{
574	458	struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
..	..	@@ -587,6 +471,11 @@
587	471	memset(&tm_iids, 0, sizeof(tm_iids));
588	472
589	473	p_mngr->pf_start_line = RESC_START(p_hwfn, QED_ILT);
	474	+
	475	+ /* Reset all ILT blocks at the beginning of ILT computing in order
	476	+ * to prevent memory allocation for irrelevant blocks afterwards.
	477	+ */
	478	+ qed_cxt_ilt_blk_reset(p_hwfn);
590	479
591	480	DP_VERBOSE(p_hwfn, QED_MSG_ILT,
592	481	"hwfn [%d] - Set context manager starting line to be 0x%08x\n",
..	..	@@ -819,7 +708,7 @@
819	708	}
820	709
821	710	/* TSDM (SRQ CONTEXT) */
822		- total = qed_cxt_get_srq_count(p_hwfn);
	711	+ total = qed_cxt_get_total_srq_count(p_hwfn);
823	712
824	713	if (total) {
825	714	p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_TSDM]);
..	..	@@ -881,30 +770,60 @@
881	770
882	771	static void qed_cxt_src_t2_free(struct qed_hwfn *p_hwfn)
883	772	{
884		- struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
	773	+ struct qed_src_t2 *p_t2 = &p_hwfn->p_cxt_mngr->src_t2;
885	774	u32 i;
886	775
887		- if (!p_mngr->t2)
	776	+ if (!p_t2 \|\| !p_t2->dma_mem)
888	777	return;
889	778
890		- for (i = 0; i < p_mngr->t2_num_pages; i++)
891		- if (p_mngr->t2[i].p_virt)
	779	+ for (i = 0; i < p_t2->num_pages; i++)
	780	+ if (p_t2->dma_mem[i].virt_addr)
892	781	dma_free_coherent(&p_hwfn->cdev->pdev->dev,
893		- p_mngr->t2[i].size,
894		- p_mngr->t2[i].p_virt,
895		- p_mngr->t2[i].p_phys);
	782	+ p_t2->dma_mem[i].size,
	783	+ p_t2->dma_mem[i].virt_addr,
	784	+ p_t2->dma_mem[i].phys_addr);
896	785
897		- kfree(p_mngr->t2);
898		- p_mngr->t2 = NULL;
	786	+ kfree(p_t2->dma_mem);
	787	+ p_t2->dma_mem = NULL;
	788	+}
	789	+
	790	+static int
	791	+qed_cxt_t2_alloc_pages(struct qed_hwfn *p_hwfn,
	792	+ struct qed_src_t2 *p_t2, u32 total_size, u32 page_size)
	793	+{
	794	+ void **p_virt;
	795	+ u32 size, i;
	796	+
	797	+ if (!p_t2 \|\| !p_t2->dma_mem)
	798	+ return -EINVAL;
	799	+
	800	+ for (i = 0; i < p_t2->num_pages; i++) {
	801	+ size = min_t(u32, total_size, page_size);
	802	+ p_virt = &p_t2->dma_mem[i].virt_addr;
	803	+
	804	+ *p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
	805	+ size,
	806	+ &p_t2->dma_mem[i].phys_addr,
	807	+ GFP_KERNEL);
	808	+ if (!p_t2->dma_mem[i].virt_addr)
	809	+ return -ENOMEM;
	810	+
	811	+ memset(*p_virt, 0, size);
	812	+ p_t2->dma_mem[i].size = size;
	813	+ total_size -= size;
	814	+ }
	815	+
	816	+ return 0;
899	817	}
900	818
901	819	static int qed_cxt_src_t2_alloc(struct qed_hwfn *p_hwfn)
902	820	{
903	821	struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
904	822	u32 conn_num, total_size, ent_per_page, psz, i;
	823	+ struct phys_mem_desc *p_t2_last_page;
905	824	struct qed_ilt_client_cfg *p_src;
906	825	struct qed_src_iids src_iids;
907		- struct qed_dma_mem *p_t2;
	826	+ struct qed_src_t2 *p_t2;
908	827	int rc;
909	828
910	829	memset(&src_iids, 0, sizeof(src_iids));
..	..	@@ -922,49 +841,39 @@
922	841
923	842	/* use the same page size as the SRC ILT client */
924	843	psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
925		- p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
	844	+ p_t2 = &p_mngr->src_t2;
	845	+ p_t2->num_pages = DIV_ROUND_UP(total_size, psz);
926	846
927	847	/* allocate t2 */
928		- p_mngr->t2 = kcalloc(p_mngr->t2_num_pages, sizeof(struct qed_dma_mem),
929		- GFP_KERNEL);
930		- if (!p_mngr->t2) {
	848	+ p_t2->dma_mem = kcalloc(p_t2->num_pages, sizeof(struct phys_mem_desc),
	849	+ GFP_KERNEL);
	850	+ if (!p_t2->dma_mem) {
	851	+ DP_NOTICE(p_hwfn, "Failed to allocate t2 table\n");
931	852	rc = -ENOMEM;
932	853	goto t2_fail;
933	854	}
934	855
935		- /* allocate t2 pages */
936		- for (i = 0; i < p_mngr->t2_num_pages; i++) {
937		- u32 size = min_t(u32, total_size, psz);
938		- void **p_virt = &p_mngr->t2[i].p_virt;
939		-
940		- *p_virt = dma_zalloc_coherent(&p_hwfn->cdev->pdev->dev,
941		- size, &p_mngr->t2[i].p_phys,
942		- GFP_KERNEL);
943		- if (!p_mngr->t2[i].p_virt) {
944		- rc = -ENOMEM;
945		- goto t2_fail;
946		- }
947		- p_mngr->t2[i].size = size;
948		- total_size -= size;
949		- }
	856	+ rc = qed_cxt_t2_alloc_pages(p_hwfn, p_t2, total_size, psz);
	857	+ if (rc)
	858	+ goto t2_fail;
950	859
951	860	/* Set the t2 pointers */
952	861
953	862	/* entries per page - must be a power of two */
954	863	ent_per_page = psz / sizeof(struct src_ent);
955	864
956		- p_mngr->first_free = (u64) p_mngr->t2[0].p_phys;
	865	+ p_t2->first_free = (u64)p_t2->dma_mem[0].phys_addr;
957	866
958		- p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
959		- p_mngr->last_free = (u64) p_t2->p_phys +
	867	+ p_t2_last_page = &p_t2->dma_mem[(conn_num - 1) / ent_per_page];
	868	+ p_t2->last_free = (u64)p_t2_last_page->phys_addr +
960	869	((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent);
961	870
962		- for (i = 0; i < p_mngr->t2_num_pages; i++) {
	871	+ for (i = 0; i < p_t2->num_pages; i++) {
963	872	u32 ent_num = min_t(u32,
964	873	ent_per_page,
965	874	conn_num);
966		- struct src_ent *entries = p_mngr->t2[i].p_virt;
967		- u64 p_ent_phys = (u64) p_mngr->t2[i].p_phys, val;
	875	+ struct src_ent *entries = p_t2->dma_mem[i].virt_addr;
	876	+ u64 p_ent_phys = (u64)p_t2->dma_mem[i].phys_addr, val;
968	877	u32 j;
969	878
970	879	for (j = 0; j < ent_num - 1; j++) {
..	..	@@ -972,8 +881,8 @@
972	881	entries[j].next = cpu_to_be64(val);
973	882	}
974	883
975		- if (i < p_mngr->t2_num_pages - 1)
976		- val = (u64) p_mngr->t2[i + 1].p_phys;
	884	+ if (i < p_t2->num_pages - 1)
	885	+ val = (u64)p_t2->dma_mem[i + 1].phys_addr;
977	886	else
978	887	val = 0;
979	888	entries[j].next = cpu_to_be64(val);
..	..	@@ -989,7 +898,7 @@
989	898	}
990	899
991	900	#define for_each_ilt_valid_client(pos, clients) \
992		- for (pos = 0; pos < ILT_CLI_MAX; pos++) \
	901	+ for (pos = 0; pos < MAX_ILT_CLIENTS; pos++) \
993	902	if (!clients[pos].active) { \
994	903	continue; \
995	904	} else \
..	..	@@ -1015,13 +924,13 @@
1015	924	ilt_size = qed_cxt_ilt_shadow_size(p_cli);
1016	925
1017	926	for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
1018		- struct qed_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
	927	+ struct phys_mem_desc *p_dma = &p_mngr->ilt_shadow[i];
1019	928
1020		- if (p_dma->p_virt)
	929	+ if (p_dma->virt_addr)
1021	930	dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1022		- p_dma->size, p_dma->p_virt,
1023		- p_dma->p_phys);
1024		- p_dma->p_virt = NULL;
	931	+ p_dma->size, p_dma->virt_addr,
	932	+ p_dma->phys_addr);
	933	+ p_dma->virt_addr = NULL;
1025	934	}
1026	935	kfree(p_mngr->ilt_shadow);
1027	936	}
..	..	@@ -1031,7 +940,7 @@
1031	940	enum ilt_clients ilt_client,
1032	941	u32 start_line_offset)
1033	942	{
1034		- struct qed_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
	943	+ struct phys_mem_desc *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
1035	944	u32 lines, line, sz_left, lines_to_skip = 0;
1036	945
1037	946	/* Special handling for RoCE that supports dynamic allocation */
..	..	@@ -1055,13 +964,13 @@
1055	964	u32 size;
1056	965
1057	966	size = min_t(u32, sz_left, p_blk->real_size_in_page);
1058		- p_virt = dma_zalloc_coherent(&p_hwfn->cdev->pdev->dev, size,
1059		- &p_phys, GFP_KERNEL);
	967	+ p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, size,
	968	+ &p_phys, GFP_KERNEL);
1060	969	if (!p_virt)
1061	970	return -ENOMEM;
1062	971
1063		- ilt_shadow[line].p_phys = p_phys;
1064		- ilt_shadow[line].p_virt = p_virt;
	972	+ ilt_shadow[line].phys_addr = p_phys;
	973	+ ilt_shadow[line].virt_addr = p_virt;
1065	974	ilt_shadow[line].size = size;
1066	975
1067	976	DP_VERBOSE(p_hwfn, QED_MSG_ILT,
..	..	@@ -1084,7 +993,7 @@
1084	993	int rc;
1085	994
1086	995	size = qed_cxt_ilt_shadow_size(clients);
1087		- p_mngr->ilt_shadow = kcalloc(size, sizeof(struct qed_dma_mem),
	996	+ p_mngr->ilt_shadow = kcalloc(size, sizeof(struct phys_mem_desc),
1088	997	GFP_KERNEL);
1089	998	if (!p_mngr->ilt_shadow) {
1090	999	rc = -ENOMEM;
..	..	@@ -1093,7 +1002,7 @@
1093	1002
1094	1003	DP_VERBOSE(p_hwfn, QED_MSG_ILT,
1095	1004	"Allocated 0x%x bytes for ilt shadow\n",
1096		- (u32)(size * sizeof(struct qed_dma_mem)));
	1005	+ (u32)(size * sizeof(struct phys_mem_desc)));
1097	1006
1098	1007	for_each_ilt_valid_client(i, clients) {
1099	1008	for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
..	..	@@ -1239,15 +1148,20 @@
1239	1148	clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
1240	1149	clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1241	1150	/* default ILT page size for all clients is 64K */
1242		- for (i = 0; i < ILT_CLI_MAX; i++)
	1151	+ for (i = 0; i < MAX_ILT_CLIENTS; i++)
1243	1152	p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
	1153	+
	1154	+ p_mngr->conn_ctx_size = CONN_CXT_SIZE(p_hwfn);
1244	1155
1245	1156	/* Initialize task sizes */
1246	1157	p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn);
1247	1158	p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn);
1248	1159
1249		- if (p_hwfn->cdev->p_iov_info)
	1160	+ if (p_hwfn->cdev->p_iov_info) {
1250	1161	p_mngr->vf_count = p_hwfn->cdev->p_iov_info->total_vfs;
	1162	+ p_mngr->first_vf_in_pf =
	1163	+ p_hwfn->cdev->p_iov_info->first_vf_in_pf;
	1164	+ }
1251	1165	/* Initialize the dynamic ILT allocation mutex */
1252	1166	mutex_init(&p_mngr->mutex);
1253	1167
..	..	@@ -1500,13 +1414,10 @@
1500	1414	{
1501	1415	struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1502	1416	struct qed_qm_pf_rt_init_params params;
1503		- struct qed_mcp_link_state *p_link;
1504	1417	struct qed_qm_iids iids;
1505	1418
1506	1419	memset(&iids, 0, sizeof(iids));
1507	1420	qed_cxt_qm_iids(p_hwfn, &iids);
1508		-
1509		- p_link = &QED_LEADING_HWFN(p_hwfn->cdev)->mcp_info->link_output;
1510	1421
1511	1422	memset(&params, 0, sizeof(params));
1512	1423	params.port_id = p_hwfn->port_id;
..	..	@@ -1523,7 +1434,6 @@
1523	1434	params.num_vports = qm_info->num_vports;
1524	1435	params.pf_wfq = qm_info->pf_wfq;
1525	1436	params.pf_rl = qm_info->pf_rl;
1526		- params.link_speed = p_link->speed;
1527	1437	params.pq_params = qm_info->qm_pq_params;
1528	1438	params.vport_params = qm_info->qm_vport_params;
1529	1439
..	..	@@ -1675,7 +1585,7 @@
1675	1585	{
1676	1586	struct qed_ilt_client_cfg *clients;
1677	1587	struct qed_cxt_mngr *p_mngr;
1678		- struct qed_dma_mem *p_shdw;
	1588	+ struct phys_mem_desc *p_shdw;
1679	1589	u32 line, rt_offst, i;
1680	1590
1681	1591	qed_ilt_bounds_init(p_hwfn);
..	..	@@ -1700,15 +1610,15 @@
1700	1610	/** p_virt could be NULL incase of dynamic
1701	1611	* allocation
1702	1612	*/
1703		- if (p_shdw[line].p_virt) {
	1613	+ if (p_shdw[line].virt_addr) {
1704	1614	SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1705	1615	SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1706		- (p_shdw[line].p_phys >> 12));
	1616	+ (p_shdw[line].phys_addr >> 12));
1707	1617
1708	1618	DP_VERBOSE(p_hwfn, QED_MSG_ILT,
1709	1619	"Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n",
1710	1620	rt_offst, line, i,
1711		- (u64)(p_shdw[line].p_phys >> 12));
	1621	+ (u64)(p_shdw[line].phys_addr >> 12));
1712	1622	}
1713	1623
1714	1624	STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
..	..	@@ -1737,9 +1647,9 @@
1737	1647	ilog2(rounded_conn_num));
1738	1648
1739	1649	STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1740		- p_hwfn->p_cxt_mngr->first_free);
	1650	+ p_hwfn->p_cxt_mngr->src_t2.first_free);
1741	1651	STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1742		- p_hwfn->p_cxt_mngr->last_free);
	1652	+ p_hwfn->p_cxt_mngr->src_t2.last_free);
1743	1653	}
1744	1654
1745	1655	/* Timers PF */
..	..	@@ -2051,10 +1961,10 @@
2051	1961	line = p_info->iid / cxts_per_p;
2052	1962
2053	1963	/* Make sure context is allocated (dynamic allocation) */
2054		- if (!p_mngr->ilt_shadow[line].p_virt)
	1964	+ if (!p_mngr->ilt_shadow[line].virt_addr)
2055	1965	return -EINVAL;
2056	1966
2057		- p_info->p_cxt = p_mngr->ilt_shadow[line].p_virt +
	1967	+ p_info->p_cxt = p_mngr->ilt_shadow[line].virt_addr +
2058	1968	p_info->iid % cxts_per_p * conn_cxt_size;
2059	1969
2060	1970	DP_VERBOSE(p_hwfn, (QED_MSG_ILT \| QED_MSG_CXT),
..	..	@@ -2068,10 +1978,8 @@
2068	1978	struct qed_rdma_pf_params *p_params,
2069	1979	u32 num_tasks)
2070	1980	{
2071		- u32 num_cons, num_qps, num_srqs;
	1981	+ u32 num_cons, num_qps;
2072	1982	enum protocol_type proto;
2073		-
2074		- num_srqs = min_t(u32, QED_RDMA_MAX_SRQS, p_params->num_srqs);
2075	1983
2076	1984	if (p_hwfn->mcp_info->func_info.protocol == QED_PCI_ETH_RDMA) {
2077	1985	DP_VERBOSE(p_hwfn, QED_MSG_SP,
..	..	@@ -2095,6 +2003,8 @@
2095	2003	}
2096	2004
2097	2005	if (num_cons && num_tasks) {
	2006	+ u32 num_srqs, num_xrc_srqs;
	2007	+
2098	2008	qed_cxt_set_proto_cid_count(p_hwfn, proto, num_cons, 0);
2099	2009
2100	2010	/* Deliberatly passing ROCE for tasks id. This is because
..	..	@@ -2103,7 +2013,13 @@
2103	2013	qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE,
2104	2014	QED_CXT_ROCE_TID_SEG, 1,
2105	2015	num_tasks, false);
2106		- qed_cxt_set_srq_count(p_hwfn, num_srqs);
	2016	+
	2017	+ num_srqs = min_t(u32, QED_RDMA_MAX_SRQS, p_params->num_srqs);
	2018	+
	2019	+ /* XRC SRQs populate a single ILT page */
	2020	+ num_xrc_srqs = qed_cxt_xrc_srqs_per_page(p_hwfn);
	2021	+
	2022	+ qed_cxt_set_srq_count(p_hwfn, num_srqs, num_xrc_srqs);
2107	2023	} else {
2108	2024	DP_INFO(p_hwfn->cdev,
2109	2025	"RDMA personality used without setting params!\n");
..	..	@@ -2130,17 +2046,18 @@
2130	2046	rdma_tasks);
2131	2047	/* no need for break since RoCE coexist with Ethernet */
2132	2048	}
	2049	+ fallthrough;
2133	2050	case QED_PCI_ETH:
2134	2051	{
2135	2052	struct qed_eth_pf_params *p_params =
2136	2053	&p_hwfn->pf_params.eth_pf_params;
2137	2054
2138		- if (!p_params->num_vf_cons)
2139		- p_params->num_vf_cons =
2140		- ETH_PF_PARAMS_VF_CONS_DEFAULT;
2141		- qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2142		- p_params->num_cons,
2143		- p_params->num_vf_cons);
	2055	+ if (!p_params->num_vf_cons)
	2056	+ p_params->num_vf_cons =
	2057	+ ETH_PF_PARAMS_VF_CONS_DEFAULT;
	2058	+ qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
	2059	+ p_params->num_cons,
	2060	+ p_params->num_vf_cons);
2144	2061	p_hwfn->p_cxt_mngr->arfs_count = p_params->num_arfs_filters;
2145	2062	break;
2146	2063	}
..	..	@@ -2234,7 +2151,7 @@
2234	2151	for (i = 0; i < total_lines; i++) {
2235	2152	shadow_line = i + p_fl_seg->start_line -
2236	2153	p_hwfn->p_cxt_mngr->pf_start_line;
2237		- p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
	2154	+ p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].virt_addr;
2238	2155	}
2239	2156	p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
2240	2157	p_fl_seg->real_size_in_page;
..	..	@@ -2253,12 +2170,14 @@
2253	2170	enum qed_cxt_elem_type elem_type, u32 iid)
2254	2171	{
2255	2172	u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
	2173	+ struct tdif_task_context *tdif_context;
2256	2174	struct qed_ilt_client_cfg *p_cli;
2257	2175	struct qed_ilt_cli_blk *p_blk;
2258	2176	struct qed_ptt *p_ptt;
2259	2177	dma_addr_t p_phys;
2260	2178	u64 ilt_hw_entry;
2261	2179	void *p_virt;
	2180	+ u32 flags1;
2262	2181	int rc = 0;
2263	2182
2264	2183	switch (elem_type) {
..	..	@@ -2268,8 +2187,15 @@
2268	2187	p_blk = &p_cli->pf_blks[CDUC_BLK];
2269	2188	break;
2270	2189	case QED_ELEM_SRQ:
	2190	+ /* The first ILT page is not used for regular SRQs. Skip it. */
	2191	+ iid += p_hwfn->p_cxt_mngr->xrc_srq_count;
2271	2192	p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2272	2193	elem_size = SRQ_CXT_SIZE;
	2194	+ p_blk = &p_cli->pf_blks[SRQ_BLK];
	2195	+ break;
	2196	+ case QED_ELEM_XRC_SRQ:
	2197	+ p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
	2198	+ elem_size = XRC_SRQ_CXT_SIZE;
2273	2199	p_blk = &p_cli->pf_blks[SRQ_BLK];
2274	2200	break;
2275	2201	case QED_ELEM_TASK:
..	..	@@ -2296,7 +2222,7 @@
2296	2222
2297	2223	mutex_lock(&p_hwfn->p_cxt_mngr->mutex);
2298	2224
2299		- if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
	2225	+ if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].virt_addr)
2300	2226	goto out0;
2301	2227
2302	2228	p_ptt = qed_ptt_acquire(p_hwfn);
..	..	@@ -2307,9 +2233,9 @@
2307	2233	goto out0;
2308	2234	}
2309	2235
2310		- p_virt = dma_zalloc_coherent(&p_hwfn->cdev->pdev->dev,
2311		- p_blk->real_size_in_page, &p_phys,
2312		- GFP_KERNEL);
	2236	+ p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
	2237	+ p_blk->real_size_in_page, &p_phys,
	2238	+ GFP_KERNEL);
2313	2239	if (!p_virt) {
2314	2240	rc = -ENOMEM;
2315	2241	goto out1;
..	..	@@ -2328,14 +2254,18 @@
2328	2254
2329	2255	for (elem_i = 0; elem_i < elems_per_p; elem_i++) {
2330	2256	elem = (union type1_task_context *)elem_start;
2331		- SET_FIELD(elem->roce_ctx.tdif_context.flags1,
2332		- TDIF_TASK_CONTEXT_REF_TAG_MASK, 0xf);
	2257	+ tdif_context = &elem->roce_ctx.tdif_context;
	2258	+
	2259	+ flags1 = le32_to_cpu(tdif_context->flags1);
	2260	+ SET_FIELD(flags1, TDIF_TASK_CONTEXT_REF_TAG_MASK, 0xf);
	2261	+ tdif_context->flags1 = cpu_to_le32(flags1);
	2262	+
2333	2263	elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn);
2334	2264	}
2335	2265	}
2336	2266
2337		- p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2338		- p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
	2267	+ p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].virt_addr = p_virt;
	2268	+ p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].phys_addr = p_phys;
2339	2269	p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2340	2270	p_blk->real_size_in_page;
2341	2271
..	..	@@ -2345,13 +2275,14 @@
2345	2275
2346	2276	ilt_hw_entry = 0;
2347	2277	SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2348		- SET_FIELD(ilt_hw_entry,
2349		- ILT_ENTRY_PHY_ADDR,
2350		- (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
	2278	+ SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
	2279	+ (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].phys_addr
	2280	+ >> 12));
2351	2281
2352	2282	/* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2353	2283	qed_dmae_host2grc(p_hwfn, p_ptt, (u64) (uintptr_t)&ilt_hw_entry,
2354		- reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 0);
	2284	+ reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
	2285	+ NULL);
2355	2286
2356	2287	if (elem_type == QED_ELEM_CXT) {
2357	2288	u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
..	..	@@ -2404,6 +2335,11 @@
2404	2335	elem_size = SRQ_CXT_SIZE;
2405	2336	p_blk = &p_cli->pf_blks[SRQ_BLK];
2406	2337	break;
	2338	+ case QED_ELEM_XRC_SRQ:
	2339	+ p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
	2340	+ elem_size = XRC_SRQ_CXT_SIZE;
	2341	+ p_blk = &p_cli->pf_blks[SRQ_BLK];
	2342	+ break;
2407	2343	case QED_ELEM_TASK:
2408	2344	p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2409	2345	elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
..	..	@@ -2433,16 +2369,16 @@
2433	2369	}
2434	2370
2435	2371	for (i = shadow_start_line; i < shadow_end_line; i++) {
2436		- if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
	2372	+ if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr)
2437	2373	continue;
2438	2374
2439	2375	dma_free_coherent(&p_hwfn->cdev->pdev->dev,
2440	2376	p_hwfn->p_cxt_mngr->ilt_shadow[i].size,
2441		- p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2442		- p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys);
	2377	+ p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr,
	2378	+ p_hwfn->p_cxt_mngr->ilt_shadow[i].phys_addr);
2443	2379
2444		- p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = NULL;
2445		- p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
	2380	+ p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr = NULL;
	2381	+ p_hwfn->p_cxt_mngr->ilt_shadow[i].phys_addr = 0;
2446	2382	p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2447	2383
2448	2384	/* compute absolute offset */
..	..	@@ -2457,7 +2393,7 @@
2457	2393	(u64) (uintptr_t) &ilt_hw_entry,
2458	2394	reg_offset,
2459	2395	sizeof(ilt_hw_entry) / sizeof(u32),
2460		- 0);
	2396	+ NULL);
2461	2397	}
2462	2398
2463	2399	qed_ptt_release(p_hwfn, p_ptt);
..	..	@@ -2490,8 +2426,12 @@
2490	2426	return rc;
2491	2427
2492	2428	/* Free TSDM CXT */
2493		- rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_SRQ, 0,
2494		- qed_cxt_get_srq_count(p_hwfn));
	2429	+ rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_XRC_SRQ, 0,
	2430	+ p_hwfn->p_cxt_mngr->xrc_srq_count);
	2431	+
	2432	+ rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_SRQ,
	2433	+ p_hwfn->p_cxt_mngr->xrc_srq_count,
	2434	+ p_hwfn->p_cxt_mngr->srq_count);
2495	2435
2496	2436	return rc;
2497	2437	}
..	..	@@ -2546,8 +2486,76 @@
2546	2486
2547	2487	ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2548	2488	p_mngr->pf_start_line;
2549		- pp_task_ctx = (u8 )p_mngr->ilt_shadow[ilt_idx].p_virt +
	2489	+ pp_task_ctx = (u8 )p_mngr->ilt_shadow[ilt_idx].virt_addr +
2550	2490	(tid % num_tids_per_block) * tid_size;
2551	2491
2552	2492	return 0;
2553	2493	}
	2494	+
	2495	+static u16 qed_blk_calculate_pages(struct qed_ilt_cli_blk *p_blk)
	2496	+{
	2497	+ if (p_blk->real_size_in_page == 0)
	2498	+ return 0;
	2499	+
	2500	+ return DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
	2501	+}
	2502	+
	2503	+u16 qed_get_cdut_num_pf_init_pages(struct qed_hwfn *p_hwfn)
	2504	+{
	2505	+ struct qed_ilt_client_cfg *p_cli;
	2506	+ struct qed_ilt_cli_blk *p_blk;
	2507	+ u16 i, pages = 0;
	2508	+
	2509	+ p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
	2510	+ for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
	2511	+ p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
	2512	+ pages += qed_blk_calculate_pages(p_blk);
	2513	+ }
	2514	+
	2515	+ return pages;
	2516	+}
	2517	+
	2518	+u16 qed_get_cdut_num_vf_init_pages(struct qed_hwfn *p_hwfn)
	2519	+{
	2520	+ struct qed_ilt_client_cfg *p_cli;
	2521	+ struct qed_ilt_cli_blk *p_blk;
	2522	+ u16 i, pages = 0;
	2523	+
	2524	+ p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
	2525	+ for (i = 0; i < NUM_TASK_VF_SEGMENTS; i++) {
	2526	+ p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(i, VF)];
	2527	+ pages += qed_blk_calculate_pages(p_blk);
	2528	+ }
	2529	+
	2530	+ return pages;
	2531	+}
	2532	+
	2533	+u16 qed_get_cdut_num_pf_work_pages(struct qed_hwfn *p_hwfn)
	2534	+{
	2535	+ struct qed_ilt_client_cfg *p_cli;
	2536	+ struct qed_ilt_cli_blk *p_blk;
	2537	+ u16 i, pages = 0;
	2538	+
	2539	+ p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
	2540	+ for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
	2541	+ p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
	2542	+ pages += qed_blk_calculate_pages(p_blk);
	2543	+ }
	2544	+
	2545	+ return pages;
	2546	+}
	2547	+
	2548	+u16 qed_get_cdut_num_vf_work_pages(struct qed_hwfn *p_hwfn)
	2549	+{
	2550	+ struct qed_ilt_client_cfg *p_cli;
	2551	+ struct qed_ilt_cli_blk *p_blk;
	2552	+ u16 pages = 0, i;
	2553	+
	2554	+ p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
	2555	+ for (i = 0; i < NUM_TASK_VF_SEGMENTS; i++) {
	2556	+ p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(i)];
	2557	+ pages += qed_blk_calculate_pages(p_blk);
	2558	+ }
	2559	+
	2560	+ return pages;
	2561	+}