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2024-05-11 297b60346df8beafee954a0fd7c2d64f33f3b9bc 
 kernel/drivers/net/ethernet/qlogic/qed/qed.h
....@@ -1,33 +1,7 @@
1
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
12 /* QLogic qed NIC Driver
23  * Copyright (c) 2015-2017  QLogic Corporation
3
- *
4
- * This software is available to you under a choice of one of two
5
- * licenses.  You may choose to be licensed under the terms of the GNU
6
- * General Public License (GPL) Version 2, available from the file
7
- * COPYING in the main directory of this source tree, or the
8
- * OpenIB.org BSD license below:
9
- *
10
- *     Redistribution and use in source and binary forms, with or
11
- *     without modification, are permitted provided that the following
12
- *     conditions are met:
13
- *
14
- *      - Redistributions of source code must retain the above
15
- *        copyright notice, this list of conditions and the following
16
- *        disclaimer.
17
- *
18
- *      - Redistributions in binary form must reproduce the above
19
- *        copyright notice, this list of conditions and the following
20
- *        disclaimer in the documentation and /or other materials
21
- *        provided with the distribution.
22
- *
23
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30
- * SOFTWARE.
4
+ * Copyright (c) 2019-2020 Marvell International Ltd.
315  */
326 
337 #ifndef _QED_H
....@@ -53,7 +27,7 @@
5327 extern const struct qed_common_ops qed_common_ops_pass;
5428 
5529 #define QED_MAJOR_VERSION		8
56
-#define QED_MINOR_VERSION		33
30
+#define QED_MINOR_VERSION		37
5731 #define QED_REVISION_VERSION		0
5832 #define QED_ENGINEERING_VERSION		20
5933 
....@@ -140,6 +114,7 @@
140114 struct qed_sb_sp_info;
141115 struct qed_ll2_info;
142116 struct qed_mcp_info;
117
+struct qed_llh_info;
143118 
144119 struct qed_rt_data {
145120 	u32	*init_val;
....@@ -252,7 +227,8 @@
252227 	QED_VLAN,
253228 	QED_RDMA_CNQ_RAM,
254229 	QED_ILT,
255
-	QED_LL2_QUEUE,
230
+	QED_LL2_RAM_QUEUE,
231
+	QED_LL2_CTX_QUEUE,
256232 	QED_CMDQS_CQS,
257233 	QED_RDMA_STATS_QUEUE,
258234 	QED_BDQ,
....@@ -269,20 +245,6 @@
269245 	QED_MAX_FEATURES,
270246 };
271247 
272
-enum QED_PORT_MODE {
273
-	QED_PORT_MODE_DE_2X40G,
274
-	QED_PORT_MODE_DE_2X50G,
275
-	QED_PORT_MODE_DE_1X100G,
276
-	QED_PORT_MODE_DE_4X10G_F,
277
-	QED_PORT_MODE_DE_4X10G_E,
278
-	QED_PORT_MODE_DE_4X20G,
279
-	QED_PORT_MODE_DE_1X40G,
280
-	QED_PORT_MODE_DE_2X25G,
281
-	QED_PORT_MODE_DE_1X25G,
282
-	QED_PORT_MODE_DE_4X25G,
283
-	QED_PORT_MODE_DE_2X10G,
284
-};
285
-
286248 enum qed_dev_cap {
287249 	QED_DEV_CAP_ETH,
288250 	QED_DEV_CAP_FCOE,
....@@ -296,50 +258,57 @@
296258 	QED_WOL_SUPPORT_PME,
297259 };
298260 
261
+enum qed_db_rec_exec {
262
+	DB_REC_DRY_RUN,
263
+	DB_REC_REAL_DEAL,
264
+	DB_REC_ONCE,
265
+};
266
+
299267 struct qed_hw_info {
300268 	/* PCI personality */
301
-	enum qed_pci_personality personality;
302
-#define QED_IS_RDMA_PERSONALITY(dev)			    \
303
-	((dev)->hw_info.personality == QED_PCI_ETH_ROCE ||  \
304
-	 (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
269
+	enum qed_pci_personality	personality;
270
+#define QED_IS_RDMA_PERSONALITY(dev)					\
271
+	((dev)->hw_info.personality == QED_PCI_ETH_ROCE ||		\
272
+	 (dev)->hw_info.personality == QED_PCI_ETH_IWARP ||		\
305273 	 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
306
-#define QED_IS_ROCE_PERSONALITY(dev)			   \
307
-	((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
274
+#define QED_IS_ROCE_PERSONALITY(dev)					\
275
+	((dev)->hw_info.personality == QED_PCI_ETH_ROCE ||		\
308276 	 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
309
-#define QED_IS_IWARP_PERSONALITY(dev)			    \
310
-	((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
277
+#define QED_IS_IWARP_PERSONALITY(dev)					\
278
+	((dev)->hw_info.personality == QED_PCI_ETH_IWARP ||		\
311279 	 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
312
-#define QED_IS_L2_PERSONALITY(dev)		      \
313
-	((dev)->hw_info.personality == QED_PCI_ETH || \
280
+#define QED_IS_L2_PERSONALITY(dev)					\
281
+	((dev)->hw_info.personality == QED_PCI_ETH ||			\
314282 	 QED_IS_RDMA_PERSONALITY(dev))
315
-#define QED_IS_FCOE_PERSONALITY(dev) \
283
+#define QED_IS_FCOE_PERSONALITY(dev)					\
316284 	((dev)->hw_info.personality == QED_PCI_FCOE)
317
-#define QED_IS_ISCSI_PERSONALITY(dev) \
285
+#define QED_IS_ISCSI_PERSONALITY(dev)					\
318286 	((dev)->hw_info.personality == QED_PCI_ISCSI)
319287 
320288 	/* Resource Allocation scheme results */
321289 	u32				resc_start[QED_MAX_RESC];
322290 	u32				resc_num[QED_MAX_RESC];
323
-	u32				feat_num[QED_MAX_FEATURES];
291
+#define RESC_START(_p_hwfn, resc)	((_p_hwfn)->hw_info.resc_start[resc])
292
+#define RESC_NUM(_p_hwfn, resc)		((_p_hwfn)->hw_info.resc_num[resc])
293
+#define RESC_END(_p_hwfn, resc)		(RESC_START(_p_hwfn, resc) +	\
294
+					 RESC_NUM(_p_hwfn, resc))
324295 
325
-#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
326
-#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
327
-#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
328
-				 RESC_NUM(_p_hwfn, resc))
329
-#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
296
+	u32				feat_num[QED_MAX_FEATURES];
297
+#define FEAT_NUM(_p_hwfn, resc)		((_p_hwfn)->hw_info.feat_num[resc])
330298 
331299 	/* Amount of traffic classes HW supports */
332
-	u8 num_hw_tc;
300
+	u8				num_hw_tc;
333301 
334302 	/* Amount of TCs which should be active according to DCBx or upper
335303 	 * layer driver configuration.
336304 	 */
337
-	u8 num_active_tc;
305
+	u8				num_active_tc;
306
+
338307 	u8				offload_tc;
339308 	bool				offload_tc_set;
340309 
341310 	bool				multi_tc_roce_en;
342
-#define IS_QED_MULTI_TC_ROCE(p_hwfn) (((p_hwfn)->hw_info.multi_tc_roce_en))
311
+#define IS_QED_MULTI_TC_ROCE(p_hwfn)	((p_hwfn)->hw_info.multi_tc_roce_en)
343312 
344313 	u32				concrete_fid;
345314 	u16				opaque_fid;
....@@ -354,12 +323,11 @@
354323 
355324 	struct qed_igu_info		*p_igu_info;
356325 
357
-	u32				port_mode;
358326 	u32				hw_mode;
359
-	unsigned long		device_capabilities;
327
+	unsigned long			device_capabilities;
360328 	u16				mtu;
361329 
362
-	enum qed_wol_support b_wol_support;
330
+	enum qed_wol_support		b_wol_support;
363331 };
364332 
365333 /* maximun size of read/write commands (HW limit) */
....@@ -425,6 +393,18 @@
425393 	u8 num_pf_rls;
426394 };
427395 
396
+#define QED_OVERFLOW_BIT	1
397
+
398
+struct qed_db_recovery_info {
399
+	struct list_head list;
400
+
401
+	/* Lock to protect the doorbell recovery mechanism list */
402
+	spinlock_t lock;
403
+	bool dorq_attn;
404
+	u32 db_recovery_counter;
405
+	unsigned long overflow;
406
+};
407
+
428408 struct storm_stats {
429409 	u32     address;
430410 	u32     len;
....@@ -442,6 +422,8 @@
442422 	const u8		*modes_tree_buf;
443423 	union init_op		*init_ops;
444424 	const u32		*arr_data;
425
+	const u32		*fw_overlays;
426
+	u32			fw_overlays_len;
445427 	u32			init_ops_size;
446428 };
447429 
....@@ -478,6 +460,9 @@
478460 
479461 	/* Allow DSCP to TC mapping */
480462 	QED_MF_DSCP_TO_TC_MAP,
463
+
464
+	/* Do not insert a vlan tag with id 0 */
465
+	QED_MF_DONT_ADD_VLAN0_TAG,
481466 };
482467 
483468 enum qed_ufp_mode {
....@@ -509,6 +494,23 @@
509494 	bool valid;
510495 };
511496 
497
+enum qed_hsi_def_type {
498
+	QED_HSI_DEF_MAX_NUM_VFS,
499
+	QED_HSI_DEF_MAX_NUM_L2_QUEUES,
500
+	QED_HSI_DEF_MAX_NUM_PORTS,
501
+	QED_HSI_DEF_MAX_SB_PER_PATH,
502
+	QED_HSI_DEF_MAX_NUM_PFS,
503
+	QED_HSI_DEF_MAX_NUM_VPORTS,
504
+	QED_HSI_DEF_NUM_ETH_RSS_ENGINE,
505
+	QED_HSI_DEF_MAX_QM_TX_QUEUES,
506
+	QED_HSI_DEF_NUM_PXP_ILT_RECORDS,
507
+	QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS,
508
+	QED_HSI_DEF_MAX_QM_GLOBAL_RLS,
509
+	QED_HSI_DEF_MAX_PBF_CMD_LINES,
510
+	QED_HSI_DEF_MAX_BTB_BLOCKS,
511
+	QED_NUM_HSI_DEFS
512
+};
513
+
512514 #define DRV_MODULE_VERSION		      \
513515 	__stringify(QED_MAJOR_VERSION) "."    \
514516 	__stringify(QED_MINOR_VERSION) "."    \
....@@ -522,6 +524,7 @@
522524 
523525 enum qed_slowpath_wq_flag {
524526 	QED_SLOWPATH_MFW_TLV_REQ,
527
+	QED_SLOWPATH_PERIODIC_DB_REC,
525528 };
526529 
527530 struct qed_hwfn {
....@@ -539,7 +542,6 @@
539542 	u8				dp_level;
540543 	char				name[NAME_SIZE];
541544 
542
-	bool				first_on_engine;
543545 	bool				hw_init_done;
544546 
545547 	u8				num_funcs_on_engine;
....@@ -570,7 +572,7 @@
570572 	struct qed_consq		*p_consq;
571573 
572574 	/* Slow-Path definitions */
573
-	struct tasklet_struct		*sp_dpc;
575
+	struct tasklet_struct		sp_dpc;
574576 	bool				b_sp_dpc_enabled;
575577 
576578 	struct qed_ptt			*p_main_ptt;
....@@ -623,6 +625,8 @@
623625 	void				*unzip_buf;
624626 
625627 	struct dbg_tools_data		dbg_info;
628
+	void				*dbg_user_info;
629
+	struct virt_mem_desc		dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE];
626630 
627631 	/* PWM region specific data */
628632 	u16				wid_count;
....@@ -639,9 +643,13 @@
639643 	/* L2-related */
640644 	struct qed_l2_info *p_l2_info;
641645 
646
+	/* Mechanism for recovering from doorbell drop */
647
+	struct qed_db_recovery_info db_recovery_info;
648
+
642649 	/* Nvm images number and attributes */
643650 	struct qed_nvm_image_info nvm_info;
644651 
652
+	struct phys_mem_desc *fw_overlay_mem;
645653 	struct qed_ptt *p_arfs_ptt;
646654 
647655 	struct qed_simd_fp_handler	simd_proto_handler[64];
....@@ -651,11 +659,12 @@
651659 	struct delayed_work iov_task;
652660 	unsigned long iov_task_flags;
653661 #endif
654
-
655
-	struct z_stream_s		*stream;
662
+	struct z_stream_s *stream;
663
+	bool slowpath_wq_active;
656664 	struct workqueue_struct *slowpath_wq;
657665 	struct delayed_work slowpath_task;
658666 	unsigned long slowpath_task_flags;
667
+	u32 periodic_db_rec_count;
659668 };
660669 
661670 struct pci_params {
....@@ -691,49 +700,46 @@
691700 	u32 dumped_dwords;
692701 };
693702 
694
-struct qed_dbg_params {
695
-	struct qed_dbg_feature features[DBG_FEATURE_NUM];
696
-	u8 engine_for_debug;
697
-	bool print_data;
698
-};
699
-
700703 struct qed_dev {
701
-	u32	dp_module;
702
-	u8	dp_level;
703
-	char	name[NAME_SIZE];
704
+	u32				dp_module;
705
+	u8				dp_level;
706
+	char				name[NAME_SIZE];
704707 
705
-	enum	qed_dev_type type;
706
-/* Translate type/revision combo into the proper conditions */
707
-#define QED_IS_BB(dev)  ((dev)->type == QED_DEV_TYPE_BB)
708
-#define QED_IS_BB_B0(dev)       (QED_IS_BB(dev) && \
709
-				 CHIP_REV_IS_B0(dev))
710
-#define QED_IS_AH(dev)  ((dev)->type == QED_DEV_TYPE_AH)
711
-#define QED_IS_K2(dev)  QED_IS_AH(dev)
708
+	enum qed_dev_type		type;
709
+	/* Translate type/revision combo into the proper conditions */
710
+#define QED_IS_BB(dev)			((dev)->type == QED_DEV_TYPE_BB)
711
+#define QED_IS_BB_B0(dev)		(QED_IS_BB(dev) && CHIP_REV_IS_B0(dev))
712
+#define QED_IS_AH(dev)			((dev)->type == QED_DEV_TYPE_AH)
713
+#define QED_IS_K2(dev)			QED_IS_AH(dev)
714
+#define QED_IS_E4(dev)			(QED_IS_BB(dev) || QED_IS_AH(dev))
715
+#define QED_IS_E5(dev)			((dev)->type == QED_DEV_TYPE_E5)
712716 
713
-	u16	vendor_id;
714
-	u16	device_id;
715
-#define QED_DEV_ID_MASK		0xff00
716
-#define QED_DEV_ID_MASK_BB	0x1600
717
-#define QED_DEV_ID_MASK_AH	0x8000
717
+	u16				vendor_id;
718718 
719
-	u16	chip_num;
720
-#define CHIP_NUM_MASK                   0xffff
721
-#define CHIP_NUM_SHIFT                  16
719
+	u16				device_id;
720
+#define QED_DEV_ID_MASK			0xff00
721
+#define QED_DEV_ID_MASK_BB		0x1600
722
+#define QED_DEV_ID_MASK_AH		0x8000
722723 
723
-	u16	chip_rev;
724
-#define CHIP_REV_MASK                   0xf
725
-#define CHIP_REV_SHIFT                  12
726
-#define CHIP_REV_IS_B0(_cdev)   ((_cdev)->chip_rev == 1)
724
+	u16				chip_num;
725
+#define CHIP_NUM_MASK			0xffff
726
+#define CHIP_NUM_SHIFT			16
727
+
728
+	u16				chip_rev;
729
+#define CHIP_REV_MASK			0xf
730
+#define CHIP_REV_SHIFT			12
731
+#define CHIP_REV_IS_B0(_cdev)		((_cdev)->chip_rev == 1)
727732 
728733 	u16				chip_metal;
729
-#define CHIP_METAL_MASK                 0xff
730
-#define CHIP_METAL_SHIFT                4
734
+#define CHIP_METAL_MASK			0xff
735
+#define CHIP_METAL_SHIFT		4
731736 
732737 	u16				chip_bond_id;
733
-#define CHIP_BOND_ID_MASK               0xf
734
-#define CHIP_BOND_ID_SHIFT              0
738
+#define CHIP_BOND_ID_MASK		0xf
739
+#define CHIP_BOND_ID_SHIFT		0
735740 
736741 	u8				num_engines;
742
+	u8				num_ports;
737743 	u8				num_ports_in_engine;
738744 	u8				num_funcs_in_port;
739745 
....@@ -767,12 +773,17 @@
767773 	u8				cache_shift;
768774 
769775 	/* Init */
770
-	const struct iro		*iro_arr;
771
-#define IRO (p_hwfn->cdev->iro_arr)
776
+	const u32 *iro_arr;
777
+#define IRO ((const struct iro *)p_hwfn->cdev->iro_arr)
772778 
773779 	/* HW functions */
774780 	u8				num_hwfns;
775781 	struct qed_hwfn			hwfns[MAX_HWFNS_PER_DEVICE];
782
+
783
+	/* Engine affinity */
784
+	u8				l2_affin_hint;
785
+	u8				fir_affin;
786
+	u8				iwarp_affin;
776787 
777788 	/* SRIOV */
778789 	struct qed_hw_sriov_info *p_iov_info;
....@@ -785,7 +796,18 @@
785796 
786797 	u32				mcp_nvm_resp;
787798 
799
+	/* Recovery */
800
+	bool recov_in_prog;
801
+
802
+	/* Indicates whether should prevent attentions from being reasserted */
803
+	bool attn_clr_en;
804
+
805
+	/* LLH info */
806
+	u8 ppfid_bitmap;
807
+	struct qed_llh_info *p_llh_info;
808
+
788809 	/* Linux specific here */
810
+	struct qed_dev_info		common_dev_info;
789811 	struct  qede_dev		*edev;
790812 	struct  pci_dev			*pdev;
791813 	u32 flags;
....@@ -809,31 +831,57 @@
809831 	} protocol_ops;
810832 	void				*ops_cookie;
811833 
812
-	struct qed_dbg_params		dbg_params;
813
-
814834 #ifdef CONFIG_QED_LL2
815835 	struct qed_cb_ll2_info		*ll2;
816836 	u8				ll2_mac_address[ETH_ALEN];
817837 #endif
838
+	struct qed_dbg_feature dbg_features[DBG_FEATURE_NUM];
839
+	u8 engine_for_debug;
840
+	bool disable_ilt_dump;
841
+	bool				dbg_bin_dump;
842
+
818843 	DECLARE_HASHTABLE(connections, 10);
819844 	const struct firmware		*firmware;
845
+
846
+	bool print_dbg_data;
820847 
821848 	u32 rdma_max_sge;
822849 	u32 rdma_max_inline;
823850 	u32 rdma_max_srq_sge;
824851 	u16 tunn_feature_mask;
852
+
853
+	bool				iwarp_cmt;
825854 };
826855 
827
-#define NUM_OF_VFS(dev)         (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \
828
-						: MAX_NUM_VFS_K2)
829
-#define NUM_OF_L2_QUEUES(dev)   (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
830
-						: MAX_NUM_L2_QUEUES_K2)
831
-#define NUM_OF_PORTS(dev)       (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \
832
-						: MAX_NUM_PORTS_K2)
833
-#define NUM_OF_SBS(dev)         (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
834
-						: MAX_SB_PER_PATH_K2)
835
-#define NUM_OF_ENG_PFS(dev)     (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \
836
-						: MAX_NUM_PFS_K2)
856
+u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type);
857
+
858
+#define NUM_OF_VFS(dev)	\
859
+	qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VFS)
860
+#define NUM_OF_L2_QUEUES(dev) \
861
+	qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_L2_QUEUES)
862
+#define NUM_OF_PORTS(dev) \
863
+	qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PORTS)
864
+#define NUM_OF_SBS(dev)	\
865
+	qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_SB_PER_PATH)
866
+#define NUM_OF_ENG_PFS(dev) \
867
+	qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PFS)
868
+#define NUM_OF_VPORTS(dev) \
869
+	qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VPORTS)
870
+#define NUM_OF_RSS_ENGINES(dev)	\
871
+	qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_ETH_RSS_ENGINE)
872
+#define NUM_OF_QM_TX_QUEUES(dev) \
873
+	qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_TX_QUEUES)
874
+#define NUM_OF_PXP_ILT_RECORDS(dev) \
875
+	qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_PXP_ILT_RECORDS)
876
+#define NUM_OF_RDMA_STATISTIC_COUNTERS(dev) \
877
+	qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS)
878
+#define NUM_OF_QM_GLOBAL_RLS(dev) \
879
+	qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_GLOBAL_RLS)
880
+#define NUM_OF_PBF_CMD_LINES(dev) \
881
+	qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_PBF_CMD_LINES)
882
+#define NUM_OF_BTB_BLOCKS(dev) \
883
+	qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_BTB_BLOCKS)
884
+
837885 
838886 /**
839887  * @brief qed_concrete_to_sw_fid - get the sw function id from
....@@ -870,11 +918,18 @@
870918 
871919 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
872920 int qed_device_num_engines(struct qed_dev *cdev);
873
-int qed_device_get_port_id(struct qed_dev *cdev);
874921 void qed_set_fw_mac_addr(__le16 *fw_msb,
875922 			 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac);
876923 
877924 #define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])
925
+#define QED_IS_CMT(dev)		((dev)->num_hwfns > 1)
926
+/* Macros for getting the engine-affinitized hwfn (FIR: fcoe,iscsi,roce) */
927
+#define QED_FIR_AFFIN_HWFN(dev)		(&(dev)->hwfns[dev->fir_affin])
928
+#define QED_IWARP_AFFIN_HWFN(dev)       (&(dev)->hwfns[dev->iwarp_affin])
929
+#define QED_AFFIN_HWFN(dev)				   \
930
+	(QED_IS_IWARP_PERSONALITY(QED_LEADING_HWFN(dev)) ? \
931
+	 QED_IWARP_AFFIN_HWFN(dev) : QED_FIR_AFFIN_HWFN(dev))
932
+#define QED_AFFIN_HWFN_IDX(dev) (IS_LEAD_HWFN(QED_AFFIN_HWFN(dev)) ? 0 : 1)
878933 
879934 /* Flags for indication of required queues */
880935 #define PQ_FLAGS_RLS    (BIT(0))
....@@ -894,7 +949,10 @@
894949 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc);
895950 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc);
896951 
897
-#define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])
952
+/* doorbell recovery mechanism */
953
+void qed_db_recovery_dp(struct qed_hwfn *p_hwfn);
954
+void qed_db_recovery_execute(struct qed_hwfn *p_hwfn);
955
+bool qed_edpm_enabled(struct qed_hwfn *p_hwfn);
898956 
899957 /* Other Linux specific common definitions */
900958 #define DP_NAME(cdev) ((cdev)->name)
....@@ -911,13 +969,22 @@
911969 	writel((u32)val, (void __iomem *)((u8 __iomem *)\
912970 					  (cdev->doorbells) + (db_addr)))
913971 
972
+#define MFW_PORT(_p_hwfn)       ((_p_hwfn)->abs_pf_id %			  \
973
+				  qed_device_num_ports((_p_hwfn)->cdev))
974
+int qed_device_num_ports(struct qed_dev *cdev);
975
+
914976 /* Prototypes */
915977 int qed_fill_dev_info(struct qed_dev *cdev,
916978 		      struct qed_dev_info *dev_info);
917979 void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt);
980
+void qed_bw_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt);
918981 u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
919982 		   u32 input_len, u8 *input_buf,
920983 		   u32 max_size, u8 *unzip_buf);
984
+int qed_recovery_process(struct qed_dev *cdev);
985
+void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn);
986
+void qed_hw_error_occurred(struct qed_hwfn *p_hwfn,
987
+			   enum qed_hw_err_type err_type);
921988 void qed_get_protocol_stats(struct qed_dev *cdev,
922989 			    enum qed_mcp_protocol_type type,
923990 			    union qed_mcp_protocol_stats *stats);
....@@ -930,4 +997,6 @@
930997 			  union qed_mfw_tlv_data *tlv_data);
931998 
932999 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc);
1000
+
1001
+void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn);
9331002 #endif /* _QED_H */